1 /* 2 * Low-Level PCI Support for the SH7780 3 * 4 * Copyright (C) 2005 - 2009 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/types.h> 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/errno.h> 15 #include <linux/delay.h> 16 #include "pci-sh4.h" 17 18 extern u8 pci_cache_line_size; 19 20 static struct resource sh7785_io_resource = { 21 .name = "SH7785_IO", 22 .start = SH7780_PCI_IO_BASE, 23 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1, 24 .flags = IORESOURCE_IO 25 }; 26 27 static struct resource sh7785_mem_resource = { 28 .name = "SH7785_mem", 29 .start = SH7780_PCI_MEMORY_BASE, 30 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1, 31 .flags = IORESOURCE_MEM 32 }; 33 34 static struct pci_channel sh7780_pci_controller = { 35 .pci_ops = &sh4_pci_ops, 36 .mem_resource = &sh7785_mem_resource, 37 .mem_offset = 0x00000000, 38 .io_resource = &sh7785_io_resource, 39 .io_offset = 0x00000000, 40 }; 41 42 static struct sh4_pci_address_map sh7780_pci_map = { 43 .window0 = { 44 #if defined(CONFIG_32BIT) 45 .base = SH7780_32BIT_DDR_BASE_ADDR, 46 .size = 0x40000000, 47 #else 48 .base = SH7780_CS0_BASE_ADDR, 49 .size = 0x20000000, 50 #endif 51 }, 52 }; 53 54 static int __init sh7780_pci_init(void) 55 { 56 struct pci_channel *chan = &sh7780_pci_controller; 57 unsigned int id; 58 const char *type = NULL; 59 int ret; 60 u32 word; 61 62 printk(KERN_NOTICE "PCI: Starting intialization.\n"); 63 64 chan->reg_base = 0xfe040000; 65 66 /* Enable CPU access to the PCIC registers. */ 67 __raw_writel(PCIECR_ENBL, PCIECR); 68 69 id = __raw_readw(chan->reg_base + SH7780_PCIVID); 70 if (id != SH7780_VENDOR_ID) { 71 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id); 72 return -ENODEV; 73 } 74 75 id = __raw_readw(chan->reg_base + SH7780_PCIDID); 76 type = (id == SH7763_DEVICE_ID) ? "SH7763" : 77 (id == SH7780_DEVICE_ID) ? "SH7780" : 78 (id == SH7781_DEVICE_ID) ? "SH7781" : 79 (id == SH7785_DEVICE_ID) ? "SH7785" : 80 NULL; 81 if (unlikely(!type)) { 82 printk(KERN_ERR "PCI: Found an unsupported Renesas host " 83 "controller, device id 0x%04x.\n", id); 84 return -EINVAL; 85 } 86 87 printk(KERN_NOTICE "PCI: Found a Renesas %s host " 88 "controller, revision %d.\n", type, 89 __raw_readb(chan->reg_base + SH7780_PCIRID)); 90 91 if ((ret = sh4_pci_check_direct(chan)) != 0) 92 return ret; 93 94 /* 95 * Set the class and sub-class codes. 96 */ 97 __raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8, 98 chan->reg_base + SH7780_PCIBCC); 99 __raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff, 100 chan->reg_base + SH7780_PCISUB); 101 102 pci_cache_line_size = pci_read_reg(chan, SH7780_PCICLS) / 4; 103 104 /* 105 * Set IO and Mem windows to local address 106 * Make PCI and local address the same for easy 1 to 1 mapping 107 */ 108 pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0); 109 /* Set the values on window 0 PCI config registers */ 110 pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0); 111 pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0); 112 113 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM); 114 115 /* Set up standard PCI config registers */ 116 __raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS); 117 __raw_writew(0x0047, chan->reg_base + SH7780_PCICMD); 118 __raw_writew(0x1912, chan->reg_base + SH7780_PCISVID); 119 __raw_writew(0x0001, chan->reg_base + SH7780_PCISID); 120 121 __raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF); 122 123 /* Apply any last-minute PCIC fixups */ 124 pci_fixup_pcic(chan); 125 126 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0); 127 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0); 128 129 #ifdef CONFIG_32BIT 130 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2); 131 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); 132 #endif 133 134 /* Set IOBR for windows containing area specified in pci.h */ 135 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1), 136 SH7780_PCIIOBR); 137 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)), 138 SH7780_PCIIOBMR); 139 140 /* SH7780 init done, set central function init complete */ 141 /* use round robin mode to stop a device starving/overruning */ 142 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; 143 pci_write_reg(chan, word, SH4_PCICR); 144 145 __set_io_port_base(SH7780_PCI_IO_BASE); 146 147 register_pci_controller(chan); 148 149 return 0; 150 } 151 arch_initcall(sh7780_pci_init); 152