14862ec07SNicholas Beck /* 24862ec07SNicholas Beck * arch/sh/drivers/pci/fixups-sdk7780.c 34862ec07SNicholas Beck * 44862ec07SNicholas Beck * PCI fixups for the SDK7780SE03 54862ec07SNicholas Beck * 64862ec07SNicholas Beck * Copyright (C) 2003 Lineo uSolutions, Inc. 74862ec07SNicholas Beck * Copyright (C) 2004 - 2006 Paul Mundt 84862ec07SNicholas Beck * 94862ec07SNicholas Beck * This file is subject to the terms and conditions of the GNU General Public 104862ec07SNicholas Beck * License. See the file "COPYING" in the main directory of this archive 114862ec07SNicholas Beck * for more details. 124862ec07SNicholas Beck */ 134862ec07SNicholas Beck #include <linux/pci.h> 144862ec07SNicholas Beck #include "pci-sh4.h" 154862ec07SNicholas Beck #include <asm/io.h> 164862ec07SNicholas Beck 17*b8b47bfbSMagnus Damm int pci_fixup_pcic(struct pci_channel *chan) 184862ec07SNicholas Beck { 194862ec07SNicholas Beck ctrl_outl(0x00000001, SH7780_PCI_VCR2); 204862ec07SNicholas Beck 214862ec07SNicholas Beck /* Enable all interrupts, so we know what to fix */ 22*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR); 23*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM); 244862ec07SNicholas Beck 254862ec07SNicholas Beck /* Set up standard PCI config registers */ 26*b8b47bfbSMagnus Damm pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS); 27*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x0047, SH7780_PCICMD); 28*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x00, SH7780_PCIPIF); 29*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x00, SH7780_PCISUB); 30*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x06, SH7780_PCIBCC); 31*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x1912, SH7780_PCISVID); 32*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x0001, SH7780_PCISID); 334862ec07SNicholas Beck 34*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */ 35*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */ 36*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */ 374862ec07SNicholas Beck 38*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1); 39*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x00000000, SH7780_PCILAR1); 40*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x00000000, SH7780_PCILSR1); 414862ec07SNicholas Beck 42*b8b47bfbSMagnus Damm pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR); 434862ec07SNicholas Beck 444862ec07SNicholas Beck /* 454862ec07SNicholas Beck * Set the MBR so PCI address is one-to-one with window, 464862ec07SNicholas Beck * meaning all calls go straight through... use ifdef to 474862ec07SNicholas Beck * catch erroneous assumption. 484862ec07SNicholas Beck */ 49*b8b47bfbSMagnus Damm pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0); 50*b8b47bfbSMagnus Damm pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */ 514862ec07SNicholas Beck 524862ec07SNicholas Beck /* Set IOBR for window containing area specified in pci.h */ 53*b8b47bfbSMagnus Damm pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), 54*b8b47bfbSMagnus Damm SH7780_PCIIOBR); 55*b8b47bfbSMagnus Damm pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18), 56*b8b47bfbSMagnus Damm SH7780_PCIIOBMR); 574862ec07SNicholas Beck 58*b8b47bfbSMagnus Damm pci_write_reg(chan, 0xA5000C01, SH7780_PCICR); 594862ec07SNicholas Beck 604862ec07SNicholas Beck return 0; 614862ec07SNicholas Beck } 62