1*4862ec07SNicholas Beck /* 2*4862ec07SNicholas Beck * arch/sh/drivers/pci/fixups-sdk7780.c 3*4862ec07SNicholas Beck * 4*4862ec07SNicholas Beck * PCI fixups for the SDK7780SE03 5*4862ec07SNicholas Beck * 6*4862ec07SNicholas Beck * Copyright (C) 2003 Lineo uSolutions, Inc. 7*4862ec07SNicholas Beck * Copyright (C) 2004 - 2006 Paul Mundt 8*4862ec07SNicholas Beck * 9*4862ec07SNicholas Beck * This file is subject to the terms and conditions of the GNU General Public 10*4862ec07SNicholas Beck * License. See the file "COPYING" in the main directory of this archive 11*4862ec07SNicholas Beck * for more details. 12*4862ec07SNicholas Beck */ 13*4862ec07SNicholas Beck #include <linux/pci.h> 14*4862ec07SNicholas Beck #include "pci-sh4.h" 15*4862ec07SNicholas Beck #include <asm/io.h> 16*4862ec07SNicholas Beck 17*4862ec07SNicholas Beck int pci_fixup_pcic(void) 18*4862ec07SNicholas Beck { 19*4862ec07SNicholas Beck ctrl_outl(0x00000001, SH7780_PCI_VCR2); 20*4862ec07SNicholas Beck 21*4862ec07SNicholas Beck /* Enable all interrupts, so we know what to fix */ 22*4862ec07SNicholas Beck pci_write_reg(0x0000C3FF, SH7780_PCIIMR); 23*4862ec07SNicholas Beck pci_write_reg(0x0000380F, SH7780_PCIAINTM); 24*4862ec07SNicholas Beck 25*4862ec07SNicholas Beck /* Set up standard PCI config registers */ 26*4862ec07SNicholas Beck pci_write_reg(0xFB00, SH7780_PCISTATUS); 27*4862ec07SNicholas Beck pci_write_reg(0x0047, SH7780_PCICMD); 28*4862ec07SNicholas Beck pci_write_reg(0x00, SH7780_PCIPIF); 29*4862ec07SNicholas Beck pci_write_reg(0x00, SH7780_PCISUB); 30*4862ec07SNicholas Beck pci_write_reg(0x06, SH7780_PCIBCC); 31*4862ec07SNicholas Beck pci_write_reg(0x1912, SH7780_PCISVID); 32*4862ec07SNicholas Beck pci_write_reg(0x0001, SH7780_PCISID); 33*4862ec07SNicholas Beck 34*4862ec07SNicholas Beck pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */ 35*4862ec07SNicholas Beck pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */ 36*4862ec07SNicholas Beck pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */ 37*4862ec07SNicholas Beck 38*4862ec07SNicholas Beck pci_write_reg(0x00000000, SH7780_PCIMBAR1); 39*4862ec07SNicholas Beck pci_write_reg(0x00000000, SH7780_PCILAR1); 40*4862ec07SNicholas Beck pci_write_reg(0x00000000, SH7780_PCILSR1); 41*4862ec07SNicholas Beck 42*4862ec07SNicholas Beck pci_write_reg(0xAB000801, SH7780_PCIIBAR); 43*4862ec07SNicholas Beck 44*4862ec07SNicholas Beck /* 45*4862ec07SNicholas Beck * Set the MBR so PCI address is one-to-one with window, 46*4862ec07SNicholas Beck * meaning all calls go straight through... use ifdef to 47*4862ec07SNicholas Beck * catch erroneous assumption. 48*4862ec07SNicholas Beck */ 49*4862ec07SNicholas Beck pci_write_reg(0xFD000000 , SH7780_PCIMBR0); 50*4862ec07SNicholas Beck pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */ 51*4862ec07SNicholas Beck 52*4862ec07SNicholas Beck /* Set IOBR for window containing area specified in pci.h */ 53*4862ec07SNicholas Beck pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR); 54*4862ec07SNicholas Beck pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR); 55*4862ec07SNicholas Beck 56*4862ec07SNicholas Beck pci_write_reg(0xA5000C01, SH7780_PCICR); 57*4862ec07SNicholas Beck 58*4862ec07SNicholas Beck return 0; 59*4862ec07SNicholas Beck } 60