184972ec0SPaul Mundt /* 2*9ca04434SNobuhiro Iwamatsu * arch/sh/drivers/pci/fixups-landisk.c 384972ec0SPaul Mundt * 484972ec0SPaul Mundt * PCI initialization for the I-O DATA Device, Inc. LANDISK board 584972ec0SPaul Mundt * 684972ec0SPaul Mundt * Copyright (C) 2006 kogiidena 7*9ca04434SNobuhiro Iwamatsu * Copyright (C) 2010 Nobuhiro Iwamatsu 884972ec0SPaul Mundt * 984972ec0SPaul Mundt * May be copied or modified under the terms of the GNU General Public 1084972ec0SPaul Mundt * License. See linux/COPYING for more information. 1184972ec0SPaul Mundt */ 1284972ec0SPaul Mundt #include <linux/kernel.h> 1384972ec0SPaul Mundt #include <linux/types.h> 1484972ec0SPaul Mundt #include <linux/init.h> 1584972ec0SPaul Mundt #include <linux/delay.h> 1684972ec0SPaul Mundt #include <linux/pci.h> 1784972ec0SPaul Mundt #include "pci-sh4.h" 1884972ec0SPaul Mundt 19*9ca04434SNobuhiro Iwamatsu #define PCIMCR_MRSET_OFF 0xBFFFFFFF 20*9ca04434SNobuhiro Iwamatsu #define PCIMCR_RFSH_OFF 0xFFFFFFFB 21*9ca04434SNobuhiro Iwamatsu 2284972ec0SPaul Mundt int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 2384972ec0SPaul Mundt { 2484972ec0SPaul Mundt /* 2584972ec0SPaul Mundt * slot0: pin1-4 = irq5,6,7,8 2684972ec0SPaul Mundt * slot1: pin1-4 = irq6,7,8,5 2784972ec0SPaul Mundt * slot2: pin1-4 = irq7,8,5,6 2884972ec0SPaul Mundt * slot3: pin1-4 = irq8,5,6,7 2984972ec0SPaul Mundt */ 3084972ec0SPaul Mundt int irq = ((slot + pin - 1) & 0x3) + 5; 3184972ec0SPaul Mundt 3284972ec0SPaul Mundt if ((slot | (pin - 1)) > 0x3) { 33*9ca04434SNobuhiro Iwamatsu printk(KERN_WARNING "PCI: Bad IRQ mapping request for slot %d pin %c\n", 3484972ec0SPaul Mundt slot, pin - 1 + 'A'); 3584972ec0SPaul Mundt return -1; 3684972ec0SPaul Mundt } 3784972ec0SPaul Mundt return irq; 3884972ec0SPaul Mundt } 39*9ca04434SNobuhiro Iwamatsu 40*9ca04434SNobuhiro Iwamatsu int pci_fixup_pcic(struct pci_channel *chan) 41*9ca04434SNobuhiro Iwamatsu { 42*9ca04434SNobuhiro Iwamatsu unsigned long bcr1, mcr; 43*9ca04434SNobuhiro Iwamatsu 44*9ca04434SNobuhiro Iwamatsu bcr1 = __raw_readl(SH7751_BCR1); 45*9ca04434SNobuhiro Iwamatsu bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 46*9ca04434SNobuhiro Iwamatsu pci_write_reg(chan, bcr1, SH4_PCIBCR1); 47*9ca04434SNobuhiro Iwamatsu 48*9ca04434SNobuhiro Iwamatsu mcr = __raw_readl(SH7751_MCR); 49*9ca04434SNobuhiro Iwamatsu mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 50*9ca04434SNobuhiro Iwamatsu pci_write_reg(chan, mcr, SH4_PCIMCR); 51*9ca04434SNobuhiro Iwamatsu 52*9ca04434SNobuhiro Iwamatsu pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); 53*9ca04434SNobuhiro Iwamatsu pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); 54*9ca04434SNobuhiro Iwamatsu pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); 55*9ca04434SNobuhiro Iwamatsu pci_write_reg(chan, 0x00000000, SH4_PCILAR1); 56*9ca04434SNobuhiro Iwamatsu 57*9ca04434SNobuhiro Iwamatsu return 0; 58*9ca04434SNobuhiro Iwamatsu } 59