1aaf9128aSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
2d8d6b902SPaul Mundt /*
3d8d6b902SPaul Mundt * SDK7786 FPGA SRAM Support.
4d8d6b902SPaul Mundt *
5d8d6b902SPaul Mundt * Copyright (C) 2010 Paul Mundt
6d8d6b902SPaul Mundt */
7d8d6b902SPaul Mundt #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8d8d6b902SPaul Mundt
9d8d6b902SPaul Mundt #include <linux/init.h>
10d8d6b902SPaul Mundt #include <linux/kernel.h>
11d8d6b902SPaul Mundt #include <linux/types.h>
12d8d6b902SPaul Mundt #include <linux/io.h>
13d8d6b902SPaul Mundt #include <linux/string.h>
14d8d6b902SPaul Mundt #include <mach/fpga.h>
15d8d6b902SPaul Mundt #include <asm/sram.h>
16*87dfb311SMasahiro Yamada #include <linux/sizes.h>
17d8d6b902SPaul Mundt
fpga_sram_init(void)18d8d6b902SPaul Mundt static int __init fpga_sram_init(void)
19d8d6b902SPaul Mundt {
20d8d6b902SPaul Mundt unsigned long phys;
21d8d6b902SPaul Mundt unsigned int area;
22d8d6b902SPaul Mundt void __iomem *vaddr;
23d8d6b902SPaul Mundt int ret;
24d8d6b902SPaul Mundt u16 data;
25d8d6b902SPaul Mundt
26d8d6b902SPaul Mundt /* Enable FPGA SRAM */
27d8d6b902SPaul Mundt data = fpga_read_reg(LCLASR);
28d8d6b902SPaul Mundt data |= LCLASR_FRAMEN;
29d8d6b902SPaul Mundt fpga_write_reg(data, LCLASR);
30d8d6b902SPaul Mundt
31d8d6b902SPaul Mundt /*
32d8d6b902SPaul Mundt * FPGA_SEL determines the area mapping
33d8d6b902SPaul Mundt */
34d8d6b902SPaul Mundt area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;
35d8d6b902SPaul Mundt if (unlikely(area == LCLASR_AREA_MASK)) {
36d8d6b902SPaul Mundt pr_err("FPGA memory unmapped.\n");
37d8d6b902SPaul Mundt return -ENXIO;
38d8d6b902SPaul Mundt }
39d8d6b902SPaul Mundt
40d8d6b902SPaul Mundt /*
41d8d6b902SPaul Mundt * The memory itself occupies a 2KiB range at the top of the area
42d8d6b902SPaul Mundt * immediately below the system registers.
43d8d6b902SPaul Mundt */
44d8d6b902SPaul Mundt phys = (area << 26) + SZ_64M - SZ_4K;
45d8d6b902SPaul Mundt
46d8d6b902SPaul Mundt /*
47d8d6b902SPaul Mundt * The FPGA SRAM resides in translatable physical space, so set
48d8d6b902SPaul Mundt * up a mapping prior to inserting it in to the pool.
49d8d6b902SPaul Mundt */
50d8d6b902SPaul Mundt vaddr = ioremap(phys, SZ_2K);
51d8d6b902SPaul Mundt if (unlikely(!vaddr)) {
52d8d6b902SPaul Mundt pr_err("Failed remapping FPGA memory.\n");
53d8d6b902SPaul Mundt return -ENXIO;
54d8d6b902SPaul Mundt }
55d8d6b902SPaul Mundt
56d8d6b902SPaul Mundt pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "
57d8d6b902SPaul Mundt "(area %d) to pool.\n",
58d8d6b902SPaul Mundt SZ_2K >> 10, phys, phys + SZ_2K - 1, area);
59d8d6b902SPaul Mundt
60d8d6b902SPaul Mundt ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);
61d8d6b902SPaul Mundt if (unlikely(ret < 0)) {
62d8d6b902SPaul Mundt pr_err("Failed adding memory\n");
63d8d6b902SPaul Mundt iounmap(vaddr);
64d8d6b902SPaul Mundt return ret;
65d8d6b902SPaul Mundt }
66d8d6b902SPaul Mundt
67d8d6b902SPaul Mundt return 0;
68d8d6b902SPaul Mundt }
69d8d6b902SPaul Mundt postcore_initcall(fpga_sram_init);
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