1*aaf9128aSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
25f240718SPaul Mundt /*
35f240718SPaul Mundt * SDK7786 FPGA IRQ Controller Support.
45f240718SPaul Mundt *
55f240718SPaul Mundt * Copyright (C) 2010 Matt Fleming
65f240718SPaul Mundt * Copyright (C) 2010 Paul Mundt
75f240718SPaul Mundt */
85f240718SPaul Mundt #include <linux/irq.h>
95f240718SPaul Mundt #include <mach/fpga.h>
105f240718SPaul Mundt #include <mach/irq.h>
115f240718SPaul Mundt
125f240718SPaul Mundt enum {
135f240718SPaul Mundt ATA_IRQ_BIT = 1,
145f240718SPaul Mundt SPI_BUSY_BIT = 2,
155f240718SPaul Mundt LIRQ5_BIT = 3,
165f240718SPaul Mundt LIRQ6_BIT = 4,
175f240718SPaul Mundt LIRQ7_BIT = 5,
185f240718SPaul Mundt LIRQ8_BIT = 6,
195f240718SPaul Mundt KEY_IRQ_BIT = 7,
205f240718SPaul Mundt PEN_IRQ_BIT = 8,
215f240718SPaul Mundt ETH_IRQ_BIT = 9,
225f240718SPaul Mundt RTC_ALARM_BIT = 10,
235f240718SPaul Mundt CRYSTAL_FAIL_BIT = 12,
245f240718SPaul Mundt ETH_PME_BIT = 14,
255f240718SPaul Mundt };
265f240718SPaul Mundt
sdk7786_init_irq(void)275f240718SPaul Mundt void __init sdk7786_init_irq(void)
285f240718SPaul Mundt {
295f240718SPaul Mundt unsigned int tmp;
305f240718SPaul Mundt
315f240718SPaul Mundt /* Enable priority encoding for all IRLs */
325f240718SPaul Mundt fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
335f240718SPaul Mundt
345f240718SPaul Mundt /* Clear FPGA interrupt status registers */
355f240718SPaul Mundt fpga_write_reg(0x0000, INTASR);
365f240718SPaul Mundt fpga_write_reg(0x0000, INTBSR);
375f240718SPaul Mundt
385f240718SPaul Mundt /* Unmask FPGA interrupts */
395f240718SPaul Mundt tmp = fpga_read_reg(INTAMR);
405f240718SPaul Mundt tmp &= ~(1 << ETH_IRQ_BIT);
415f240718SPaul Mundt fpga_write_reg(tmp, INTAMR);
425f240718SPaul Mundt
435f240718SPaul Mundt plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
445f240718SPaul Mundt plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
455f240718SPaul Mundt }
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