1aaf9128aSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
2c8b5d9dcSPaul Mundt /*
3c8b5d9dcSPaul Mundt * Renesas Technology Corp. R0P7785LC0011RL Support.
4c8b5d9dcSPaul Mundt *
5c8b5d9dcSPaul Mundt * Copyright (C) 2008 Yoshihiro Shimoda
6a77b5ac0SPaul Mundt * Copyright (C) 2009 Paul Mundt
7c8b5d9dcSPaul Mundt */
8c8b5d9dcSPaul Mundt #include <linux/init.h>
9c8b5d9dcSPaul Mundt #include <linux/platform_device.h>
10c8b5d9dcSPaul Mundt #include <linux/sm501.h>
11c8b5d9dcSPaul Mundt #include <linux/sm501-regs.h>
12c8b5d9dcSPaul Mundt #include <linux/fb.h>
13c8b5d9dcSPaul Mundt #include <linux/mtd/physmap.h>
14c8b5d9dcSPaul Mundt #include <linux/delay.h>
155a62a225SYoshihiro Shimoda #include <linux/interrupt.h>
16c8b5d9dcSPaul Mundt #include <linux/i2c.h>
17e5c71377SWolfram Sang #include <linux/platform_data/i2c-pca-platform.h>
18c8b5d9dcSPaul Mundt #include <linux/i2c-algo-pca.h>
195a62a225SYoshihiro Shimoda #include <linux/usb/r8a66597.h>
20c825abc4SPaul Mundt #include <linux/sh_intc.h>
21604437f0SPaul Mundt #include <linux/irq.h>
22d57d6408SPaul Mundt #include <linux/io.h>
23a77b5ac0SPaul Mundt #include <linux/clk.h>
24a77b5ac0SPaul Mundt #include <linux/errno.h>
25df0d3234SChris Packham #include <linux/gpio/machine.h>
267639a454SPaul Mundt #include <mach/sh7785lcr.h>
275a62a225SYoshihiro Shimoda #include <cpu/sh7785.h>
28a77b5ac0SPaul Mundt #include <asm/heartbeat.h>
29a77b5ac0SPaul Mundt #include <asm/clock.h>
30f03c4866SPaul Mundt #include <asm/bl_bit.h>
31c8b5d9dcSPaul Mundt
32c8b5d9dcSPaul Mundt /*
33c8b5d9dcSPaul Mundt * NOTE: This board has 2 physical memory maps.
34c8b5d9dcSPaul Mundt * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
35c8b5d9dcSPaul Mundt */
36a09d2831SPaul Mundt static struct resource heartbeat_resource = {
37c8b5d9dcSPaul Mundt .start = PLD_LEDCR,
38c8b5d9dcSPaul Mundt .end = PLD_LEDCR,
39a09d2831SPaul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
40c8b5d9dcSPaul Mundt };
41c8b5d9dcSPaul Mundt
42c8b5d9dcSPaul Mundt static struct platform_device heartbeat_device = {
43c8b5d9dcSPaul Mundt .name = "heartbeat",
44c8b5d9dcSPaul Mundt .id = -1,
45a09d2831SPaul Mundt .num_resources = 1,
46a09d2831SPaul Mundt .resource = &heartbeat_resource,
47c8b5d9dcSPaul Mundt };
48c8b5d9dcSPaul Mundt
49c8b5d9dcSPaul Mundt static struct mtd_partition nor_flash_partitions[] = {
50c8b5d9dcSPaul Mundt {
51c8b5d9dcSPaul Mundt .name = "loader",
52c8b5d9dcSPaul Mundt .offset = 0x00000000,
53c8b5d9dcSPaul Mundt .size = 512 * 1024,
54c8b5d9dcSPaul Mundt },
55c8b5d9dcSPaul Mundt {
56c8b5d9dcSPaul Mundt .name = "bootenv",
57c8b5d9dcSPaul Mundt .offset = MTDPART_OFS_APPEND,
58c8b5d9dcSPaul Mundt .size = 512 * 1024,
59c8b5d9dcSPaul Mundt },
60c8b5d9dcSPaul Mundt {
61c8b5d9dcSPaul Mundt .name = "kernel",
62c8b5d9dcSPaul Mundt .offset = MTDPART_OFS_APPEND,
63c8b5d9dcSPaul Mundt .size = 4 * 1024 * 1024,
64c8b5d9dcSPaul Mundt },
65c8b5d9dcSPaul Mundt {
66c8b5d9dcSPaul Mundt .name = "data",
67c8b5d9dcSPaul Mundt .offset = MTDPART_OFS_APPEND,
68c8b5d9dcSPaul Mundt .size = MTDPART_SIZ_FULL,
69c8b5d9dcSPaul Mundt },
70c8b5d9dcSPaul Mundt };
71c8b5d9dcSPaul Mundt
72c8b5d9dcSPaul Mundt static struct physmap_flash_data nor_flash_data = {
73c8b5d9dcSPaul Mundt .width = 4,
74c8b5d9dcSPaul Mundt .parts = nor_flash_partitions,
75c8b5d9dcSPaul Mundt .nr_parts = ARRAY_SIZE(nor_flash_partitions),
76c8b5d9dcSPaul Mundt };
77c8b5d9dcSPaul Mundt
78c8b5d9dcSPaul Mundt static struct resource nor_flash_resources[] = {
79c8b5d9dcSPaul Mundt [0] = {
80c8b5d9dcSPaul Mundt .start = NOR_FLASH_ADDR,
81c8b5d9dcSPaul Mundt .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
82c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM,
83c8b5d9dcSPaul Mundt }
84c8b5d9dcSPaul Mundt };
85c8b5d9dcSPaul Mundt
86c8b5d9dcSPaul Mundt static struct platform_device nor_flash_device = {
87c8b5d9dcSPaul Mundt .name = "physmap-flash",
88c8b5d9dcSPaul Mundt .dev = {
89c8b5d9dcSPaul Mundt .platform_data = &nor_flash_data,
90c8b5d9dcSPaul Mundt },
91c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(nor_flash_resources),
92c8b5d9dcSPaul Mundt .resource = nor_flash_resources,
93c8b5d9dcSPaul Mundt };
94c8b5d9dcSPaul Mundt
955a62a225SYoshihiro Shimoda static struct r8a66597_platdata r8a66597_data = {
965a62a225SYoshihiro Shimoda .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
975a62a225SYoshihiro Shimoda .vif = 1,
985a62a225SYoshihiro Shimoda };
995a62a225SYoshihiro Shimoda
100c8b5d9dcSPaul Mundt static struct resource r8a66597_usb_host_resources[] = {
101c8b5d9dcSPaul Mundt [0] = {
102c8b5d9dcSPaul Mundt .start = R8A66597_ADDR,
103c8b5d9dcSPaul Mundt .end = R8A66597_ADDR + R8A66597_SIZE - 1,
104c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM,
105c8b5d9dcSPaul Mundt },
106c8b5d9dcSPaul Mundt [1] = {
107c825abc4SPaul Mundt .start = evt2irq(0x240),
108c825abc4SPaul Mundt .end = evt2irq(0x240),
1095a62a225SYoshihiro Shimoda .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
110c8b5d9dcSPaul Mundt },
111c8b5d9dcSPaul Mundt };
112c8b5d9dcSPaul Mundt
113c8b5d9dcSPaul Mundt static struct platform_device r8a66597_usb_host_device = {
114c8b5d9dcSPaul Mundt .name = "r8a66597_hcd",
115c8b5d9dcSPaul Mundt .id = -1,
116c8b5d9dcSPaul Mundt .dev = {
117c8b5d9dcSPaul Mundt .dma_mask = NULL,
118c8b5d9dcSPaul Mundt .coherent_dma_mask = 0xffffffff,
1195a62a225SYoshihiro Shimoda .platform_data = &r8a66597_data,
120c8b5d9dcSPaul Mundt },
121c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
122c8b5d9dcSPaul Mundt .resource = r8a66597_usb_host_resources,
123c8b5d9dcSPaul Mundt };
124c8b5d9dcSPaul Mundt
125c8b5d9dcSPaul Mundt static struct resource sm501_resources[] = {
126c8b5d9dcSPaul Mundt [0] = {
127c8b5d9dcSPaul Mundt .start = SM107_MEM_ADDR,
128c8b5d9dcSPaul Mundt .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
129c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM,
130c8b5d9dcSPaul Mundt },
131c8b5d9dcSPaul Mundt [1] = {
132c8b5d9dcSPaul Mundt .start = SM107_REG_ADDR,
133c8b5d9dcSPaul Mundt .end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
134c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM,
135c8b5d9dcSPaul Mundt },
136c8b5d9dcSPaul Mundt [2] = {
137c825abc4SPaul Mundt .start = evt2irq(0x340),
138c8b5d9dcSPaul Mundt .flags = IORESOURCE_IRQ,
139c8b5d9dcSPaul Mundt },
140c8b5d9dcSPaul Mundt };
141c8b5d9dcSPaul Mundt
142c8b5d9dcSPaul Mundt static struct fb_videomode sm501_default_mode_crt = {
143c8b5d9dcSPaul Mundt .pixclock = 35714, /* 28MHz */
144c8b5d9dcSPaul Mundt .xres = 640,
145c8b5d9dcSPaul Mundt .yres = 480,
146c8b5d9dcSPaul Mundt .left_margin = 105,
147c8b5d9dcSPaul Mundt .right_margin = 16,
148c8b5d9dcSPaul Mundt .upper_margin = 33,
149c8b5d9dcSPaul Mundt .lower_margin = 10,
150c8b5d9dcSPaul Mundt .hsync_len = 39,
151c8b5d9dcSPaul Mundt .vsync_len = 2,
152c8b5d9dcSPaul Mundt .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
153c8b5d9dcSPaul Mundt };
154c8b5d9dcSPaul Mundt
155c8b5d9dcSPaul Mundt static struct fb_videomode sm501_default_mode_pnl = {
156c8b5d9dcSPaul Mundt .pixclock = 40000, /* 25MHz */
157c8b5d9dcSPaul Mundt .xres = 640,
158c8b5d9dcSPaul Mundt .yres = 480,
159c8b5d9dcSPaul Mundt .left_margin = 2,
160c8b5d9dcSPaul Mundt .right_margin = 16,
161c8b5d9dcSPaul Mundt .upper_margin = 33,
162c8b5d9dcSPaul Mundt .lower_margin = 10,
163c8b5d9dcSPaul Mundt .hsync_len = 39,
164c8b5d9dcSPaul Mundt .vsync_len = 2,
165c8b5d9dcSPaul Mundt .sync = 0,
166c8b5d9dcSPaul Mundt };
167c8b5d9dcSPaul Mundt
168c8b5d9dcSPaul Mundt static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
169c8b5d9dcSPaul Mundt .def_bpp = 16,
170c8b5d9dcSPaul Mundt .def_mode = &sm501_default_mode_pnl,
171c8b5d9dcSPaul Mundt .flags = SM501FB_FLAG_USE_INIT_MODE |
172c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWCURSOR |
173c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWACCEL |
174c8b5d9dcSPaul Mundt SM501FB_FLAG_DISABLE_AT_EXIT |
175c8b5d9dcSPaul Mundt SM501FB_FLAG_PANEL_NO_VBIASEN,
176c8b5d9dcSPaul Mundt };
177c8b5d9dcSPaul Mundt
178c8b5d9dcSPaul Mundt static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
179c8b5d9dcSPaul Mundt .def_bpp = 16,
180c8b5d9dcSPaul Mundt .def_mode = &sm501_default_mode_crt,
181c8b5d9dcSPaul Mundt .flags = SM501FB_FLAG_USE_INIT_MODE |
182c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWCURSOR |
183c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWACCEL |
184c8b5d9dcSPaul Mundt SM501FB_FLAG_DISABLE_AT_EXIT,
185c8b5d9dcSPaul Mundt };
186c8b5d9dcSPaul Mundt
187c8b5d9dcSPaul Mundt static struct sm501_platdata_fb sm501_fb_pdata = {
188c8b5d9dcSPaul Mundt .fb_route = SM501_FB_OWN,
189c8b5d9dcSPaul Mundt .fb_crt = &sm501_pdata_fbsub_crt,
190c8b5d9dcSPaul Mundt .fb_pnl = &sm501_pdata_fbsub_pnl,
191c8b5d9dcSPaul Mundt };
192c8b5d9dcSPaul Mundt
193c8b5d9dcSPaul Mundt static struct sm501_initdata sm501_initdata = {
194c8b5d9dcSPaul Mundt .gpio_high = {
195c8b5d9dcSPaul Mundt .set = 0x00001fe0,
196c8b5d9dcSPaul Mundt .mask = 0x0,
197c8b5d9dcSPaul Mundt },
198c8b5d9dcSPaul Mundt .devices = 0,
199c8b5d9dcSPaul Mundt .mclk = 84 * 1000000,
200c8b5d9dcSPaul Mundt .m1xclk = 112 * 1000000,
201c8b5d9dcSPaul Mundt };
202c8b5d9dcSPaul Mundt
203c8b5d9dcSPaul Mundt static struct sm501_platdata sm501_platform_data = {
204c8b5d9dcSPaul Mundt .init = &sm501_initdata,
205c8b5d9dcSPaul Mundt .fb = &sm501_fb_pdata,
206c8b5d9dcSPaul Mundt };
207c8b5d9dcSPaul Mundt
208c8b5d9dcSPaul Mundt static struct platform_device sm501_device = {
209c8b5d9dcSPaul Mundt .name = "sm501",
210c8b5d9dcSPaul Mundt .id = -1,
211c8b5d9dcSPaul Mundt .dev = {
212c8b5d9dcSPaul Mundt .platform_data = &sm501_platform_data,
213c8b5d9dcSPaul Mundt },
214c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(sm501_resources),
215c8b5d9dcSPaul Mundt .resource = sm501_resources,
216c8b5d9dcSPaul Mundt };
217c8b5d9dcSPaul Mundt
218e79d5747SYoshihiro Shimoda static struct resource i2c_proto_resources[] = {
219e79d5747SYoshihiro Shimoda [0] = {
220e79d5747SYoshihiro Shimoda .start = PCA9564_PROTO_32BIT_ADDR,
221e79d5747SYoshihiro Shimoda .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
222e79d5747SYoshihiro Shimoda .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
223e79d5747SYoshihiro Shimoda },
224e79d5747SYoshihiro Shimoda [1] = {
225c825abc4SPaul Mundt .start = evt2irq(0x380),
226c825abc4SPaul Mundt .end = evt2irq(0x380),
227e79d5747SYoshihiro Shimoda .flags = IORESOURCE_IRQ,
228e79d5747SYoshihiro Shimoda },
229e79d5747SYoshihiro Shimoda };
230e79d5747SYoshihiro Shimoda
231c8b5d9dcSPaul Mundt static struct resource i2c_resources[] = {
232c8b5d9dcSPaul Mundt [0] = {
233c8b5d9dcSPaul Mundt .start = PCA9564_ADDR,
234c8b5d9dcSPaul Mundt .end = PCA9564_ADDR + PCA9564_SIZE - 1,
235c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
236c8b5d9dcSPaul Mundt },
237c8b5d9dcSPaul Mundt [1] = {
238c825abc4SPaul Mundt .start = evt2irq(0x380),
239c825abc4SPaul Mundt .end = evt2irq(0x380),
240c8b5d9dcSPaul Mundt .flags = IORESOURCE_IRQ,
241c8b5d9dcSPaul Mundt },
242c8b5d9dcSPaul Mundt };
243c8b5d9dcSPaul Mundt
244df0d3234SChris Packham static struct gpiod_lookup_table i2c_gpio_table = {
245df0d3234SChris Packham .dev_id = "i2c.0",
246df0d3234SChris Packham .table = {
247df0d3234SChris Packham GPIO_LOOKUP("pfc-sh7757", 0, "reset-gpios", GPIO_ACTIVE_LOW),
248df0d3234SChris Packham { },
249df0d3234SChris Packham },
250df0d3234SChris Packham };
251df0d3234SChris Packham
252c8b5d9dcSPaul Mundt static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
253c8b5d9dcSPaul Mundt .i2c_clock_speed = I2C_PCA_CON_330kHz,
2548e99ada8SWolfram Sang .timeout = HZ,
255c8b5d9dcSPaul Mundt };
256c8b5d9dcSPaul Mundt
257c8b5d9dcSPaul Mundt static struct platform_device i2c_device = {
258c8b5d9dcSPaul Mundt .name = "i2c-pca-platform",
259c8b5d9dcSPaul Mundt .id = -1,
260c8b5d9dcSPaul Mundt .dev = {
261c8b5d9dcSPaul Mundt .platform_data = &i2c_platform_data,
262c8b5d9dcSPaul Mundt },
263c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(i2c_resources),
264c8b5d9dcSPaul Mundt .resource = i2c_resources,
265c8b5d9dcSPaul Mundt };
266c8b5d9dcSPaul Mundt
267c8b5d9dcSPaul Mundt static struct platform_device *sh7785lcr_devices[] __initdata = {
268c8b5d9dcSPaul Mundt &heartbeat_device,
269c8b5d9dcSPaul Mundt &nor_flash_device,
270c8b5d9dcSPaul Mundt &r8a66597_usb_host_device,
271c8b5d9dcSPaul Mundt &sm501_device,
272c8b5d9dcSPaul Mundt &i2c_device,
273c8b5d9dcSPaul Mundt };
274c8b5d9dcSPaul Mundt
275c8b5d9dcSPaul Mundt static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
276c8b5d9dcSPaul Mundt {
277c8b5d9dcSPaul Mundt I2C_BOARD_INFO("r2025sd", 0x32),
278c8b5d9dcSPaul Mundt },
279c8b5d9dcSPaul Mundt };
280c8b5d9dcSPaul Mundt
sh7785lcr_devices_setup(void)281c8b5d9dcSPaul Mundt static int __init sh7785lcr_devices_setup(void)
282c8b5d9dcSPaul Mundt {
283c8b5d9dcSPaul Mundt i2c_register_board_info(0, sh7785lcr_i2c_devices,
284c8b5d9dcSPaul Mundt ARRAY_SIZE(sh7785lcr_i2c_devices));
285c8b5d9dcSPaul Mundt
286e79d5747SYoshihiro Shimoda if (mach_is_sh7785lcr_pt()) {
287d1af119aSPaul Mundt i2c_device.resource = i2c_proto_resources;
288e79d5747SYoshihiro Shimoda i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
289e79d5747SYoshihiro Shimoda }
290e79d5747SYoshihiro Shimoda
291df0d3234SChris Packham gpiod_add_lookup_table(&i2c_gpio_table);
292c8b5d9dcSPaul Mundt return platform_add_devices(sh7785lcr_devices,
293c8b5d9dcSPaul Mundt ARRAY_SIZE(sh7785lcr_devices));
294c8b5d9dcSPaul Mundt }
29595d210ceSNobuhiro Iwamatsu device_initcall(sh7785lcr_devices_setup);
296c8b5d9dcSPaul Mundt
297c8b5d9dcSPaul Mundt /* Initialize IRQ setting */
init_sh7785lcr_IRQ(void)298c8b5d9dcSPaul Mundt void __init init_sh7785lcr_IRQ(void)
299c8b5d9dcSPaul Mundt {
300c8b5d9dcSPaul Mundt plat_irq_setup_pins(IRQ_MODE_IRQ7654);
301c8b5d9dcSPaul Mundt plat_irq_setup_pins(IRQ_MODE_IRQ3210);
302c8b5d9dcSPaul Mundt }
303c8b5d9dcSPaul Mundt
sh7785lcr_clk_init(void)304a77b5ac0SPaul Mundt static int sh7785lcr_clk_init(void)
305a77b5ac0SPaul Mundt {
306a77b5ac0SPaul Mundt struct clk *clk;
307a77b5ac0SPaul Mundt int ret;
308a77b5ac0SPaul Mundt
309a77b5ac0SPaul Mundt clk = clk_get(NULL, "extal");
3107912825dSPaul Mundt if (IS_ERR(clk))
311a77b5ac0SPaul Mundt return PTR_ERR(clk);
312a77b5ac0SPaul Mundt ret = clk_set_rate(clk, 33333333);
313a77b5ac0SPaul Mundt clk_put(clk);
314a77b5ac0SPaul Mundt
315a77b5ac0SPaul Mundt return ret;
316a77b5ac0SPaul Mundt }
317a77b5ac0SPaul Mundt
sh7785lcr_power_off(void)318c8b5d9dcSPaul Mundt static void sh7785lcr_power_off(void)
319c8b5d9dcSPaul Mundt {
320df4d4f1aSYoshihiro Shimoda unsigned char *p;
321df4d4f1aSYoshihiro Shimoda
322df4d4f1aSYoshihiro Shimoda p = ioremap(PLD_POFCR, PLD_POFCR + 1);
323df4d4f1aSYoshihiro Shimoda if (!p) {
324df4d4f1aSYoshihiro Shimoda printk(KERN_ERR "%s: ioremap error.\n", __func__);
325df4d4f1aSYoshihiro Shimoda return;
326df4d4f1aSYoshihiro Shimoda }
327df4d4f1aSYoshihiro Shimoda *p = 0x01;
328df4d4f1aSYoshihiro Shimoda iounmap(p);
329600fa578SMagnus Damm set_bl_bit();
330600fa578SMagnus Damm while (1)
331600fa578SMagnus Damm cpu_relax();
332c8b5d9dcSPaul Mundt }
333c8b5d9dcSPaul Mundt
334c8b5d9dcSPaul Mundt /* Initialize the board */
sh7785lcr_setup(char ** cmdline_p)335c8b5d9dcSPaul Mundt static void __init sh7785lcr_setup(char **cmdline_p)
336c8b5d9dcSPaul Mundt {
337c8b5d9dcSPaul Mundt void __iomem *sm501_reg;
338c8b5d9dcSPaul Mundt
339c8b5d9dcSPaul Mundt printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
340c8b5d9dcSPaul Mundt
341c8b5d9dcSPaul Mundt pm_power_off = sh7785lcr_power_off;
342c8b5d9dcSPaul Mundt
343c8b5d9dcSPaul Mundt /* sm501 DRAM configuration */
344*4bdc0d67SChristoph Hellwig sm501_reg = ioremap(SM107_REG_ADDR, SM501_DRAM_CONTROL);
3456f82b6ebSMatt Fleming if (!sm501_reg) {
3466f82b6ebSMatt Fleming printk(KERN_ERR "%s: ioremap error.\n", __func__);
3476f82b6ebSMatt Fleming return;
3486f82b6ebSMatt Fleming }
3496f82b6ebSMatt Fleming
3506f82b6ebSMatt Fleming writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
351d57d6408SPaul Mundt iounmap(sm501_reg);
352c8b5d9dcSPaul Mundt }
353c8b5d9dcSPaul Mundt
35463d12e23SMagnus Damm /* Return the board specific boot mode pin configuration */
sh7785lcr_mode_pins(void)35563d12e23SMagnus Damm static int sh7785lcr_mode_pins(void)
35663d12e23SMagnus Damm {
35763d12e23SMagnus Damm int value = 0;
35863d12e23SMagnus Damm
35963d12e23SMagnus Damm /* These are the factory default settings of S1 and S2.
36063d12e23SMagnus Damm * If you change these dip switches then you will need to
36163d12e23SMagnus Damm * adjust the values below as well.
36263d12e23SMagnus Damm */
3630d4fdbb6SMagnus Damm value |= MODE_PIN4; /* Clock Mode 16 */
3640d4fdbb6SMagnus Damm value |= MODE_PIN5; /* 32-bit Area0 bus width */
3650d4fdbb6SMagnus Damm value |= MODE_PIN6; /* 32-bit Area0 bus width */
3660d4fdbb6SMagnus Damm value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
3670d4fdbb6SMagnus Damm value |= MODE_PIN8; /* Little Endian */
3680d4fdbb6SMagnus Damm value |= MODE_PIN9; /* Master Mode */
3690d4fdbb6SMagnus Damm value |= MODE_PIN14; /* No PLL step-up */
37063d12e23SMagnus Damm
37163d12e23SMagnus Damm return value;
37263d12e23SMagnus Damm }
37363d12e23SMagnus Damm
374c8b5d9dcSPaul Mundt /*
375c8b5d9dcSPaul Mundt * The Machine Vector
376c8b5d9dcSPaul Mundt */
377c8b5d9dcSPaul Mundt static struct sh_machine_vector mv_sh7785lcr __initmv = {
378c8b5d9dcSPaul Mundt .mv_name = "SH7785LCR",
379c8b5d9dcSPaul Mundt .mv_setup = sh7785lcr_setup,
380a77b5ac0SPaul Mundt .mv_clk_init = sh7785lcr_clk_init,
381c8b5d9dcSPaul Mundt .mv_init_irq = init_sh7785lcr_IRQ,
38263d12e23SMagnus Damm .mv_mode_pins = sh7785lcr_mode_pins,
383c8b5d9dcSPaul Mundt };
384c8b5d9dcSPaul Mundt
385