1 /* 2 * arch/s390/kernel/time.c 3 * Time of day based timer functions. 4 * 5 * S390 version 6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation 7 * Author(s): Hartmut Penner (hp@de.ibm.com), 8 * Martin Schwidefsky (schwidefsky@de.ibm.com), 9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 10 * 11 * Derived from "arch/i386/kernel/time.c" 12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/module.h> 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/param.h> 20 #include <linux/string.h> 21 #include <linux/mm.h> 22 #include <linux/interrupt.h> 23 #include <linux/time.h> 24 #include <linux/sysdev.h> 25 #include <linux/delay.h> 26 #include <linux/init.h> 27 #include <linux/smp.h> 28 #include <linux/types.h> 29 #include <linux/profile.h> 30 #include <linux/timex.h> 31 #include <linux/notifier.h> 32 #include <linux/clocksource.h> 33 34 #include <asm/uaccess.h> 35 #include <asm/delay.h> 36 #include <asm/s390_ext.h> 37 #include <asm/div64.h> 38 #include <asm/irq.h> 39 #include <asm/irq_regs.h> 40 #include <asm/timer.h> 41 #include <asm/etr.h> 42 43 /* change this if you have some constant time drift */ 44 #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) 45 #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) 46 47 /* The value of the TOD clock for 1.1.1970. */ 48 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL 49 50 /* 51 * Create a small time difference between the timer interrupts 52 * on the different cpus to avoid lock contention. 53 */ 54 #define CPU_DEVIATION (smp_processor_id() << 12) 55 56 #define TICK_SIZE tick 57 58 static ext_int_info_t ext_int_info_cc; 59 static ext_int_info_t ext_int_etr_cc; 60 static u64 init_timer_cc; 61 static u64 jiffies_timer_cc; 62 static u64 xtime_cc; 63 64 /* 65 * Scheduler clock - returns current time in nanosec units. 66 */ 67 unsigned long long sched_clock(void) 68 { 69 return ((get_clock() - jiffies_timer_cc) * 125) >> 9; 70 } 71 72 /* 73 * Monotonic_clock - returns # of nanoseconds passed since time_init() 74 */ 75 unsigned long long monotonic_clock(void) 76 { 77 return sched_clock(); 78 } 79 EXPORT_SYMBOL(monotonic_clock); 80 81 void tod_to_timeval(__u64 todval, struct timespec *xtime) 82 { 83 unsigned long long sec; 84 85 sec = todval >> 12; 86 do_div(sec, 1000000); 87 xtime->tv_sec = sec; 88 todval -= (sec * 1000000) << 12; 89 xtime->tv_nsec = ((todval * 1000) >> 12); 90 } 91 92 #ifdef CONFIG_PROFILING 93 #define s390_do_profile() profile_tick(CPU_PROFILING) 94 #else 95 #define s390_do_profile() do { ; } while(0) 96 #endif /* CONFIG_PROFILING */ 97 98 /* 99 * Advance the per cpu tick counter up to the time given with the 100 * "time" argument. The per cpu update consists of accounting 101 * the virtual cpu time, calling update_process_times and calling 102 * the profiling hook. If xtime is before time it is advanced as well. 103 */ 104 void account_ticks(u64 time) 105 { 106 __u32 ticks; 107 __u64 tmp; 108 109 /* Calculate how many ticks have passed. */ 110 if (time < S390_lowcore.jiffy_timer) 111 return; 112 tmp = time - S390_lowcore.jiffy_timer; 113 if (tmp >= 2*CLK_TICKS_PER_JIFFY) { /* more than two ticks ? */ 114 ticks = __div(tmp, CLK_TICKS_PER_JIFFY) + 1; 115 S390_lowcore.jiffy_timer += 116 CLK_TICKS_PER_JIFFY * (__u64) ticks; 117 } else if (tmp >= CLK_TICKS_PER_JIFFY) { 118 ticks = 2; 119 S390_lowcore.jiffy_timer += 2*CLK_TICKS_PER_JIFFY; 120 } else { 121 ticks = 1; 122 S390_lowcore.jiffy_timer += CLK_TICKS_PER_JIFFY; 123 } 124 125 #ifdef CONFIG_SMP 126 /* 127 * Do not rely on the boot cpu to do the calls to do_timer. 128 * Spread it over all cpus instead. 129 */ 130 write_seqlock(&xtime_lock); 131 if (S390_lowcore.jiffy_timer > xtime_cc) { 132 __u32 xticks; 133 tmp = S390_lowcore.jiffy_timer - xtime_cc; 134 if (tmp >= 2*CLK_TICKS_PER_JIFFY) { 135 xticks = __div(tmp, CLK_TICKS_PER_JIFFY); 136 xtime_cc += (__u64) xticks * CLK_TICKS_PER_JIFFY; 137 } else { 138 xticks = 1; 139 xtime_cc += CLK_TICKS_PER_JIFFY; 140 } 141 do_timer(xticks); 142 } 143 write_sequnlock(&xtime_lock); 144 #else 145 do_timer(ticks); 146 #endif 147 148 #ifdef CONFIG_VIRT_CPU_ACCOUNTING 149 account_tick_vtime(current); 150 #else 151 while (ticks--) 152 update_process_times(user_mode(get_irq_regs())); 153 #endif 154 155 s390_do_profile(); 156 } 157 158 #ifdef CONFIG_NO_IDLE_HZ 159 160 #ifdef CONFIG_NO_IDLE_HZ_INIT 161 int sysctl_hz_timer = 0; 162 #else 163 int sysctl_hz_timer = 1; 164 #endif 165 166 /* 167 * Stop the HZ tick on the current CPU. 168 * Only cpu_idle may call this function. 169 */ 170 static void stop_hz_timer(void) 171 { 172 unsigned long flags; 173 unsigned long seq, next; 174 __u64 timer, todval; 175 int cpu = smp_processor_id(); 176 177 if (sysctl_hz_timer != 0) 178 return; 179 180 cpu_set(cpu, nohz_cpu_mask); 181 182 /* 183 * Leave the clock comparator set up for the next timer 184 * tick if either rcu or a softirq is pending. 185 */ 186 if (rcu_needs_cpu(cpu) || local_softirq_pending()) { 187 cpu_clear(cpu, nohz_cpu_mask); 188 return; 189 } 190 191 /* 192 * This cpu is going really idle. Set up the clock comparator 193 * for the next event. 194 */ 195 next = next_timer_interrupt(); 196 do { 197 seq = read_seqbegin_irqsave(&xtime_lock, flags); 198 timer = ((__u64) next) - ((__u64) jiffies) + jiffies_64; 199 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 200 todval = -1ULL; 201 /* Be careful about overflows. */ 202 if (timer < (-1ULL / CLK_TICKS_PER_JIFFY)) { 203 timer = jiffies_timer_cc + timer * CLK_TICKS_PER_JIFFY; 204 if (timer >= jiffies_timer_cc) 205 todval = timer; 206 } 207 set_clock_comparator(todval); 208 } 209 210 /* 211 * Start the HZ tick on the current CPU. 212 * Only cpu_idle may call this function. 213 */ 214 static void start_hz_timer(void) 215 { 216 BUG_ON(!in_interrupt()); 217 218 if (!cpu_isset(smp_processor_id(), nohz_cpu_mask)) 219 return; 220 account_ticks(get_clock()); 221 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 222 cpu_clear(smp_processor_id(), nohz_cpu_mask); 223 } 224 225 static int nohz_idle_notify(struct notifier_block *self, 226 unsigned long action, void *hcpu) 227 { 228 switch (action) { 229 case S390_CPU_IDLE: 230 stop_hz_timer(); 231 break; 232 case S390_CPU_NOT_IDLE: 233 start_hz_timer(); 234 break; 235 } 236 return NOTIFY_OK; 237 } 238 239 static struct notifier_block nohz_idle_nb = { 240 .notifier_call = nohz_idle_notify, 241 }; 242 243 static void __init nohz_init(void) 244 { 245 if (register_idle_notifier(&nohz_idle_nb)) 246 panic("Couldn't register idle notifier"); 247 } 248 249 #endif 250 251 /* 252 * Set up per cpu jiffy timer and set the clock comparator. 253 */ 254 static void setup_jiffy_timer(void) 255 { 256 /* Set up clock comparator to next jiffy. */ 257 S390_lowcore.jiffy_timer = 258 jiffies_timer_cc + (jiffies_64 + 1) * CLK_TICKS_PER_JIFFY; 259 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 260 } 261 262 /* 263 * Set up lowcore and control register of the current cpu to 264 * enable TOD clock and clock comparator interrupts. 265 */ 266 void init_cpu_timer(void) 267 { 268 setup_jiffy_timer(); 269 270 /* Enable clock comparator timer interrupt. */ 271 __ctl_set_bit(0,11); 272 273 /* Always allow ETR external interrupts, even without an ETR. */ 274 __ctl_set_bit(0, 4); 275 } 276 277 static void clock_comparator_interrupt(__u16 code) 278 { 279 /* set clock comparator for next tick */ 280 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 281 } 282 283 static void etr_reset(void); 284 static void etr_ext_handler(__u16); 285 286 /* 287 * Get the TOD clock running. 288 */ 289 static u64 __init reset_tod_clock(void) 290 { 291 u64 time; 292 293 etr_reset(); 294 if (store_clock(&time) == 0) 295 return time; 296 /* TOD clock not running. Set the clock to Unix Epoch. */ 297 if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0) 298 panic("TOD clock not operational."); 299 300 return TOD_UNIX_EPOCH; 301 } 302 303 static cycle_t read_tod_clock(void) 304 { 305 return get_clock(); 306 } 307 308 static struct clocksource clocksource_tod = { 309 .name = "tod", 310 .rating = 100, 311 .read = read_tod_clock, 312 .mask = -1ULL, 313 .mult = 1000, 314 .shift = 12, 315 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 316 }; 317 318 319 /* 320 * Initialize the TOD clock and the CPU timer of 321 * the boot cpu. 322 */ 323 void __init time_init(void) 324 { 325 init_timer_cc = reset_tod_clock(); 326 xtime_cc = init_timer_cc + CLK_TICKS_PER_JIFFY; 327 jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY; 328 329 /* set xtime */ 330 tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime); 331 set_normalized_timespec(&wall_to_monotonic, 332 -xtime.tv_sec, -xtime.tv_nsec); 333 334 /* request the clock comparator external interrupt */ 335 if (register_early_external_interrupt(0x1004, 336 clock_comparator_interrupt, 337 &ext_int_info_cc) != 0) 338 panic("Couldn't request external interrupt 0x1004"); 339 340 if (clocksource_register(&clocksource_tod) != 0) 341 panic("Could not register TOD clock source"); 342 343 /* request the etr external interrupt */ 344 if (register_early_external_interrupt(0x1406, etr_ext_handler, 345 &ext_int_etr_cc) != 0) 346 panic("Couldn't request external interrupt 0x1406"); 347 348 /* Enable TOD clock interrupts on the boot cpu. */ 349 init_cpu_timer(); 350 351 #ifdef CONFIG_NO_IDLE_HZ 352 nohz_init(); 353 #endif 354 355 #ifdef CONFIG_VIRT_TIMER 356 vtime_init(); 357 #endif 358 } 359 360 /* 361 * External Time Reference (ETR) code. 362 */ 363 static int etr_port0_online; 364 static int etr_port1_online; 365 366 static int __init early_parse_etr(char *p) 367 { 368 if (strncmp(p, "off", 3) == 0) 369 etr_port0_online = etr_port1_online = 0; 370 else if (strncmp(p, "port0", 5) == 0) 371 etr_port0_online = 1; 372 else if (strncmp(p, "port1", 5) == 0) 373 etr_port1_online = 1; 374 else if (strncmp(p, "on", 2) == 0) 375 etr_port0_online = etr_port1_online = 1; 376 return 0; 377 } 378 early_param("etr", early_parse_etr); 379 380 enum etr_event { 381 ETR_EVENT_PORT0_CHANGE, 382 ETR_EVENT_PORT1_CHANGE, 383 ETR_EVENT_PORT_ALERT, 384 ETR_EVENT_SYNC_CHECK, 385 ETR_EVENT_SWITCH_LOCAL, 386 ETR_EVENT_UPDATE, 387 }; 388 389 enum etr_flags { 390 ETR_FLAG_ENOSYS, 391 ETR_FLAG_EACCES, 392 ETR_FLAG_STEAI, 393 }; 394 395 /* 396 * Valid bit combinations of the eacr register are (x = don't care): 397 * e0 e1 dp p0 p1 ea es sl 398 * 0 0 x 0 0 0 0 0 initial, disabled state 399 * 0 0 x 0 1 1 0 0 port 1 online 400 * 0 0 x 1 0 1 0 0 port 0 online 401 * 0 0 x 1 1 1 0 0 both ports online 402 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode 403 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode 404 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync 405 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync 406 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable 407 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync 408 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync 409 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode 410 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode 411 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync 412 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync 413 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable 414 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync 415 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync 416 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync 417 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync 418 */ 419 static struct etr_eacr etr_eacr; 420 static u64 etr_tolec; /* time of last eacr update */ 421 static unsigned long etr_flags; 422 static struct etr_aib etr_port0; 423 static int etr_port0_uptodate; 424 static struct etr_aib etr_port1; 425 static int etr_port1_uptodate; 426 static unsigned long etr_events; 427 static struct timer_list etr_timer; 428 static DEFINE_PER_CPU(atomic_t, etr_sync_word); 429 430 static void etr_timeout(unsigned long dummy); 431 static void etr_work_fn(struct work_struct *work); 432 static DECLARE_WORK(etr_work, etr_work_fn); 433 434 /* 435 * The etr get_clock function. It will write the current clock value 436 * to the clock pointer and return 0 if the clock is in sync with the 437 * external time source. If the clock mode is local it will return 438 * -ENOSYS and -EAGAIN if the clock is not in sync with the external 439 * reference. This function is what ETR is all about.. 440 */ 441 int get_sync_clock(unsigned long long *clock) 442 { 443 atomic_t *sw_ptr; 444 unsigned int sw0, sw1; 445 446 sw_ptr = &get_cpu_var(etr_sync_word); 447 sw0 = atomic_read(sw_ptr); 448 *clock = get_clock(); 449 sw1 = atomic_read(sw_ptr); 450 put_cpu_var(etr_sync_sync); 451 if (sw0 == sw1 && (sw0 & 0x80000000U)) 452 /* Success: time is in sync. */ 453 return 0; 454 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 455 return -ENOSYS; 456 if (test_bit(ETR_FLAG_EACCES, &etr_flags)) 457 return -EACCES; 458 return -EAGAIN; 459 } 460 EXPORT_SYMBOL(get_sync_clock); 461 462 /* 463 * Make get_sync_clock return -EAGAIN. 464 */ 465 static void etr_disable_sync_clock(void *dummy) 466 { 467 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); 468 /* 469 * Clear the in-sync bit 2^31. All get_sync_clock calls will 470 * fail until the sync bit is turned back on. In addition 471 * increase the "sequence" counter to avoid the race of an 472 * etr event and the complete recovery against get_sync_clock. 473 */ 474 atomic_clear_mask(0x80000000, sw_ptr); 475 atomic_inc(sw_ptr); 476 } 477 478 /* 479 * Make get_sync_clock return 0 again. 480 * Needs to be called from a context disabled for preemption. 481 */ 482 static void etr_enable_sync_clock(void) 483 { 484 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); 485 atomic_set_mask(0x80000000, sw_ptr); 486 } 487 488 /* 489 * Reset ETR attachment. 490 */ 491 static void etr_reset(void) 492 { 493 etr_eacr = (struct etr_eacr) { 494 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, 495 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, 496 .es = 0, .sl = 0 }; 497 if (etr_setr(&etr_eacr) == 0) 498 etr_tolec = get_clock(); 499 else { 500 set_bit(ETR_FLAG_ENOSYS, &etr_flags); 501 if (etr_port0_online || etr_port1_online) { 502 printk(KERN_WARNING "Running on non ETR capable " 503 "machine, only local mode available.\n"); 504 etr_port0_online = etr_port1_online = 0; 505 } 506 } 507 } 508 509 static int __init etr_init(void) 510 { 511 struct etr_aib aib; 512 513 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 514 return 0; 515 /* Check if this machine has the steai instruction. */ 516 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) 517 set_bit(ETR_FLAG_STEAI, &etr_flags); 518 setup_timer(&etr_timer, etr_timeout, 0UL); 519 if (!etr_port0_online && !etr_port1_online) 520 set_bit(ETR_FLAG_EACCES, &etr_flags); 521 if (etr_port0_online) { 522 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 523 schedule_work(&etr_work); 524 } 525 if (etr_port1_online) { 526 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 527 schedule_work(&etr_work); 528 } 529 return 0; 530 } 531 532 arch_initcall(etr_init); 533 534 /* 535 * Two sorts of ETR machine checks. The architecture reads: 536 * "When a machine-check niterruption occurs and if a switch-to-local or 537 * ETR-sync-check interrupt request is pending but disabled, this pending 538 * disabled interruption request is indicated and is cleared". 539 * Which means that we can get etr_switch_to_local events from the machine 540 * check handler although the interruption condition is disabled. Lovely.. 541 */ 542 543 /* 544 * Switch to local machine check. This is called when the last usable 545 * ETR port goes inactive. After switch to local the clock is not in sync. 546 */ 547 void etr_switch_to_local(void) 548 { 549 if (!etr_eacr.sl) 550 return; 551 etr_disable_sync_clock(NULL); 552 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); 553 schedule_work(&etr_work); 554 } 555 556 /* 557 * ETR sync check machine check. This is called when the ETR OTE and the 558 * local clock OTE are farther apart than the ETR sync check tolerance. 559 * After a ETR sync check the clock is not in sync. The machine check 560 * is broadcasted to all cpus at the same time. 561 */ 562 void etr_sync_check(void) 563 { 564 if (!etr_eacr.es) 565 return; 566 etr_disable_sync_clock(NULL); 567 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); 568 schedule_work(&etr_work); 569 } 570 571 /* 572 * ETR external interrupt. There are two causes: 573 * 1) port state change, check the usability of the port 574 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the 575 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) 576 * or ETR-data word 4 (edf4) has changed. 577 */ 578 static void etr_ext_handler(__u16 code) 579 { 580 struct etr_interruption_parameter *intparm = 581 (struct etr_interruption_parameter *) &S390_lowcore.ext_params; 582 583 if (intparm->pc0) 584 /* ETR port 0 state change. */ 585 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 586 if (intparm->pc1) 587 /* ETR port 1 state change. */ 588 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 589 if (intparm->eai) 590 /* 591 * ETR port alert on either port 0, 1 or both. 592 * Both ports are not up-to-date now. 593 */ 594 set_bit(ETR_EVENT_PORT_ALERT, &etr_events); 595 schedule_work(&etr_work); 596 } 597 598 static void etr_timeout(unsigned long dummy) 599 { 600 set_bit(ETR_EVENT_UPDATE, &etr_events); 601 schedule_work(&etr_work); 602 } 603 604 /* 605 * Check if the etr mode is pss. 606 */ 607 static inline int etr_mode_is_pps(struct etr_eacr eacr) 608 { 609 return eacr.es && !eacr.sl; 610 } 611 612 /* 613 * Check if the etr mode is etr. 614 */ 615 static inline int etr_mode_is_etr(struct etr_eacr eacr) 616 { 617 return eacr.es && eacr.sl; 618 } 619 620 /* 621 * Check if the port can be used for TOD synchronization. 622 * For PPS mode the port has to receive OTEs. For ETR mode 623 * the port has to receive OTEs, the ETR stepping bit has to 624 * be zero and the validity bits for data frame 1, 2, and 3 625 * have to be 1. 626 */ 627 static int etr_port_valid(struct etr_aib *aib, int port) 628 { 629 unsigned int psc; 630 631 /* Check that this port is receiving OTEs. */ 632 if (aib->tsp == 0) 633 return 0; 634 635 psc = port ? aib->esw.psc1 : aib->esw.psc0; 636 if (psc == etr_lpsc_pps_mode) 637 return 1; 638 if (psc == etr_lpsc_operational_step) 639 return !aib->esw.y && aib->slsw.v1 && 640 aib->slsw.v2 && aib->slsw.v3; 641 return 0; 642 } 643 644 /* 645 * Check if two ports are on the same network. 646 */ 647 static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) 648 { 649 // FIXME: any other fields we have to compare? 650 return aib1->edf1.net_id == aib2->edf1.net_id; 651 } 652 653 /* 654 * Wrapper for etr_stei that converts physical port states 655 * to logical port states to be consistent with the output 656 * of stetr (see etr_psc vs. etr_lpsc). 657 */ 658 static void etr_steai_cv(struct etr_aib *aib, unsigned int func) 659 { 660 BUG_ON(etr_steai(aib, func) != 0); 661 /* Convert port state to logical port state. */ 662 if (aib->esw.psc0 == 1) 663 aib->esw.psc0 = 2; 664 else if (aib->esw.psc0 == 0 && aib->esw.p == 0) 665 aib->esw.psc0 = 1; 666 if (aib->esw.psc1 == 1) 667 aib->esw.psc1 = 2; 668 else if (aib->esw.psc1 == 0 && aib->esw.p == 1) 669 aib->esw.psc1 = 1; 670 } 671 672 /* 673 * Check if the aib a2 is still connected to the same attachment as 674 * aib a1, the etv values differ by one and a2 is valid. 675 */ 676 static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) 677 { 678 int state_a1, state_a2; 679 680 /* Paranoia check: e0/e1 should better be the same. */ 681 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || 682 a1->esw.eacr.e1 != a2->esw.eacr.e1) 683 return 0; 684 685 /* Still connected to the same etr ? */ 686 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; 687 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; 688 if (state_a1 == etr_lpsc_operational_step) { 689 if (state_a2 != etr_lpsc_operational_step || 690 a1->edf1.net_id != a2->edf1.net_id || 691 a1->edf1.etr_id != a2->edf1.etr_id || 692 a1->edf1.etr_pn != a2->edf1.etr_pn) 693 return 0; 694 } else if (state_a2 != etr_lpsc_pps_mode) 695 return 0; 696 697 /* The ETV value of a2 needs to be ETV of a1 + 1. */ 698 if (a1->edf2.etv + 1 != a2->edf2.etv) 699 return 0; 700 701 if (!etr_port_valid(a2, p)) 702 return 0; 703 704 return 1; 705 } 706 707 /* 708 * The time is "clock". xtime is what we think the time is. 709 * Adjust the value by a multiple of jiffies and add the delta to ntp. 710 * "delay" is an approximation how long the synchronization took. If 711 * the time correction is positive, then "delay" is subtracted from 712 * the time difference and only the remaining part is passed to ntp. 713 */ 714 static void etr_adjust_time(unsigned long long clock, unsigned long long delay) 715 { 716 unsigned long long delta, ticks; 717 struct timex adjust; 718 719 /* 720 * We don't have to take the xtime lock because the cpu 721 * executing etr_adjust_time is running disabled in 722 * tasklet context and all other cpus are looping in 723 * etr_sync_cpu_start. 724 */ 725 if (clock > xtime_cc) { 726 /* It is later than we thought. */ 727 delta = ticks = clock - xtime_cc; 728 delta = ticks = (delta < delay) ? 0 : delta - delay; 729 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); 730 init_timer_cc = init_timer_cc + delta; 731 jiffies_timer_cc = jiffies_timer_cc + delta; 732 xtime_cc = xtime_cc + delta; 733 adjust.offset = ticks * (1000000 / HZ); 734 } else { 735 /* It is earlier than we thought. */ 736 delta = ticks = xtime_cc - clock; 737 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); 738 init_timer_cc = init_timer_cc - delta; 739 jiffies_timer_cc = jiffies_timer_cc - delta; 740 xtime_cc = xtime_cc - delta; 741 adjust.offset = -ticks * (1000000 / HZ); 742 } 743 if (adjust.offset != 0) { 744 printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n", 745 adjust.offset); 746 adjust.modes = ADJ_OFFSET_SINGLESHOT; 747 do_adjtimex(&adjust); 748 } 749 } 750 751 #ifdef CONFIG_SMP 752 static void etr_sync_cpu_start(void *dummy) 753 { 754 int *in_sync = dummy; 755 756 etr_enable_sync_clock(); 757 /* 758 * This looks like a busy wait loop but it isn't. etr_sync_cpus 759 * is called on all other cpus while the TOD clocks is stopped. 760 * __udelay will stop the cpu on an enabled wait psw until the 761 * TOD is running again. 762 */ 763 while (*in_sync == 0) { 764 __udelay(1); 765 /* 766 * A different cpu changes *in_sync. Therefore use 767 * barrier() to force memory access. 768 */ 769 barrier(); 770 } 771 if (*in_sync != 1) 772 /* Didn't work. Clear per-cpu in sync bit again. */ 773 etr_disable_sync_clock(NULL); 774 /* 775 * This round of TOD syncing is done. Set the clock comparator 776 * to the next tick and let the processor continue. 777 */ 778 setup_jiffy_timer(); 779 } 780 781 static void etr_sync_cpu_end(void *dummy) 782 { 783 } 784 #endif /* CONFIG_SMP */ 785 786 /* 787 * Sync the TOD clock using the port refered to by aibp. This port 788 * has to be enabled and the other port has to be disabled. The 789 * last eacr update has to be more than 1.6 seconds in the past. 790 */ 791 static int etr_sync_clock(struct etr_aib *aib, int port) 792 { 793 struct etr_aib *sync_port; 794 unsigned long long clock, delay; 795 int in_sync, follows; 796 int rc; 797 798 /* Check if the current aib is adjacent to the sync port aib. */ 799 sync_port = (port == 0) ? &etr_port0 : &etr_port1; 800 follows = etr_aib_follows(sync_port, aib, port); 801 memcpy(sync_port, aib, sizeof(*aib)); 802 if (!follows) 803 return -EAGAIN; 804 805 /* 806 * Catch all other cpus and make them wait until we have 807 * successfully synced the clock. smp_call_function will 808 * return after all other cpus are in etr_sync_cpu_start. 809 */ 810 in_sync = 0; 811 preempt_disable(); 812 smp_call_function(etr_sync_cpu_start,&in_sync,0,0); 813 local_irq_disable(); 814 etr_enable_sync_clock(); 815 816 /* Set clock to next OTE. */ 817 __ctl_set_bit(14, 21); 818 __ctl_set_bit(0, 29); 819 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; 820 if (set_clock(clock) == 0) { 821 __udelay(1); /* Wait for the clock to start. */ 822 __ctl_clear_bit(0, 29); 823 __ctl_clear_bit(14, 21); 824 etr_stetr(aib); 825 /* Adjust Linux timing variables. */ 826 delay = (unsigned long long) 827 (aib->edf2.etv - sync_port->edf2.etv) << 32; 828 etr_adjust_time(clock, delay); 829 setup_jiffy_timer(); 830 /* Verify that the clock is properly set. */ 831 if (!etr_aib_follows(sync_port, aib, port)) { 832 /* Didn't work. */ 833 etr_disable_sync_clock(NULL); 834 in_sync = -EAGAIN; 835 rc = -EAGAIN; 836 } else { 837 in_sync = 1; 838 rc = 0; 839 } 840 } else { 841 /* Could not set the clock ?!? */ 842 __ctl_clear_bit(0, 29); 843 __ctl_clear_bit(14, 21); 844 etr_disable_sync_clock(NULL); 845 in_sync = -EAGAIN; 846 rc = -EAGAIN; 847 } 848 local_irq_enable(); 849 smp_call_function(etr_sync_cpu_end,NULL,0,0); 850 preempt_enable(); 851 return rc; 852 } 853 854 /* 855 * Handle the immediate effects of the different events. 856 * The port change event is used for online/offline changes. 857 */ 858 static struct etr_eacr etr_handle_events(struct etr_eacr eacr) 859 { 860 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) 861 eacr.es = 0; 862 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) 863 eacr.es = eacr.sl = 0; 864 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) 865 etr_port0_uptodate = etr_port1_uptodate = 0; 866 867 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { 868 if (eacr.e0) 869 /* 870 * Port change of an enabled port. We have to 871 * assume that this can have caused an stepping 872 * port switch. 873 */ 874 etr_tolec = get_clock(); 875 eacr.p0 = etr_port0_online; 876 if (!eacr.p0) 877 eacr.e0 = 0; 878 etr_port0_uptodate = 0; 879 } 880 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { 881 if (eacr.e1) 882 /* 883 * Port change of an enabled port. We have to 884 * assume that this can have caused an stepping 885 * port switch. 886 */ 887 etr_tolec = get_clock(); 888 eacr.p1 = etr_port1_online; 889 if (!eacr.p1) 890 eacr.e1 = 0; 891 etr_port1_uptodate = 0; 892 } 893 clear_bit(ETR_EVENT_UPDATE, &etr_events); 894 return eacr; 895 } 896 897 /* 898 * Set up a timer that expires after the etr_tolec + 1.6 seconds if 899 * one of the ports needs an update. 900 */ 901 static void etr_set_tolec_timeout(unsigned long long now) 902 { 903 unsigned long micros; 904 905 if ((!etr_eacr.p0 || etr_port0_uptodate) && 906 (!etr_eacr.p1 || etr_port1_uptodate)) 907 return; 908 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; 909 micros = (micros > 1600000) ? 0 : 1600000 - micros; 910 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); 911 } 912 913 /* 914 * Set up a time that expires after 1/2 second. 915 */ 916 static void etr_set_sync_timeout(void) 917 { 918 mod_timer(&etr_timer, jiffies + HZ/2); 919 } 920 921 /* 922 * Update the aib information for one or both ports. 923 */ 924 static struct etr_eacr etr_handle_update(struct etr_aib *aib, 925 struct etr_eacr eacr) 926 { 927 /* With both ports disabled the aib information is useless. */ 928 if (!eacr.e0 && !eacr.e1) 929 return eacr; 930 931 /* Update port0 or port1 with aib stored in etr_work_fn. */ 932 if (aib->esw.q == 0) { 933 /* Information for port 0 stored. */ 934 if (eacr.p0 && !etr_port0_uptodate) { 935 etr_port0 = *aib; 936 if (etr_port0_online) 937 etr_port0_uptodate = 1; 938 } 939 } else { 940 /* Information for port 1 stored. */ 941 if (eacr.p1 && !etr_port1_uptodate) { 942 etr_port1 = *aib; 943 if (etr_port0_online) 944 etr_port1_uptodate = 1; 945 } 946 } 947 948 /* 949 * Do not try to get the alternate port aib if the clock 950 * is not in sync yet. 951 */ 952 if (!eacr.es) 953 return eacr; 954 955 /* 956 * If steai is available we can get the information about 957 * the other port immediately. If only stetr is available the 958 * data-port bit toggle has to be used. 959 */ 960 if (test_bit(ETR_FLAG_STEAI, &etr_flags)) { 961 if (eacr.p0 && !etr_port0_uptodate) { 962 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); 963 etr_port0_uptodate = 1; 964 } 965 if (eacr.p1 && !etr_port1_uptodate) { 966 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); 967 etr_port1_uptodate = 1; 968 } 969 } else { 970 /* 971 * One port was updated above, if the other 972 * port is not uptodate toggle dp bit. 973 */ 974 if ((eacr.p0 && !etr_port0_uptodate) || 975 (eacr.p1 && !etr_port1_uptodate)) 976 eacr.dp ^= 1; 977 else 978 eacr.dp = 0; 979 } 980 return eacr; 981 } 982 983 /* 984 * Write new etr control register if it differs from the current one. 985 * Return 1 if etr_tolec has been updated as well. 986 */ 987 static void etr_update_eacr(struct etr_eacr eacr) 988 { 989 int dp_changed; 990 991 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) 992 /* No change, return. */ 993 return; 994 /* 995 * The disable of an active port of the change of the data port 996 * bit can/will cause a change in the data port. 997 */ 998 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || 999 (etr_eacr.dp ^ eacr.dp) != 0; 1000 etr_eacr = eacr; 1001 etr_setr(&etr_eacr); 1002 if (dp_changed) 1003 etr_tolec = get_clock(); 1004 } 1005 1006 /* 1007 * ETR tasklet. In this function you'll find the main logic. In 1008 * particular this is the only function that calls etr_update_eacr(), 1009 * it "controls" the etr control register. 1010 */ 1011 static void etr_work_fn(struct work_struct *work) 1012 { 1013 unsigned long long now; 1014 struct etr_eacr eacr; 1015 struct etr_aib aib; 1016 int sync_port; 1017 1018 /* Create working copy of etr_eacr. */ 1019 eacr = etr_eacr; 1020 1021 /* Check for the different events and their immediate effects. */ 1022 eacr = etr_handle_events(eacr); 1023 1024 /* Check if ETR is supposed to be active. */ 1025 eacr.ea = eacr.p0 || eacr.p1; 1026 if (!eacr.ea) { 1027 /* Both ports offline. Reset everything. */ 1028 eacr.dp = eacr.es = eacr.sl = 0; 1029 on_each_cpu(etr_disable_sync_clock, NULL, 0, 1); 1030 del_timer_sync(&etr_timer); 1031 etr_update_eacr(eacr); 1032 set_bit(ETR_FLAG_EACCES, &etr_flags); 1033 return; 1034 } 1035 1036 /* Store aib to get the current ETR status word. */ 1037 BUG_ON(etr_stetr(&aib) != 0); 1038 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ 1039 now = get_clock(); 1040 1041 /* 1042 * Update the port information if the last stepping port change 1043 * or data port change is older than 1.6 seconds. 1044 */ 1045 if (now >= etr_tolec + (1600000 << 12)) 1046 eacr = etr_handle_update(&aib, eacr); 1047 1048 /* 1049 * Select ports to enable. The prefered synchronization mode is PPS. 1050 * If a port can be enabled depends on a number of things: 1051 * 1) The port needs to be online and uptodate. A port is not 1052 * disabled just because it is not uptodate, but it is only 1053 * enabled if it is uptodate. 1054 * 2) The port needs to have the same mode (pps / etr). 1055 * 3) The port needs to be usable -> etr_port_valid() == 1 1056 * 4) To enable the second port the clock needs to be in sync. 1057 * 5) If both ports are useable and are ETR ports, the network id 1058 * has to be the same. 1059 * The eacr.sl bit is used to indicate etr mode vs. pps mode. 1060 */ 1061 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { 1062 eacr.sl = 0; 1063 eacr.e0 = 1; 1064 if (!etr_mode_is_pps(etr_eacr)) 1065 eacr.es = 0; 1066 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) 1067 eacr.e1 = 0; 1068 // FIXME: uptodate checks ? 1069 else if (etr_port0_uptodate && etr_port1_uptodate) 1070 eacr.e1 = 1; 1071 sync_port = (etr_port0_uptodate && 1072 etr_port_valid(&etr_port0, 0)) ? 0 : -1; 1073 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1074 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { 1075 eacr.sl = 0; 1076 eacr.e0 = 0; 1077 eacr.e1 = 1; 1078 if (!etr_mode_is_pps(etr_eacr)) 1079 eacr.es = 0; 1080 sync_port = (etr_port1_uptodate && 1081 etr_port_valid(&etr_port1, 1)) ? 1 : -1; 1082 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1083 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { 1084 eacr.sl = 1; 1085 eacr.e0 = 1; 1086 if (!etr_mode_is_etr(etr_eacr)) 1087 eacr.es = 0; 1088 if (!eacr.es || !eacr.p1 || 1089 aib.esw.psc1 != etr_lpsc_operational_alt) 1090 eacr.e1 = 0; 1091 else if (etr_port0_uptodate && etr_port1_uptodate && 1092 etr_compare_network(&etr_port0, &etr_port1)) 1093 eacr.e1 = 1; 1094 sync_port = (etr_port0_uptodate && 1095 etr_port_valid(&etr_port0, 0)) ? 0 : -1; 1096 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1097 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { 1098 eacr.sl = 1; 1099 eacr.e0 = 0; 1100 eacr.e1 = 1; 1101 if (!etr_mode_is_etr(etr_eacr)) 1102 eacr.es = 0; 1103 sync_port = (etr_port1_uptodate && 1104 etr_port_valid(&etr_port1, 1)) ? 1 : -1; 1105 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1106 } else { 1107 /* Both ports not usable. */ 1108 eacr.es = eacr.sl = 0; 1109 sync_port = -1; 1110 set_bit(ETR_FLAG_EACCES, &etr_flags); 1111 } 1112 1113 /* 1114 * If the clock is in sync just update the eacr and return. 1115 * If there is no valid sync port wait for a port update. 1116 */ 1117 if (eacr.es || sync_port < 0) { 1118 etr_update_eacr(eacr); 1119 etr_set_tolec_timeout(now); 1120 return; 1121 } 1122 1123 /* 1124 * Prepare control register for clock syncing 1125 * (reset data port bit, set sync check control. 1126 */ 1127 eacr.dp = 0; 1128 eacr.es = 1; 1129 1130 /* 1131 * Update eacr and try to synchronize the clock. If the update 1132 * of eacr caused a stepping port switch (or if we have to 1133 * assume that a stepping port switch has occured) or the 1134 * clock syncing failed, reset the sync check control bit 1135 * and set up a timer to try again after 0.5 seconds 1136 */ 1137 etr_update_eacr(eacr); 1138 if (now < etr_tolec + (1600000 << 12) || 1139 etr_sync_clock(&aib, sync_port) != 0) { 1140 /* Sync failed. Try again in 1/2 second. */ 1141 eacr.es = 0; 1142 etr_update_eacr(eacr); 1143 etr_set_sync_timeout(); 1144 } else 1145 etr_set_tolec_timeout(now); 1146 } 1147 1148 /* 1149 * Sysfs interface functions 1150 */ 1151 static struct sysdev_class etr_sysclass = { 1152 set_kset_name("etr") 1153 }; 1154 1155 static struct sys_device etr_port0_dev = { 1156 .id = 0, 1157 .cls = &etr_sysclass, 1158 }; 1159 1160 static struct sys_device etr_port1_dev = { 1161 .id = 1, 1162 .cls = &etr_sysclass, 1163 }; 1164 1165 /* 1166 * ETR class attributes 1167 */ 1168 static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf) 1169 { 1170 return sprintf(buf, "%i\n", etr_port0.esw.p); 1171 } 1172 1173 static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); 1174 1175 static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf) 1176 { 1177 char *mode_str; 1178 1179 if (etr_mode_is_pps(etr_eacr)) 1180 mode_str = "pps"; 1181 else if (etr_mode_is_etr(etr_eacr)) 1182 mode_str = "etr"; 1183 else 1184 mode_str = "local"; 1185 return sprintf(buf, "%s\n", mode_str); 1186 } 1187 1188 static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); 1189 1190 /* 1191 * ETR port attributes 1192 */ 1193 static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev) 1194 { 1195 if (dev == &etr_port0_dev) 1196 return etr_port0_online ? &etr_port0 : NULL; 1197 else 1198 return etr_port1_online ? &etr_port1 : NULL; 1199 } 1200 1201 static ssize_t etr_online_show(struct sys_device *dev, char *buf) 1202 { 1203 unsigned int online; 1204 1205 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; 1206 return sprintf(buf, "%i\n", online); 1207 } 1208 1209 static ssize_t etr_online_store(struct sys_device *dev, 1210 const char *buf, size_t count) 1211 { 1212 unsigned int value; 1213 1214 value = simple_strtoul(buf, NULL, 0); 1215 if (value != 0 && value != 1) 1216 return -EINVAL; 1217 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 1218 return -ENOSYS; 1219 if (dev == &etr_port0_dev) { 1220 if (etr_port0_online == value) 1221 return count; /* Nothing to do. */ 1222 etr_port0_online = value; 1223 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 1224 schedule_work(&etr_work); 1225 } else { 1226 if (etr_port1_online == value) 1227 return count; /* Nothing to do. */ 1228 etr_port1_online = value; 1229 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 1230 schedule_work(&etr_work); 1231 } 1232 return count; 1233 } 1234 1235 static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store); 1236 1237 static ssize_t etr_stepping_control_show(struct sys_device *dev, char *buf) 1238 { 1239 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? 1240 etr_eacr.e0 : etr_eacr.e1); 1241 } 1242 1243 static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); 1244 1245 static ssize_t etr_mode_code_show(struct sys_device *dev, char *buf) 1246 { 1247 if (!etr_port0_online && !etr_port1_online) 1248 /* Status word is not uptodate if both ports are offline. */ 1249 return -ENODATA; 1250 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? 1251 etr_port0.esw.psc0 : etr_port0.esw.psc1); 1252 } 1253 1254 static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL); 1255 1256 static ssize_t etr_untuned_show(struct sys_device *dev, char *buf) 1257 { 1258 struct etr_aib *aib = etr_aib_from_dev(dev); 1259 1260 if (!aib || !aib->slsw.v1) 1261 return -ENODATA; 1262 return sprintf(buf, "%i\n", aib->edf1.u); 1263 } 1264 1265 static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL); 1266 1267 static ssize_t etr_network_id_show(struct sys_device *dev, char *buf) 1268 { 1269 struct etr_aib *aib = etr_aib_from_dev(dev); 1270 1271 if (!aib || !aib->slsw.v1) 1272 return -ENODATA; 1273 return sprintf(buf, "%i\n", aib->edf1.net_id); 1274 } 1275 1276 static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL); 1277 1278 static ssize_t etr_id_show(struct sys_device *dev, char *buf) 1279 { 1280 struct etr_aib *aib = etr_aib_from_dev(dev); 1281 1282 if (!aib || !aib->slsw.v1) 1283 return -ENODATA; 1284 return sprintf(buf, "%i\n", aib->edf1.etr_id); 1285 } 1286 1287 static SYSDEV_ATTR(id, 0400, etr_id_show, NULL); 1288 1289 static ssize_t etr_port_number_show(struct sys_device *dev, char *buf) 1290 { 1291 struct etr_aib *aib = etr_aib_from_dev(dev); 1292 1293 if (!aib || !aib->slsw.v1) 1294 return -ENODATA; 1295 return sprintf(buf, "%i\n", aib->edf1.etr_pn); 1296 } 1297 1298 static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL); 1299 1300 static ssize_t etr_coupled_show(struct sys_device *dev, char *buf) 1301 { 1302 struct etr_aib *aib = etr_aib_from_dev(dev); 1303 1304 if (!aib || !aib->slsw.v3) 1305 return -ENODATA; 1306 return sprintf(buf, "%i\n", aib->edf3.c); 1307 } 1308 1309 static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL); 1310 1311 static ssize_t etr_local_time_show(struct sys_device *dev, char *buf) 1312 { 1313 struct etr_aib *aib = etr_aib_from_dev(dev); 1314 1315 if (!aib || !aib->slsw.v3) 1316 return -ENODATA; 1317 return sprintf(buf, "%i\n", aib->edf3.blto); 1318 } 1319 1320 static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL); 1321 1322 static ssize_t etr_utc_offset_show(struct sys_device *dev, char *buf) 1323 { 1324 struct etr_aib *aib = etr_aib_from_dev(dev); 1325 1326 if (!aib || !aib->slsw.v3) 1327 return -ENODATA; 1328 return sprintf(buf, "%i\n", aib->edf3.buo); 1329 } 1330 1331 static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); 1332 1333 static struct sysdev_attribute *etr_port_attributes[] = { 1334 &attr_online, 1335 &attr_stepping_control, 1336 &attr_state_code, 1337 &attr_untuned, 1338 &attr_network, 1339 &attr_id, 1340 &attr_port, 1341 &attr_coupled, 1342 &attr_local_time, 1343 &attr_utc_offset, 1344 NULL 1345 }; 1346 1347 static int __init etr_register_port(struct sys_device *dev) 1348 { 1349 struct sysdev_attribute **attr; 1350 int rc; 1351 1352 rc = sysdev_register(dev); 1353 if (rc) 1354 goto out; 1355 for (attr = etr_port_attributes; *attr; attr++) { 1356 rc = sysdev_create_file(dev, *attr); 1357 if (rc) 1358 goto out_unreg; 1359 } 1360 return 0; 1361 out_unreg: 1362 for (; attr >= etr_port_attributes; attr--) 1363 sysdev_remove_file(dev, *attr); 1364 sysdev_unregister(dev); 1365 out: 1366 return rc; 1367 } 1368 1369 static void __init etr_unregister_port(struct sys_device *dev) 1370 { 1371 struct sysdev_attribute **attr; 1372 1373 for (attr = etr_port_attributes; *attr; attr++) 1374 sysdev_remove_file(dev, *attr); 1375 sysdev_unregister(dev); 1376 } 1377 1378 static int __init etr_init_sysfs(void) 1379 { 1380 int rc; 1381 1382 rc = sysdev_class_register(&etr_sysclass); 1383 if (rc) 1384 goto out; 1385 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port); 1386 if (rc) 1387 goto out_unreg_class; 1388 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode); 1389 if (rc) 1390 goto out_remove_stepping_port; 1391 rc = etr_register_port(&etr_port0_dev); 1392 if (rc) 1393 goto out_remove_stepping_mode; 1394 rc = etr_register_port(&etr_port1_dev); 1395 if (rc) 1396 goto out_remove_port0; 1397 return 0; 1398 1399 out_remove_port0: 1400 etr_unregister_port(&etr_port0_dev); 1401 out_remove_stepping_mode: 1402 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode); 1403 out_remove_stepping_port: 1404 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port); 1405 out_unreg_class: 1406 sysdev_class_unregister(&etr_sysclass); 1407 out: 1408 return rc; 1409 } 1410 1411 device_initcall(etr_init_sysfs); 1412