1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/interrupt.h> 13 #include <linux/seq_file.h> 14 #include <linux/proc_fs.h> 15 #include <linux/profile.h> 16 #include <linux/export.h> 17 #include <linux/kernel.h> 18 #include <linux/ftrace.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/init.h> 22 #include <linux/cpu.h> 23 #include <linux/irq.h> 24 #include <linux/entry-common.h> 25 #include <asm/irq_regs.h> 26 #include <asm/cputime.h> 27 #include <asm/lowcore.h> 28 #include <asm/irq.h> 29 #include <asm/hw_irq.h> 30 #include <asm/stacktrace.h> 31 #include "entry.h" 32 33 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 34 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 35 36 struct irq_class { 37 int irq; 38 char *name; 39 char *desc; 40 }; 41 42 /* 43 * The list of "main" irq classes on s390. This is the list of interrupts 44 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 45 * Historically only external and I/O interrupts have been part of /proc/stat. 46 * We can't add the split external and I/O sub classes since the first field 47 * in the "intr" line in /proc/stat is supposed to be the sum of all other 48 * fields. 49 * Since the external and I/O interrupt fields are already sums we would end 50 * up with having a sum which accounts each interrupt twice. 51 */ 52 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 53 {.irq = EXT_INTERRUPT, .name = "EXT"}, 54 {.irq = IO_INTERRUPT, .name = "I/O"}, 55 {.irq = THIN_INTERRUPT, .name = "AIO"}, 56 }; 57 58 /* 59 * The list of split external and I/O interrupts that appear only in 60 * /proc/interrupts. 61 * In addition this list contains non external / I/O events like NMIs. 62 */ 63 static const struct irq_class irqclass_sub_desc[] = { 64 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 65 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 66 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 67 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 68 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 69 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 70 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 71 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 72 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 73 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 74 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 75 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 76 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 77 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 78 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 79 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 80 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 81 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 82 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 83 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"}, 84 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 85 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 86 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 87 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 88 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 89 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 90 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 91 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 92 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 93 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 94 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 95 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 96 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 97 }; 98 99 static void do_IRQ(struct pt_regs *regs, int irq) 100 { 101 if (tod_after_eq(S390_lowcore.int_clock, 102 S390_lowcore.clock_comparator)) 103 /* Serve timer interrupts first. */ 104 clock_comparator_work(); 105 generic_handle_irq(irq); 106 } 107 108 static int on_async_stack(void) 109 { 110 unsigned long frame = current_frame_address(); 111 112 return !!!((S390_lowcore.async_stack - frame) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)); 113 } 114 115 static void do_irq_async(struct pt_regs *regs, int irq) 116 { 117 if (on_async_stack()) 118 do_IRQ(regs, irq); 119 else 120 CALL_ON_STACK(do_IRQ, S390_lowcore.async_stack, 2, regs, irq); 121 } 122 123 static int irq_pending(struct pt_regs *regs) 124 { 125 int cc; 126 127 asm volatile("tpi 0\n" 128 "ipm %0" : "=d" (cc) : : "cc"); 129 return cc >> 28; 130 } 131 132 void noinstr do_io_irq(struct pt_regs *regs) 133 { 134 irqentry_state_t state = irqentry_enter(regs); 135 struct pt_regs *old_regs = set_irq_regs(regs); 136 int from_idle; 137 138 irq_enter(); 139 140 if (user_mode(regs)) 141 update_timer_sys(); 142 143 from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit; 144 if (from_idle) 145 account_idle_time_irq(); 146 147 do { 148 memcpy(®s->int_code, &S390_lowcore.subchannel_id, 12); 149 if (S390_lowcore.io_int_word & BIT(31)) 150 do_irq_async(regs, THIN_INTERRUPT); 151 else 152 do_irq_async(regs, IO_INTERRUPT); 153 } while (MACHINE_IS_LPAR && irq_pending(regs)); 154 155 irq_exit(); 156 set_irq_regs(old_regs); 157 irqentry_exit(regs, state); 158 159 if (from_idle) 160 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 161 } 162 163 void noinstr do_ext_irq(struct pt_regs *regs) 164 { 165 irqentry_state_t state = irqentry_enter(regs); 166 struct pt_regs *old_regs = set_irq_regs(regs); 167 int from_idle; 168 169 irq_enter(); 170 171 if (user_mode(regs)) 172 update_timer_sys(); 173 174 memcpy(®s->int_code, &S390_lowcore.ext_cpu_addr, 4); 175 regs->int_parm = S390_lowcore.ext_params; 176 regs->int_parm_long = *(unsigned long *)S390_lowcore.ext_params2; 177 178 from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit; 179 if (from_idle) 180 account_idle_time_irq(); 181 182 do_irq_async(regs, EXT_INTERRUPT); 183 184 irq_exit(); 185 set_irq_regs(old_regs); 186 irqentry_exit(regs, state); 187 188 if (from_idle) 189 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 190 } 191 192 static void show_msi_interrupt(struct seq_file *p, int irq) 193 { 194 struct irq_desc *desc; 195 unsigned long flags; 196 int cpu; 197 198 irq_lock_sparse(); 199 desc = irq_to_desc(irq); 200 if (!desc) 201 goto out; 202 203 raw_spin_lock_irqsave(&desc->lock, flags); 204 seq_printf(p, "%3d: ", irq); 205 for_each_online_cpu(cpu) 206 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 207 208 if (desc->irq_data.chip) 209 seq_printf(p, " %8s", desc->irq_data.chip->name); 210 211 if (desc->action) 212 seq_printf(p, " %s", desc->action->name); 213 214 seq_putc(p, '\n'); 215 raw_spin_unlock_irqrestore(&desc->lock, flags); 216 out: 217 irq_unlock_sparse(); 218 } 219 220 /* 221 * show_interrupts is needed by /proc/interrupts. 222 */ 223 int show_interrupts(struct seq_file *p, void *v) 224 { 225 int index = *(loff_t *) v; 226 int cpu, irq; 227 228 get_online_cpus(); 229 if (index == 0) { 230 seq_puts(p, " "); 231 for_each_online_cpu(cpu) 232 seq_printf(p, "CPU%-8d", cpu); 233 seq_putc(p, '\n'); 234 } 235 if (index < NR_IRQS_BASE) { 236 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 237 irq = irqclass_main_desc[index].irq; 238 for_each_online_cpu(cpu) 239 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 240 seq_putc(p, '\n'); 241 goto out; 242 } 243 if (index < nr_irqs) { 244 show_msi_interrupt(p, index); 245 goto out; 246 } 247 for (index = 0; index < NR_ARCH_IRQS; index++) { 248 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 249 irq = irqclass_sub_desc[index].irq; 250 for_each_online_cpu(cpu) 251 seq_printf(p, "%10u ", 252 per_cpu(irq_stat, cpu).irqs[irq]); 253 if (irqclass_sub_desc[index].desc) 254 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 255 seq_putc(p, '\n'); 256 } 257 out: 258 put_online_cpus(); 259 return 0; 260 } 261 262 unsigned int arch_dynirq_lower_bound(unsigned int from) 263 { 264 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 265 } 266 267 /* 268 * Switch to the asynchronous interrupt stack for softirq execution. 269 */ 270 void do_softirq_own_stack(void) 271 { 272 unsigned long old, new; 273 274 old = current_stack_pointer(); 275 /* Check against async. stack address range. */ 276 new = S390_lowcore.async_stack; 277 if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) { 278 CALL_ON_STACK(__do_softirq, new, 0); 279 } else { 280 /* We are already on the async stack. */ 281 __do_softirq(); 282 } 283 } 284 285 /* 286 * ext_int_hash[index] is the list head for all external interrupts that hash 287 * to this index. 288 */ 289 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 290 291 struct ext_int_info { 292 ext_int_handler_t handler; 293 struct hlist_node entry; 294 struct rcu_head rcu; 295 u16 code; 296 }; 297 298 /* ext_int_hash_lock protects the handler lists for external interrupts */ 299 static DEFINE_SPINLOCK(ext_int_hash_lock); 300 301 static inline int ext_hash(u16 code) 302 { 303 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 304 305 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 306 } 307 308 int register_external_irq(u16 code, ext_int_handler_t handler) 309 { 310 struct ext_int_info *p; 311 unsigned long flags; 312 int index; 313 314 p = kmalloc(sizeof(*p), GFP_ATOMIC); 315 if (!p) 316 return -ENOMEM; 317 p->code = code; 318 p->handler = handler; 319 index = ext_hash(code); 320 321 spin_lock_irqsave(&ext_int_hash_lock, flags); 322 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 323 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 324 return 0; 325 } 326 EXPORT_SYMBOL(register_external_irq); 327 328 int unregister_external_irq(u16 code, ext_int_handler_t handler) 329 { 330 struct ext_int_info *p; 331 unsigned long flags; 332 int index = ext_hash(code); 333 334 spin_lock_irqsave(&ext_int_hash_lock, flags); 335 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 336 if (p->code == code && p->handler == handler) { 337 hlist_del_rcu(&p->entry); 338 kfree_rcu(p, rcu); 339 } 340 } 341 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 342 return 0; 343 } 344 EXPORT_SYMBOL(unregister_external_irq); 345 346 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 347 { 348 struct pt_regs *regs = get_irq_regs(); 349 struct ext_code ext_code; 350 struct ext_int_info *p; 351 int index; 352 353 ext_code = *(struct ext_code *) ®s->int_code; 354 if (ext_code.code != EXT_IRQ_CLK_COMP) 355 set_cpu_flag(CIF_NOHZ_DELAY); 356 357 index = ext_hash(ext_code.code); 358 rcu_read_lock(); 359 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 360 if (unlikely(p->code != ext_code.code)) 361 continue; 362 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 363 } 364 rcu_read_unlock(); 365 return IRQ_HANDLED; 366 } 367 368 static void __init init_ext_interrupts(void) 369 { 370 int idx; 371 372 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 373 INIT_HLIST_HEAD(&ext_int_hash[idx]); 374 375 irq_set_chip_and_handler(EXT_INTERRUPT, 376 &dummy_irq_chip, handle_percpu_irq); 377 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 378 panic("Failed to register EXT interrupt\n"); 379 } 380 381 void __init init_IRQ(void) 382 { 383 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 384 init_cio_interrupts(); 385 init_airq_interrupts(); 386 init_ext_interrupts(); 387 } 388 389 static DEFINE_SPINLOCK(irq_subclass_lock); 390 static unsigned char irq_subclass_refcount[64]; 391 392 void irq_subclass_register(enum irq_subclass subclass) 393 { 394 spin_lock(&irq_subclass_lock); 395 if (!irq_subclass_refcount[subclass]) 396 ctl_set_bit(0, subclass); 397 irq_subclass_refcount[subclass]++; 398 spin_unlock(&irq_subclass_lock); 399 } 400 EXPORT_SYMBOL(irq_subclass_register); 401 402 void irq_subclass_unregister(enum irq_subclass subclass) 403 { 404 spin_lock(&irq_subclass_lock); 405 irq_subclass_refcount[subclass]--; 406 if (!irq_subclass_refcount[subclass]) 407 ctl_clear_bit(0, subclass); 408 spin_unlock(&irq_subclass_lock); 409 } 410 EXPORT_SYMBOL(irq_subclass_unregister); 411