xref: /openbmc/linux/arch/s390/kernel/entry.S (revision 7041d28115e91f2144f811ffe8a195c696b1e1d0) 
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *    S390 low-level entry points.
4 *
5 *    Copyright IBM Corp. 1999, 2012
6 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 *		 Hartmut Penner (hp@de.ibm.com),
8 *		 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 *		 Heiko Carstens <heiko.carstens@de.ibm.com>
10 */
11
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/processor.h>
15#include <asm/cache.h>
16#include <asm/ctl_reg.h>
17#include <asm/errno.h>
18#include <asm/ptrace.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21#include <asm/unistd.h>
22#include <asm/page.h>
23#include <asm/sigp.h>
24#include <asm/irq.h>
25#include <asm/vx-insn.h>
26#include <asm/setup.h>
27#include <asm/nmi.h>
28#include <asm/export.h>
29
30__PT_R0      =	__PT_GPRS
31__PT_R1      =	__PT_GPRS + 8
32__PT_R2      =	__PT_GPRS + 16
33__PT_R3      =	__PT_GPRS + 24
34__PT_R4      =	__PT_GPRS + 32
35__PT_R5      =	__PT_GPRS + 40
36__PT_R6      =	__PT_GPRS + 48
37__PT_R7      =	__PT_GPRS + 56
38__PT_R8      =	__PT_GPRS + 64
39__PT_R9      =	__PT_GPRS + 72
40__PT_R10     =	__PT_GPRS + 80
41__PT_R11     =	__PT_GPRS + 88
42__PT_R12     =	__PT_GPRS + 96
43__PT_R13     =	__PT_GPRS + 104
44__PT_R14     =	__PT_GPRS + 112
45__PT_R15     =	__PT_GPRS + 120
46
47STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
48STACK_SIZE  = 1 << STACK_SHIFT
49STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
50
51_TIF_WORK	= (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
52		   _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
53_TIF_TRACE	= (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
54		   _TIF_SYSCALL_TRACEPOINT)
55_CIF_WORK	= (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
56		   _CIF_ASCE_SECONDARY | _CIF_FPU)
57_PIF_WORK	= (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
58
59#define BASED(name) name-cleanup_critical(%r13)
60
61	.macro	TRACE_IRQS_ON
62#ifdef CONFIG_TRACE_IRQFLAGS
63	basr	%r2,%r0
64	brasl	%r14,trace_hardirqs_on_caller
65#endif
66	.endm
67
68	.macro	TRACE_IRQS_OFF
69#ifdef CONFIG_TRACE_IRQFLAGS
70	basr	%r2,%r0
71	brasl	%r14,trace_hardirqs_off_caller
72#endif
73	.endm
74
75	.macro	LOCKDEP_SYS_EXIT
76#ifdef CONFIG_LOCKDEP
77	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
78	jz	.+10
79	brasl	%r14,lockdep_sys_exit
80#endif
81	.endm
82
83	.macro	CHECK_STACK stacksize,savearea
84#ifdef CONFIG_CHECK_STACK
85	tml	%r15,\stacksize - CONFIG_STACK_GUARD
86	lghi	%r14,\savearea
87	jz	stack_overflow
88#endif
89	.endm
90
91	.macro	SWITCH_ASYNC savearea,timer
92	tmhh	%r8,0x0001		# interrupting from user ?
93	jnz	1f
94	lgr	%r14,%r9
95	slg	%r14,BASED(.Lcritical_start)
96	clg	%r14,BASED(.Lcritical_length)
97	jhe	0f
98	lghi	%r11,\savearea		# inside critical section, do cleanup
99	brasl	%r14,cleanup_critical
100	tmhh	%r8,0x0001		# retest problem state after cleanup
101	jnz	1f
1020:	lg	%r14,__LC_ASYNC_STACK	# are we already on the async stack?
103	slgr	%r14,%r15
104	srag	%r14,%r14,STACK_SHIFT
105	jnz	2f
106	CHECK_STACK 1<<STACK_SHIFT,\savearea
107	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
108	j	3f
1091:	UPDATE_VTIME %r14,%r15,\timer
1102:	lg	%r15,__LC_ASYNC_STACK	# load async stack
1113:	la	%r11,STACK_FRAME_OVERHEAD(%r15)
112	.endm
113
114	.macro UPDATE_VTIME w1,w2,enter_timer
115	lg	\w1,__LC_EXIT_TIMER
116	lg	\w2,__LC_LAST_UPDATE_TIMER
117	slg	\w1,\enter_timer
118	slg	\w2,__LC_EXIT_TIMER
119	alg	\w1,__LC_USER_TIMER
120	alg	\w2,__LC_SYSTEM_TIMER
121	stg	\w1,__LC_USER_TIMER
122	stg	\w2,__LC_SYSTEM_TIMER
123	mvc	__LC_LAST_UPDATE_TIMER(8),\enter_timer
124	.endm
125
126	.macro REENABLE_IRQS
127	stg	%r8,__LC_RETURN_PSW
128	ni	__LC_RETURN_PSW,0xbf
129	ssm	__LC_RETURN_PSW
130	.endm
131
132	.macro STCK savearea
133#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
134	.insn	s,0xb27c0000,\savearea		# store clock fast
135#else
136	.insn	s,0xb2050000,\savearea		# store clock
137#endif
138	.endm
139
140	/*
141	 * The TSTMSK macro generates a test-under-mask instruction by
142	 * calculating the memory offset for the specified mask value.
143	 * Mask value can be any constant.  The macro shifts the mask
144	 * value to calculate the memory offset for the test-under-mask
145	 * instruction.
146	 */
147	.macro TSTMSK addr, mask, size=8, bytepos=0
148		.if (\bytepos < \size) && (\mask >> 8)
149			.if (\mask & 0xff)
150				.error "Mask exceeds byte boundary"
151			.endif
152			TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
153			.exitm
154		.endif
155		.ifeq \mask
156			.error "Mask must not be zero"
157		.endif
158		off = \size - \bytepos - 1
159		tm	off+\addr, \mask
160	.endm
161
162	.section .kprobes.text, "ax"
163.Ldummy:
164	/*
165	 * This nop exists only in order to avoid that __switch_to starts at
166	 * the beginning of the kprobes text section. In that case we would
167	 * have several symbols at the same address. E.g. objdump would take
168	 * an arbitrary symbol name when disassembling this code.
169	 * With the added nop in between the __switch_to symbol is unique
170	 * again.
171	 */
172	nop	0
173
174/*
175 * Scheduler resume function, called by switch_to
176 *  gpr2 = (task_struct *) prev
177 *  gpr3 = (task_struct *) next
178 * Returns:
179 *  gpr2 = prev
180 */
181ENTRY(__switch_to)
182	stmg	%r6,%r15,__SF_GPRS(%r15)	# store gprs of prev task
183	lghi	%r4,__TASK_stack
184	lghi	%r1,__TASK_thread
185	lg	%r5,0(%r4,%r3)			# start of kernel stack of next
186	stg	%r15,__THREAD_ksp(%r1,%r2)	# store kernel stack of prev
187	lgr	%r15,%r5
188	aghi	%r15,STACK_INIT			# end of kernel stack of next
189	stg	%r3,__LC_CURRENT		# store task struct of next
190	stg	%r15,__LC_KERNEL_STACK		# store end of kernel stack
191	lg	%r15,__THREAD_ksp(%r1,%r3)	# load kernel stack of next
192	aghi	%r3,__TASK_pid
193	mvc	__LC_CURRENT_PID(4,%r0),0(%r3)	# store pid of next
194	lmg	%r6,%r15,__SF_GPRS(%r15)	# load gprs of next task
195	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
196	bzr	%r14
197	.insn	s,0xb2800000,__LC_LPP		# set program parameter
198	br	%r14
199
200.L__critical_start:
201
202#if IS_ENABLED(CONFIG_KVM)
203/*
204 * sie64a calling convention:
205 * %r2 pointer to sie control block
206 * %r3 guest register save area
207 */
208ENTRY(sie64a)
209	stmg	%r6,%r14,__SF_GPRS(%r15)	# save kernel registers
210	stg	%r2,__SF_EMPTY(%r15)		# save control block pointer
211	stg	%r3,__SF_EMPTY+8(%r15)		# save guest register save area
212	xc	__SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # reason code = 0
213	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU		# load guest fp/vx registers ?
214	jno	.Lsie_load_guest_gprs
215	brasl	%r14,load_fpu_regs		# load guest fp/vx regs
216.Lsie_load_guest_gprs:
217	lmg	%r0,%r13,0(%r3)			# load guest gprs 0-13
218	lg	%r14,__LC_GMAP			# get gmap pointer
219	ltgr	%r14,%r14
220	jz	.Lsie_gmap
221	lctlg	%c1,%c1,__GMAP_ASCE(%r14)	# load primary asce
222.Lsie_gmap:
223	lg	%r14,__SF_EMPTY(%r15)		# get control block pointer
224	oi	__SIE_PROG0C+3(%r14),1		# we are going into SIE now
225	tm	__SIE_PROG20+3(%r14),3		# last exit...
226	jnz	.Lsie_skip
227	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
228	jo	.Lsie_skip			# exit if fp/vx regs changed
229.Lsie_entry:
230	sie	0(%r14)
231.Lsie_skip:
232	ni	__SIE_PROG0C+3(%r14),0xfe	# no longer in SIE
233	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
234.Lsie_done:
235# some program checks are suppressing. C code (e.g. do_protection_exception)
236# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
237# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
238# Other instructions between sie64a and .Lsie_done should not cause program
239# interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
240# See also .Lcleanup_sie
241.Lrewind_pad6:
242	nopr	7
243.Lrewind_pad4:
244	nopr	7
245.Lrewind_pad2:
246	nopr	7
247	.globl sie_exit
248sie_exit:
249	lg	%r14,__SF_EMPTY+8(%r15)		# load guest register save area
250	stmg	%r0,%r13,0(%r14)		# save guest gprs 0-13
251	xgr	%r0,%r0				# clear guest registers to
252	xgr	%r1,%r1				# prevent speculative use
253	xgr	%r2,%r2
254	xgr	%r3,%r3
255	xgr	%r4,%r4
256	xgr	%r5,%r5
257	lmg	%r6,%r14,__SF_GPRS(%r15)	# restore kernel registers
258	lg	%r2,__SF_EMPTY+16(%r15)		# return exit reason code
259	br	%r14
260.Lsie_fault:
261	lghi	%r14,-EFAULT
262	stg	%r14,__SF_EMPTY+16(%r15)	# set exit reason code
263	j	sie_exit
264
265	EX_TABLE(.Lrewind_pad6,.Lsie_fault)
266	EX_TABLE(.Lrewind_pad4,.Lsie_fault)
267	EX_TABLE(.Lrewind_pad2,.Lsie_fault)
268	EX_TABLE(sie_exit,.Lsie_fault)
269EXPORT_SYMBOL(sie64a)
270EXPORT_SYMBOL(sie_exit)
271#endif
272
273/*
274 * SVC interrupt handler routine. System calls are synchronous events and
275 * are executed with interrupts enabled.
276 */
277
278ENTRY(system_call)
279	stpt	__LC_SYNC_ENTER_TIMER
280.Lsysc_stmg:
281	stmg	%r8,%r15,__LC_SAVE_AREA_SYNC
282	lg	%r12,__LC_CURRENT
283	lghi	%r13,__TASK_thread
284	lghi	%r14,_PIF_SYSCALL
285.Lsysc_per:
286	lg	%r15,__LC_KERNEL_STACK
287	la	%r11,STACK_FRAME_OVERHEAD(%r15)	# pointer to pt_regs
288.Lsysc_vtime:
289	UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
290	stmg	%r0,%r7,__PT_R0(%r11)
291	# clear user controlled register to prevent speculative use
292	xgr	%r0,%r0
293	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
294	mvc	__PT_PSW(16,%r11),__LC_SVC_OLD_PSW
295	mvc	__PT_INT_CODE(4,%r11),__LC_SVC_ILC
296	stg	%r14,__PT_FLAGS(%r11)
297.Lsysc_do_svc:
298	# load address of system call table
299	lg	%r10,__THREAD_sysc_table(%r13,%r12)
300	llgh	%r8,__PT_INT_CODE+2(%r11)
301	slag	%r8,%r8,2			# shift and test for svc 0
302	jnz	.Lsysc_nr_ok
303	# svc 0: system call number in %r1
304	llgfr	%r1,%r1				# clear high word in r1
305	cghi	%r1,NR_syscalls
306	jnl	.Lsysc_nr_ok
307	sth	%r1,__PT_INT_CODE+2(%r11)
308	slag	%r8,%r1,2
309.Lsysc_nr_ok:
310	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
311	stg	%r2,__PT_ORIG_GPR2(%r11)
312	stg	%r7,STACK_FRAME_OVERHEAD(%r15)
313	lgf	%r9,0(%r8,%r10)			# get system call add.
314	TSTMSK	__TI_flags(%r12),_TIF_TRACE
315	jnz	.Lsysc_tracesys
316	basr	%r14,%r9			# call sys_xxxx
317	stg	%r2,__PT_R2(%r11)		# store return value
318
319.Lsysc_return:
320	LOCKDEP_SYS_EXIT
321.Lsysc_tif:
322	TSTMSK	__PT_FLAGS(%r11),_PIF_WORK
323	jnz	.Lsysc_work
324	TSTMSK	__TI_flags(%r12),_TIF_WORK
325	jnz	.Lsysc_work			# check for work
326	TSTMSK	__LC_CPU_FLAGS,_CIF_WORK
327	jnz	.Lsysc_work
328.Lsysc_restore:
329	lg	%r14,__LC_VDSO_PER_CPU
330	lmg	%r0,%r10,__PT_R0(%r11)
331	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r11)
332.Lsysc_exit_timer:
333	stpt	__LC_EXIT_TIMER
334	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
335	lmg	%r11,%r15,__PT_R11(%r11)
336	lpswe	__LC_RETURN_PSW
337.Lsysc_done:
338
339#
340# One of the work bits is on. Find out which one.
341#
342.Lsysc_work:
343	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
344	jo	.Lsysc_mcck_pending
345	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
346	jo	.Lsysc_reschedule
347	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
348	jo	.Lsysc_syscall_restart
349#ifdef CONFIG_UPROBES
350	TSTMSK	__TI_flags(%r12),_TIF_UPROBE
351	jo	.Lsysc_uprobe_notify
352#endif
353	TSTMSK	__TI_flags(%r12),_TIF_GUARDED_STORAGE
354	jo	.Lsysc_guarded_storage
355	TSTMSK	__PT_FLAGS(%r11),_PIF_PER_TRAP
356	jo	.Lsysc_singlestep
357#ifdef CONFIG_LIVEPATCH
358	TSTMSK	__TI_flags(%r12),_TIF_PATCH_PENDING
359	jo	.Lsysc_patch_pending	# handle live patching just before
360					# signals and possible syscall restart
361#endif
362	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
363	jo	.Lsysc_syscall_restart
364	TSTMSK	__TI_flags(%r12),_TIF_SIGPENDING
365	jo	.Lsysc_sigpending
366	TSTMSK	__TI_flags(%r12),_TIF_NOTIFY_RESUME
367	jo	.Lsysc_notify_resume
368	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
369	jo	.Lsysc_vxrs
370	TSTMSK	__LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
371	jnz	.Lsysc_asce
372	j	.Lsysc_return		# beware of critical section cleanup
373
374#
375# _TIF_NEED_RESCHED is set, call schedule
376#
377.Lsysc_reschedule:
378	larl	%r14,.Lsysc_return
379	jg	schedule
380
381#
382# _CIF_MCCK_PENDING is set, call handler
383#
384.Lsysc_mcck_pending:
385	larl	%r14,.Lsysc_return
386	jg	s390_handle_mcck	# TIF bit will be cleared by handler
387
388#
389# _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce
390#
391.Lsysc_asce:
392	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
393	lctlg	%c7,%c7,__LC_VDSO_ASCE		# load secondary asce
394	TSTMSK	__LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
395	jz	.Lsysc_return
396#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
397	tm	__LC_STFLE_FAC_LIST+3,0x10	# has MVCOS ?
398	jnz	.Lsysc_set_fs_fixup
399	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
400	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
401	j	.Lsysc_return
402.Lsysc_set_fs_fixup:
403#endif
404	larl	%r14,.Lsysc_return
405	jg	set_fs_fixup
406
407#
408# CIF_FPU is set, restore floating-point controls and floating-point registers.
409#
410.Lsysc_vxrs:
411	larl	%r14,.Lsysc_return
412	jg	load_fpu_regs
413
414#
415# _TIF_SIGPENDING is set, call do_signal
416#
417.Lsysc_sigpending:
418	lgr	%r2,%r11		# pass pointer to pt_regs
419	brasl	%r14,do_signal
420	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL
421	jno	.Lsysc_return
422.Lsysc_do_syscall:
423	lghi	%r13,__TASK_thread
424	lmg	%r2,%r7,__PT_R2(%r11)	# load svc arguments
425	lghi	%r1,0			# svc 0 returns -ENOSYS
426	j	.Lsysc_do_svc
427
428#
429# _TIF_NOTIFY_RESUME is set, call do_notify_resume
430#
431.Lsysc_notify_resume:
432	lgr	%r2,%r11		# pass pointer to pt_regs
433	larl	%r14,.Lsysc_return
434	jg	do_notify_resume
435
436#
437# _TIF_UPROBE is set, call uprobe_notify_resume
438#
439#ifdef CONFIG_UPROBES
440.Lsysc_uprobe_notify:
441	lgr	%r2,%r11		# pass pointer to pt_regs
442	larl	%r14,.Lsysc_return
443	jg	uprobe_notify_resume
444#endif
445
446#
447# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
448#
449.Lsysc_guarded_storage:
450	lgr	%r2,%r11		# pass pointer to pt_regs
451	larl	%r14,.Lsysc_return
452	jg	gs_load_bc_cb
453#
454# _TIF_PATCH_PENDING is set, call klp_update_patch_state
455#
456#ifdef CONFIG_LIVEPATCH
457.Lsysc_patch_pending:
458	lg	%r2,__LC_CURRENT	# pass pointer to task struct
459	larl	%r14,.Lsysc_return
460	jg	klp_update_patch_state
461#endif
462
463#
464# _PIF_PER_TRAP is set, call do_per_trap
465#
466.Lsysc_singlestep:
467	ni	__PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
468	lgr	%r2,%r11		# pass pointer to pt_regs
469	larl	%r14,.Lsysc_return
470	jg	do_per_trap
471
472#
473# _PIF_SYSCALL_RESTART is set, repeat the current system call
474#
475.Lsysc_syscall_restart:
476	ni	__PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
477	lmg	%r1,%r7,__PT_R1(%r11)	# load svc arguments
478	lg	%r2,__PT_ORIG_GPR2(%r11)
479	j	.Lsysc_do_svc
480
481#
482# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
483# and after the system call
484#
485.Lsysc_tracesys:
486	lgr	%r2,%r11		# pass pointer to pt_regs
487	la	%r3,0
488	llgh	%r0,__PT_INT_CODE+2(%r11)
489	stg	%r0,__PT_R2(%r11)
490	brasl	%r14,do_syscall_trace_enter
491	lghi	%r0,NR_syscalls
492	clgr	%r0,%r2
493	jnh	.Lsysc_tracenogo
494	sllg	%r8,%r2,2
495	lgf	%r9,0(%r8,%r10)
496.Lsysc_tracego:
497	lmg	%r3,%r7,__PT_R3(%r11)
498	stg	%r7,STACK_FRAME_OVERHEAD(%r15)
499	lg	%r2,__PT_ORIG_GPR2(%r11)
500	basr	%r14,%r9		# call sys_xxx
501	stg	%r2,__PT_R2(%r11)	# store return value
502.Lsysc_tracenogo:
503	TSTMSK	__TI_flags(%r12),_TIF_TRACE
504	jz	.Lsysc_return
505	lgr	%r2,%r11		# pass pointer to pt_regs
506	larl	%r14,.Lsysc_return
507	jg	do_syscall_trace_exit
508
509#
510# a new process exits the kernel with ret_from_fork
511#
512ENTRY(ret_from_fork)
513	la	%r11,STACK_FRAME_OVERHEAD(%r15)
514	lg	%r12,__LC_CURRENT
515	brasl	%r14,schedule_tail
516	TRACE_IRQS_ON
517	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
518	tm	__PT_PSW+1(%r11),0x01	# forking a kernel thread ?
519	jne	.Lsysc_tracenogo
520	# it's a kernel thread
521	lmg	%r9,%r10,__PT_R9(%r11)	# load gprs
522ENTRY(kernel_thread_starter)
523	la	%r2,0(%r10)
524	basr	%r14,%r9
525	j	.Lsysc_tracenogo
526
527/*
528 * Program check handler routine
529 */
530
531ENTRY(pgm_check_handler)
532	stpt	__LC_SYNC_ENTER_TIMER
533	stmg	%r8,%r15,__LC_SAVE_AREA_SYNC
534	lg	%r10,__LC_LAST_BREAK
535	lg	%r12,__LC_CURRENT
536	lghi	%r11,0
537	larl	%r13,cleanup_critical
538	lmg	%r8,%r9,__LC_PGM_OLD_PSW
539	tmhh	%r8,0x0001		# test problem state bit
540	jnz	2f			# -> fault in user space
541#if IS_ENABLED(CONFIG_KVM)
542	# cleanup critical section for program checks in sie64a
543	lgr	%r14,%r9
544	slg	%r14,BASED(.Lsie_critical_start)
545	clg	%r14,BASED(.Lsie_critical_length)
546	jhe	0f
547	lg	%r14,__SF_EMPTY(%r15)		# get control block pointer
548	ni	__SIE_PROG0C+3(%r14),0xfe	# no longer in SIE
549	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
550	larl	%r9,sie_exit			# skip forward to sie_exit
551	lghi	%r11,_PIF_GUEST_FAULT
552#endif
5530:	tmhh	%r8,0x4000		# PER bit set in old PSW ?
554	jnz	1f			# -> enabled, can't be a double fault
555	tm	__LC_PGM_ILC+3,0x80	# check for per exception
556	jnz	.Lpgm_svcper		# -> single stepped svc
5571:	CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
558	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
559	j	4f
5602:	UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
561	lg	%r15,__LC_KERNEL_STACK
562	lgr	%r14,%r12
563	aghi	%r14,__TASK_thread	# pointer to thread_struct
564	lghi	%r13,__LC_PGM_TDB
565	tm	__LC_PGM_ILC+2,0x02	# check for transaction abort
566	jz	3f
567	mvc	__THREAD_trap_tdb(256,%r14),0(%r13)
5683:	stg	%r10,__THREAD_last_break(%r14)
5694:	lgr	%r13,%r11
570	la	%r11,STACK_FRAME_OVERHEAD(%r15)
571	stmg	%r0,%r7,__PT_R0(%r11)
572	# clear user controlled registers to prevent speculative use
573	xgr	%r0,%r0
574	xgr	%r1,%r1
575	xgr	%r2,%r2
576	xgr	%r3,%r3
577	xgr	%r4,%r4
578	xgr	%r5,%r5
579	xgr	%r6,%r6
580	xgr	%r7,%r7
581	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
582	stmg	%r8,%r9,__PT_PSW(%r11)
583	mvc	__PT_INT_CODE(4,%r11),__LC_PGM_ILC
584	mvc	__PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
585	stg	%r13,__PT_FLAGS(%r11)
586	stg	%r10,__PT_ARGS(%r11)
587	tm	__LC_PGM_ILC+3,0x80	# check for per exception
588	jz	5f
589	tmhh	%r8,0x0001		# kernel per event ?
590	jz	.Lpgm_kprobe
591	oi	__PT_FLAGS+7(%r11),_PIF_PER_TRAP
592	mvc	__THREAD_per_address(8,%r14),__LC_PER_ADDRESS
593	mvc	__THREAD_per_cause(2,%r14),__LC_PER_CODE
594	mvc	__THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
5955:	REENABLE_IRQS
596	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
597	larl	%r1,pgm_check_table
598	llgh	%r10,__PT_INT_CODE+2(%r11)
599	nill	%r10,0x007f
600	sll	%r10,2
601	je	.Lpgm_return
602	lgf	%r1,0(%r10,%r1)		# load address of handler routine
603	lgr	%r2,%r11		# pass pointer to pt_regs
604	basr	%r14,%r1		# branch to interrupt-handler
605.Lpgm_return:
606	LOCKDEP_SYS_EXIT
607	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
608	jno	.Lsysc_restore
609	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL
610	jo	.Lsysc_do_syscall
611	j	.Lsysc_tif
612
613#
614# PER event in supervisor state, must be kprobes
615#
616.Lpgm_kprobe:
617	REENABLE_IRQS
618	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
619	lgr	%r2,%r11		# pass pointer to pt_regs
620	brasl	%r14,do_per_trap
621	j	.Lpgm_return
622
623#
624# single stepped system call
625#
626.Lpgm_svcper:
627	mvc	__LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
628	lghi	%r13,__TASK_thread
629	larl	%r14,.Lsysc_per
630	stg	%r14,__LC_RETURN_PSW+8
631	lghi	%r14,_PIF_SYSCALL | _PIF_PER_TRAP
632	lpswe	__LC_RETURN_PSW		# branch to .Lsysc_per and enable irqs
633
634/*
635 * IO interrupt handler routine
636 */
637ENTRY(io_int_handler)
638	STCK	__LC_INT_CLOCK
639	stpt	__LC_ASYNC_ENTER_TIMER
640	stmg	%r8,%r15,__LC_SAVE_AREA_ASYNC
641	lg	%r12,__LC_CURRENT
642	larl	%r13,cleanup_critical
643	lmg	%r8,%r9,__LC_IO_OLD_PSW
644	SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
645	stmg	%r0,%r7,__PT_R0(%r11)
646	# clear user controlled registers to prevent speculative use
647	xgr	%r0,%r0
648	xgr	%r1,%r1
649	xgr	%r2,%r2
650	xgr	%r3,%r3
651	xgr	%r4,%r4
652	xgr	%r5,%r5
653	xgr	%r6,%r6
654	xgr	%r7,%r7
655	xgr	%r10,%r10
656	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
657	stmg	%r8,%r9,__PT_PSW(%r11)
658	mvc	__PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
659	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
660	TSTMSK	__LC_CPU_FLAGS,_CIF_IGNORE_IRQ
661	jo	.Lio_restore
662	TRACE_IRQS_OFF
663	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
664.Lio_loop:
665	lgr	%r2,%r11		# pass pointer to pt_regs
666	lghi	%r3,IO_INTERRUPT
667	tm	__PT_INT_CODE+8(%r11),0x80	# adapter interrupt ?
668	jz	.Lio_call
669	lghi	%r3,THIN_INTERRUPT
670.Lio_call:
671	brasl	%r14,do_IRQ
672	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
673	jz	.Lio_return
674	tpi	0
675	jz	.Lio_return
676	mvc	__PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
677	j	.Lio_loop
678.Lio_return:
679	LOCKDEP_SYS_EXIT
680	TRACE_IRQS_ON
681.Lio_tif:
682	TSTMSK	__TI_flags(%r12),_TIF_WORK
683	jnz	.Lio_work		# there is work to do (signals etc.)
684	TSTMSK	__LC_CPU_FLAGS,_CIF_WORK
685	jnz	.Lio_work
686.Lio_restore:
687	lg	%r14,__LC_VDSO_PER_CPU
688	lmg	%r0,%r10,__PT_R0(%r11)
689	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r11)
690.Lio_exit_timer:
691	stpt	__LC_EXIT_TIMER
692	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
693	lmg	%r11,%r15,__PT_R11(%r11)
694	lpswe	__LC_RETURN_PSW
695.Lio_done:
696
697#
698# There is work todo, find out in which context we have been interrupted:
699# 1) if we return to user space we can do all _TIF_WORK work
700# 2) if we return to kernel code and kvm is enabled check if we need to
701#    modify the psw to leave SIE
702# 3) if we return to kernel code and preemptive scheduling is enabled check
703#    the preemption counter and if it is zero call preempt_schedule_irq
704# Before any work can be done, a switch to the kernel stack is required.
705#
706.Lio_work:
707	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
708	jo	.Lio_work_user		# yes -> do resched & signal
709#ifdef CONFIG_PREEMPT
710	# check for preemptive scheduling
711	icm	%r0,15,__LC_PREEMPT_COUNT
712	jnz	.Lio_restore		# preemption is disabled
713	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
714	jno	.Lio_restore
715	# switch to kernel stack
716	lg	%r1,__PT_R15(%r11)
717	aghi	%r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
718	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
719	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
720	la	%r11,STACK_FRAME_OVERHEAD(%r1)
721	lgr	%r15,%r1
722	# TRACE_IRQS_ON already done at .Lio_return, call
723	# TRACE_IRQS_OFF to keep things symmetrical
724	TRACE_IRQS_OFF
725	brasl	%r14,preempt_schedule_irq
726	j	.Lio_return
727#else
728	j	.Lio_restore
729#endif
730
731#
732# Need to do work before returning to userspace, switch to kernel stack
733#
734.Lio_work_user:
735	lg	%r1,__LC_KERNEL_STACK
736	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
737	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
738	la	%r11,STACK_FRAME_OVERHEAD(%r1)
739	lgr	%r15,%r1
740
741#
742# One of the work bits is on. Find out which one.
743#
744.Lio_work_tif:
745	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
746	jo	.Lio_mcck_pending
747	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
748	jo	.Lio_reschedule
749#ifdef CONFIG_LIVEPATCH
750	TSTMSK	__TI_flags(%r12),_TIF_PATCH_PENDING
751	jo	.Lio_patch_pending
752#endif
753	TSTMSK	__TI_flags(%r12),_TIF_SIGPENDING
754	jo	.Lio_sigpending
755	TSTMSK	__TI_flags(%r12),_TIF_NOTIFY_RESUME
756	jo	.Lio_notify_resume
757	TSTMSK	__TI_flags(%r12),_TIF_GUARDED_STORAGE
758	jo	.Lio_guarded_storage
759	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
760	jo	.Lio_vxrs
761	TSTMSK	__LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
762	jnz	.Lio_asce
763	j	.Lio_return		# beware of critical section cleanup
764
765#
766# _CIF_MCCK_PENDING is set, call handler
767#
768.Lio_mcck_pending:
769	# TRACE_IRQS_ON already done at .Lio_return
770	brasl	%r14,s390_handle_mcck	# TIF bit will be cleared by handler
771	TRACE_IRQS_OFF
772	j	.Lio_return
773
774#
775# _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
776#
777.Lio_asce:
778	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
779	lctlg	%c7,%c7,__LC_VDSO_ASCE		# load secondary asce
780	TSTMSK	__LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
781	jz	.Lio_return
782#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
783	tm	__LC_STFLE_FAC_LIST+3,0x10	# has MVCOS ?
784	jnz	.Lio_set_fs_fixup
785	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
786	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
787	j	.Lio_return
788.Lio_set_fs_fixup:
789#endif
790	larl	%r14,.Lio_return
791	jg	set_fs_fixup
792
793#
794# CIF_FPU is set, restore floating-point controls and floating-point registers.
795#
796.Lio_vxrs:
797	larl	%r14,.Lio_return
798	jg	load_fpu_regs
799
800#
801# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
802#
803.Lio_guarded_storage:
804	# TRACE_IRQS_ON already done at .Lio_return
805	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
806	lgr	%r2,%r11		# pass pointer to pt_regs
807	brasl	%r14,gs_load_bc_cb
808	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
809	TRACE_IRQS_OFF
810	j	.Lio_return
811
812#
813# _TIF_NEED_RESCHED is set, call schedule
814#
815.Lio_reschedule:
816	# TRACE_IRQS_ON already done at .Lio_return
817	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
818	brasl	%r14,schedule		# call scheduler
819	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
820	TRACE_IRQS_OFF
821	j	.Lio_return
822
823#
824# _TIF_PATCH_PENDING is set, call klp_update_patch_state
825#
826#ifdef CONFIG_LIVEPATCH
827.Lio_patch_pending:
828	lg	%r2,__LC_CURRENT	# pass pointer to task struct
829	larl	%r14,.Lio_return
830	jg	klp_update_patch_state
831#endif
832
833#
834# _TIF_SIGPENDING or is set, call do_signal
835#
836.Lio_sigpending:
837	# TRACE_IRQS_ON already done at .Lio_return
838	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
839	lgr	%r2,%r11		# pass pointer to pt_regs
840	brasl	%r14,do_signal
841	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
842	TRACE_IRQS_OFF
843	j	.Lio_return
844
845#
846# _TIF_NOTIFY_RESUME or is set, call do_notify_resume
847#
848.Lio_notify_resume:
849	# TRACE_IRQS_ON already done at .Lio_return
850	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
851	lgr	%r2,%r11		# pass pointer to pt_regs
852	brasl	%r14,do_notify_resume
853	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
854	TRACE_IRQS_OFF
855	j	.Lio_return
856
857/*
858 * External interrupt handler routine
859 */
860ENTRY(ext_int_handler)
861	STCK	__LC_INT_CLOCK
862	stpt	__LC_ASYNC_ENTER_TIMER
863	stmg	%r8,%r15,__LC_SAVE_AREA_ASYNC
864	lg	%r12,__LC_CURRENT
865	larl	%r13,cleanup_critical
866	lmg	%r8,%r9,__LC_EXT_OLD_PSW
867	SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
868	stmg	%r0,%r7,__PT_R0(%r11)
869	# clear user controlled registers to prevent speculative use
870	xgr	%r0,%r0
871	xgr	%r1,%r1
872	xgr	%r2,%r2
873	xgr	%r3,%r3
874	xgr	%r4,%r4
875	xgr	%r5,%r5
876	xgr	%r6,%r6
877	xgr	%r7,%r7
878	xgr	%r10,%r10
879	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
880	stmg	%r8,%r9,__PT_PSW(%r11)
881	lghi	%r1,__LC_EXT_PARAMS2
882	mvc	__PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
883	mvc	__PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
884	mvc	__PT_INT_PARM_LONG(8,%r11),0(%r1)
885	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
886	TSTMSK	__LC_CPU_FLAGS,_CIF_IGNORE_IRQ
887	jo	.Lio_restore
888	TRACE_IRQS_OFF
889	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
890	lgr	%r2,%r11		# pass pointer to pt_regs
891	lghi	%r3,EXT_INTERRUPT
892	brasl	%r14,do_IRQ
893	j	.Lio_return
894
895/*
896 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
897 */
898ENTRY(psw_idle)
899	stg	%r3,__SF_EMPTY(%r15)
900	larl	%r1,.Lpsw_idle_lpsw+4
901	stg	%r1,__SF_EMPTY+8(%r15)
902#ifdef CONFIG_SMP
903	larl	%r1,smp_cpu_mtid
904	llgf	%r1,0(%r1)
905	ltgr	%r1,%r1
906	jz	.Lpsw_idle_stcctm
907	.insn	rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
908.Lpsw_idle_stcctm:
909#endif
910	oi	__LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
911	STCK	__CLOCK_IDLE_ENTER(%r2)
912	stpt	__TIMER_IDLE_ENTER(%r2)
913.Lpsw_idle_lpsw:
914	lpswe	__SF_EMPTY(%r15)
915	br	%r14
916.Lpsw_idle_end:
917
918/*
919 * Store floating-point controls and floating-point or vector register
920 * depending whether the vector facility is available.	A critical section
921 * cleanup assures that the registers are stored even if interrupted for
922 * some other work.  The CIF_FPU flag is set to trigger a lazy restore
923 * of the register contents at return from io or a system call.
924 */
925ENTRY(save_fpu_regs)
926	lg	%r2,__LC_CURRENT
927	aghi	%r2,__TASK_thread
928	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
929	bor	%r14
930	stfpc	__THREAD_FPU_fpc(%r2)
931	lg	%r3,__THREAD_FPU_regs(%r2)
932	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
933	jz	.Lsave_fpu_regs_fp	  # no -> store FP regs
934	VSTM	%v0,%v15,0,%r3		  # vstm 0,15,0(3)
935	VSTM	%v16,%v31,256,%r3	  # vstm 16,31,256(3)
936	j	.Lsave_fpu_regs_done	  # -> set CIF_FPU flag
937.Lsave_fpu_regs_fp:
938	std	0,0(%r3)
939	std	1,8(%r3)
940	std	2,16(%r3)
941	std	3,24(%r3)
942	std	4,32(%r3)
943	std	5,40(%r3)
944	std	6,48(%r3)
945	std	7,56(%r3)
946	std	8,64(%r3)
947	std	9,72(%r3)
948	std	10,80(%r3)
949	std	11,88(%r3)
950	std	12,96(%r3)
951	std	13,104(%r3)
952	std	14,112(%r3)
953	std	15,120(%r3)
954.Lsave_fpu_regs_done:
955	oi	__LC_CPU_FLAGS+7,_CIF_FPU
956	br	%r14
957.Lsave_fpu_regs_end:
958EXPORT_SYMBOL(save_fpu_regs)
959
960/*
961 * Load floating-point controls and floating-point or vector registers.
962 * A critical section cleanup assures that the register contents are
963 * loaded even if interrupted for some other work.
964 *
965 * There are special calling conventions to fit into sysc and io return work:
966 *	%r15:	<kernel stack>
967 * The function requires:
968 *	%r4
969 */
970load_fpu_regs:
971	lg	%r4,__LC_CURRENT
972	aghi	%r4,__TASK_thread
973	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
974	bnor	%r14
975	lfpc	__THREAD_FPU_fpc(%r4)
976	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
977	lg	%r4,__THREAD_FPU_regs(%r4)	# %r4 <- reg save area
978	jz	.Lload_fpu_regs_fp		# -> no VX, load FP regs
979	VLM	%v0,%v15,0,%r4
980	VLM	%v16,%v31,256,%r4
981	j	.Lload_fpu_regs_done
982.Lload_fpu_regs_fp:
983	ld	0,0(%r4)
984	ld	1,8(%r4)
985	ld	2,16(%r4)
986	ld	3,24(%r4)
987	ld	4,32(%r4)
988	ld	5,40(%r4)
989	ld	6,48(%r4)
990	ld	7,56(%r4)
991	ld	8,64(%r4)
992	ld	9,72(%r4)
993	ld	10,80(%r4)
994	ld	11,88(%r4)
995	ld	12,96(%r4)
996	ld	13,104(%r4)
997	ld	14,112(%r4)
998	ld	15,120(%r4)
999.Lload_fpu_regs_done:
1000	ni	__LC_CPU_FLAGS+7,255-_CIF_FPU
1001	br	%r14
1002.Lload_fpu_regs_end:
1003
1004.L__critical_end:
1005
1006/*
1007 * Machine check handler routines
1008 */
1009ENTRY(mcck_int_handler)
1010	STCK	__LC_MCCK_CLOCK
1011	la	%r1,4095		# validate r1
1012	spt	__LC_CPU_TIMER_SAVE_AREA-4095(%r1)	# validate cpu timer
1013	sckc	__LC_CLOCK_COMPARATOR			# validate comparator
1014	lam	%a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs
1015	lmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
1016	lg	%r12,__LC_CURRENT
1017	larl	%r13,cleanup_critical
1018	lmg	%r8,%r9,__LC_MCK_OLD_PSW
1019	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1020	jo	.Lmcck_panic		# yes -> rest of mcck code invalid
1021	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_CR_VALID
1022	jno	.Lmcck_panic		# control registers invalid -> panic
1023	la	%r14,4095
1024	lctlg	%c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
1025	ptlb
1026	lg	%r11,__LC_MCESAD-4095(%r14) # extended machine check save area
1027	nill	%r11,0xfc00		# MCESA_ORIGIN_MASK
1028	TSTMSK	__LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE
1029	jno	0f
1030	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_GS_VALID
1031	jno	0f
1032	.insn	 rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC
10330:	l	%r14,__LC_FP_CREG_SAVE_AREA-4095(%r14)
1034	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_FC_VALID
1035	jo	0f
1036	sr	%r14,%r14
10370:	sfpc	%r14
1038	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1039	jo	0f
1040	lghi	%r14,__LC_FPREGS_SAVE_AREA
1041	ld	%f0,0(%r14)
1042	ld	%f1,8(%r14)
1043	ld	%f2,16(%r14)
1044	ld	%f3,24(%r14)
1045	ld	%f4,32(%r14)
1046	ld	%f5,40(%r14)
1047	ld	%f6,48(%r14)
1048	ld	%f7,56(%r14)
1049	ld	%f8,64(%r14)
1050	ld	%f9,72(%r14)
1051	ld	%f10,80(%r14)
1052	ld	%f11,88(%r14)
1053	ld	%f12,96(%r14)
1054	ld	%f13,104(%r14)
1055	ld	%f14,112(%r14)
1056	ld	%f15,120(%r14)
1057	j	1f
10580:	VLM	%v0,%v15,0,%r11
1059	VLM	%v16,%v31,256,%r11
10601:	lghi	%r14,__LC_CPU_TIMER_SAVE_AREA
1061	mvc	__LC_MCCK_ENTER_TIMER(8),0(%r14)
1062	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1063	jo	3f
1064	la	%r14,__LC_SYNC_ENTER_TIMER
1065	clc	0(8,%r14),__LC_ASYNC_ENTER_TIMER
1066	jl	0f
1067	la	%r14,__LC_ASYNC_ENTER_TIMER
10680:	clc	0(8,%r14),__LC_EXIT_TIMER
1069	jl	1f
1070	la	%r14,__LC_EXIT_TIMER
10711:	clc	0(8,%r14),__LC_LAST_UPDATE_TIMER
1072	jl	2f
1073	la	%r14,__LC_LAST_UPDATE_TIMER
10742:	spt	0(%r14)
1075	mvc	__LC_MCCK_ENTER_TIMER(8),0(%r14)
10763:	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
1077	jno	.Lmcck_panic
1078	tmhh	%r8,0x0001		# interrupting from user ?
1079	jnz	4f
1080	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
1081	jno	.Lmcck_panic
10824:	SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1083.Lmcck_skip:
1084	lghi	%r14,__LC_GPREGS_SAVE_AREA+64
1085	stmg	%r0,%r7,__PT_R0(%r11)
1086	# clear user controlled registers to prevent speculative use
1087	xgr	%r0,%r0
1088	xgr	%r1,%r1
1089	xgr	%r2,%r2
1090	xgr	%r3,%r3
1091	xgr	%r4,%r4
1092	xgr	%r5,%r5
1093	xgr	%r6,%r6
1094	xgr	%r7,%r7
1095	xgr	%r10,%r10
1096	mvc	__PT_R8(64,%r11),0(%r14)
1097	stmg	%r8,%r9,__PT_PSW(%r11)
1098	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1099	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1100	lgr	%r2,%r11		# pass pointer to pt_regs
1101	brasl	%r14,s390_do_machine_check
1102	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
1103	jno	.Lmcck_return
1104	lg	%r1,__LC_KERNEL_STACK	# switch to kernel stack
1105	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1106	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1107	la	%r11,STACK_FRAME_OVERHEAD(%r1)
1108	lgr	%r15,%r1
1109	ssm	__LC_PGM_NEW_PSW	# turn dat on, keep irqs off
1110	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
1111	jno	.Lmcck_return
1112	TRACE_IRQS_OFF
1113	brasl	%r14,s390_handle_mcck
1114	TRACE_IRQS_ON
1115.Lmcck_return:
1116	lg	%r14,__LC_VDSO_PER_CPU
1117	lmg	%r0,%r10,__PT_R0(%r11)
1118	mvc	__LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1119	tm	__LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1120	jno	0f
1121	stpt	__LC_EXIT_TIMER
1122	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
11230:	lmg	%r11,%r15,__PT_R11(%r11)
1124	lpswe	__LC_RETURN_MCCK_PSW
1125
1126.Lmcck_panic:
1127	lg	%r15,__LC_PANIC_STACK
1128	la	%r11,STACK_FRAME_OVERHEAD(%r15)
1129	j	.Lmcck_skip
1130
1131#
1132# PSW restart interrupt handler
1133#
1134ENTRY(restart_int_handler)
1135	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
1136	jz	0f
1137	.insn	s,0xb2800000,__LC_LPP
11380:	stg	%r15,__LC_SAVE_AREA_RESTART
1139	lg	%r15,__LC_RESTART_STACK
1140	aghi	%r15,-__PT_SIZE			# create pt_regs on stack
1141	xc	0(__PT_SIZE,%r15),0(%r15)
1142	stmg	%r0,%r14,__PT_R0(%r15)
1143	mvc	__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1144	mvc	__PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
1145	aghi	%r15,-STACK_FRAME_OVERHEAD	# create stack frame on stack
1146	xc	0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1147	lg	%r1,__LC_RESTART_FN		# load fn, parm & source cpu
1148	lg	%r2,__LC_RESTART_DATA
1149	lg	%r3,__LC_RESTART_SOURCE
1150	ltgr	%r3,%r3				# test source cpu address
1151	jm	1f				# negative -> skip source stop
11520:	sigp	%r4,%r3,SIGP_SENSE		# sigp sense to source cpu
1153	brc	10,0b				# wait for status stored
11541:	basr	%r14,%r1			# call function
1155	stap	__SF_EMPTY(%r15)		# store cpu address
1156	llgh	%r3,__SF_EMPTY(%r15)
11572:	sigp	%r4,%r3,SIGP_STOP		# sigp stop to current cpu
1158	brc	2,2b
11593:	j	3b
1160
1161	.section .kprobes.text, "ax"
1162
1163#ifdef CONFIG_CHECK_STACK
1164/*
1165 * The synchronous or the asynchronous stack overflowed. We are dead.
1166 * No need to properly save the registers, we are going to panic anyway.
1167 * Setup a pt_regs so that show_trace can provide a good call trace.
1168 */
1169stack_overflow:
1170	lg	%r15,__LC_PANIC_STACK	# change to panic stack
1171	la	%r11,STACK_FRAME_OVERHEAD(%r15)
1172	stmg	%r0,%r7,__PT_R0(%r11)
1173	stmg	%r8,%r9,__PT_PSW(%r11)
1174	mvc	__PT_R8(64,%r11),0(%r14)
1175	stg	%r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1176	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1177	lgr	%r2,%r11		# pass pointer to pt_regs
1178	jg	kernel_stack_overflow
1179#endif
1180
1181cleanup_critical:
1182#if IS_ENABLED(CONFIG_KVM)
1183	clg	%r9,BASED(.Lcleanup_table_sie)	# .Lsie_gmap
1184	jl	0f
1185	clg	%r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1186	jl	.Lcleanup_sie
1187#endif
1188	clg	%r9,BASED(.Lcleanup_table)	# system_call
1189	jl	0f
1190	clg	%r9,BASED(.Lcleanup_table+8)	# .Lsysc_do_svc
1191	jl	.Lcleanup_system_call
1192	clg	%r9,BASED(.Lcleanup_table+16)	# .Lsysc_tif
1193	jl	0f
1194	clg	%r9,BASED(.Lcleanup_table+24)	# .Lsysc_restore
1195	jl	.Lcleanup_sysc_tif
1196	clg	%r9,BASED(.Lcleanup_table+32)	# .Lsysc_done
1197	jl	.Lcleanup_sysc_restore
1198	clg	%r9,BASED(.Lcleanup_table+40)	# .Lio_tif
1199	jl	0f
1200	clg	%r9,BASED(.Lcleanup_table+48)	# .Lio_restore
1201	jl	.Lcleanup_io_tif
1202	clg	%r9,BASED(.Lcleanup_table+56)	# .Lio_done
1203	jl	.Lcleanup_io_restore
1204	clg	%r9,BASED(.Lcleanup_table+64)	# psw_idle
1205	jl	0f
1206	clg	%r9,BASED(.Lcleanup_table+72)	# .Lpsw_idle_end
1207	jl	.Lcleanup_idle
1208	clg	%r9,BASED(.Lcleanup_table+80)	# save_fpu_regs
1209	jl	0f
1210	clg	%r9,BASED(.Lcleanup_table+88)	# .Lsave_fpu_regs_end
1211	jl	.Lcleanup_save_fpu_regs
1212	clg	%r9,BASED(.Lcleanup_table+96)	# load_fpu_regs
1213	jl	0f
1214	clg	%r9,BASED(.Lcleanup_table+104)	# .Lload_fpu_regs_end
1215	jl	.Lcleanup_load_fpu_regs
12160:	br	%r14
1217
1218	.align	8
1219.Lcleanup_table:
1220	.quad	system_call
1221	.quad	.Lsysc_do_svc
1222	.quad	.Lsysc_tif
1223	.quad	.Lsysc_restore
1224	.quad	.Lsysc_done
1225	.quad	.Lio_tif
1226	.quad	.Lio_restore
1227	.quad	.Lio_done
1228	.quad	psw_idle
1229	.quad	.Lpsw_idle_end
1230	.quad	save_fpu_regs
1231	.quad	.Lsave_fpu_regs_end
1232	.quad	load_fpu_regs
1233	.quad	.Lload_fpu_regs_end
1234
1235#if IS_ENABLED(CONFIG_KVM)
1236.Lcleanup_table_sie:
1237	.quad	.Lsie_gmap
1238	.quad	.Lsie_done
1239
1240.Lcleanup_sie:
1241	cghi    %r11,__LC_SAVE_AREA_ASYNC 	#Is this in normal interrupt?
1242	je      1f
1243	slg     %r9,BASED(.Lsie_crit_mcck_start)
1244	clg     %r9,BASED(.Lsie_crit_mcck_length)
1245	jh      1f
1246	oi      __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
12471:	lg	%r9,__SF_EMPTY(%r15)		# get control block pointer
1248	ni	__SIE_PROG0C+3(%r9),0xfe	# no longer in SIE
1249	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
1250	larl	%r9,sie_exit			# skip forward to sie_exit
1251	br	%r14
1252#endif
1253
1254.Lcleanup_system_call:
1255	# check if stpt has been executed
1256	clg	%r9,BASED(.Lcleanup_system_call_insn)
1257	jh	0f
1258	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1259	cghi	%r11,__LC_SAVE_AREA_ASYNC
1260	je	0f
1261	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
12620:	# check if stmg has been executed
1263	clg	%r9,BASED(.Lcleanup_system_call_insn+8)
1264	jh	0f
1265	mvc	__LC_SAVE_AREA_SYNC(64),0(%r11)
12660:	# check if base register setup + TIF bit load has been done
1267	clg	%r9,BASED(.Lcleanup_system_call_insn+16)
1268	jhe	0f
1269	# set up saved register r12 task struct pointer
1270	stg	%r12,32(%r11)
1271	# set up saved register r13 __TASK_thread offset
1272	mvc	40(8,%r11),BASED(.Lcleanup_system_call_const)
12730:	# check if the user time update has been done
1274	clg	%r9,BASED(.Lcleanup_system_call_insn+24)
1275	jh	0f
1276	lg	%r15,__LC_EXIT_TIMER
1277	slg	%r15,__LC_SYNC_ENTER_TIMER
1278	alg	%r15,__LC_USER_TIMER
1279	stg	%r15,__LC_USER_TIMER
12800:	# check if the system time update has been done
1281	clg	%r9,BASED(.Lcleanup_system_call_insn+32)
1282	jh	0f
1283	lg	%r15,__LC_LAST_UPDATE_TIMER
1284	slg	%r15,__LC_EXIT_TIMER
1285	alg	%r15,__LC_SYSTEM_TIMER
1286	stg	%r15,__LC_SYSTEM_TIMER
12870:	# update accounting time stamp
1288	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1289	# set up saved register r11
1290	lg	%r15,__LC_KERNEL_STACK
1291	la	%r9,STACK_FRAME_OVERHEAD(%r15)
1292	stg	%r9,24(%r11)		# r11 pt_regs pointer
1293	# fill pt_regs
1294	mvc	__PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1295	stmg	%r0,%r7,__PT_R0(%r9)
1296	mvc	__PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1297	mvc	__PT_INT_CODE(4,%r9),__LC_SVC_ILC
1298	xc	__PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1299	mvi	__PT_FLAGS+7(%r9),_PIF_SYSCALL
1300	# setup saved register r15
1301	stg	%r15,56(%r11)		# r15 stack pointer
1302	# set new psw address and exit
1303	larl	%r9,.Lsysc_do_svc
1304	br	%r14
1305.Lcleanup_system_call_insn:
1306	.quad	system_call
1307	.quad	.Lsysc_stmg
1308	.quad	.Lsysc_per
1309	.quad	.Lsysc_vtime+36
1310	.quad	.Lsysc_vtime+42
1311.Lcleanup_system_call_const:
1312	.quad	__TASK_thread
1313
1314.Lcleanup_sysc_tif:
1315	larl	%r9,.Lsysc_tif
1316	br	%r14
1317
1318.Lcleanup_sysc_restore:
1319	# check if stpt has been executed
1320	clg	%r9,BASED(.Lcleanup_sysc_restore_insn)
1321	jh	0f
1322	mvc	__LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1323	cghi	%r11,__LC_SAVE_AREA_ASYNC
1324	je	0f
1325	mvc	__LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
13260:	clg	%r9,BASED(.Lcleanup_sysc_restore_insn+8)
1327	je	1f
1328	lg	%r9,24(%r11)		# get saved pointer to pt_regs
1329	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r9)
1330	mvc	0(64,%r11),__PT_R8(%r9)
1331	lmg	%r0,%r7,__PT_R0(%r9)
13321:	lmg	%r8,%r9,__LC_RETURN_PSW
1333	br	%r14
1334.Lcleanup_sysc_restore_insn:
1335	.quad	.Lsysc_exit_timer
1336	.quad	.Lsysc_done - 4
1337
1338.Lcleanup_io_tif:
1339	larl	%r9,.Lio_tif
1340	br	%r14
1341
1342.Lcleanup_io_restore:
1343	# check if stpt has been executed
1344	clg	%r9,BASED(.Lcleanup_io_restore_insn)
1345	jh	0f
1346	mvc	__LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
13470:	clg	%r9,BASED(.Lcleanup_io_restore_insn+8)
1348	je	1f
1349	lg	%r9,24(%r11)		# get saved r11 pointer to pt_regs
1350	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r9)
1351	mvc	0(64,%r11),__PT_R8(%r9)
1352	lmg	%r0,%r7,__PT_R0(%r9)
13531:	lmg	%r8,%r9,__LC_RETURN_PSW
1354	br	%r14
1355.Lcleanup_io_restore_insn:
1356	.quad	.Lio_exit_timer
1357	.quad	.Lio_done - 4
1358
1359.Lcleanup_idle:
1360	ni	__LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1361	# copy interrupt clock & cpu timer
1362	mvc	__CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1363	mvc	__TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1364	cghi	%r11,__LC_SAVE_AREA_ASYNC
1365	je	0f
1366	mvc	__CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1367	mvc	__TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
13680:	# check if stck & stpt have been executed
1369	clg	%r9,BASED(.Lcleanup_idle_insn)
1370	jhe	1f
1371	mvc	__CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1372	mvc	__TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
13731:	# calculate idle cycles
1374#ifdef CONFIG_SMP
1375	clg	%r9,BASED(.Lcleanup_idle_insn)
1376	jl	3f
1377	larl	%r1,smp_cpu_mtid
1378	llgf	%r1,0(%r1)
1379	ltgr	%r1,%r1
1380	jz	3f
1381	.insn	rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1382	larl	%r3,mt_cycles
1383	ag	%r3,__LC_PERCPU_OFFSET
1384	la	%r4,__SF_EMPTY+16(%r15)
13852:	lg	%r0,0(%r3)
1386	slg	%r0,0(%r4)
1387	alg	%r0,64(%r4)
1388	stg	%r0,0(%r3)
1389	la	%r3,8(%r3)
1390	la	%r4,8(%r4)
1391	brct	%r1,2b
1392#endif
13933:	# account system time going idle
1394	lg	%r9,__LC_STEAL_TIMER
1395	alg	%r9,__CLOCK_IDLE_ENTER(%r2)
1396	slg	%r9,__LC_LAST_UPDATE_CLOCK
1397	stg	%r9,__LC_STEAL_TIMER
1398	mvc	__LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1399	lg	%r9,__LC_SYSTEM_TIMER
1400	alg	%r9,__LC_LAST_UPDATE_TIMER
1401	slg	%r9,__TIMER_IDLE_ENTER(%r2)
1402	stg	%r9,__LC_SYSTEM_TIMER
1403	mvc	__LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1404	# prepare return psw
1405	nihh	%r8,0xfcfd		# clear irq & wait state bits
1406	lg	%r9,48(%r11)		# return from psw_idle
1407	br	%r14
1408.Lcleanup_idle_insn:
1409	.quad	.Lpsw_idle_lpsw
1410
1411.Lcleanup_save_fpu_regs:
1412	larl	%r9,save_fpu_regs
1413	br	%r14
1414
1415.Lcleanup_load_fpu_regs:
1416	larl	%r9,load_fpu_regs
1417	br	%r14
1418
1419/*
1420 * Integer constants
1421 */
1422	.align	8
1423.Lcritical_start:
1424	.quad	.L__critical_start
1425.Lcritical_length:
1426	.quad	.L__critical_end - .L__critical_start
1427#if IS_ENABLED(CONFIG_KVM)
1428.Lsie_critical_start:
1429	.quad	.Lsie_gmap
1430.Lsie_critical_length:
1431	.quad	.Lsie_done - .Lsie_gmap
1432.Lsie_crit_mcck_start:
1433	.quad   .Lsie_entry
1434.Lsie_crit_mcck_length:
1435	.quad   .Lsie_skip - .Lsie_entry
1436#endif
1437
1438	.section .rodata, "a"
1439#define SYSCALL(esame,emu)	.long esame
1440	.globl	sys_call_table
1441sys_call_table:
1442#include "asm/syscall_table.h"
1443#undef SYSCALL
1444
1445#ifdef CONFIG_COMPAT
1446
1447#define SYSCALL(esame,emu)	.long emu
1448	.globl	sys_call_table_emu
1449sys_call_table_emu:
1450#include "asm/syscall_table.h"
1451#undef SYSCALL
1452#endif
1453