1 // SPDX-License-Identifier: GPL-2.0 2 /* BPF JIT compiler for RV64G 3 * 4 * Copyright(c) 2019 Björn Töpel <bjorn.topel@gmail.com> 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bpf.h> 10 #include <linux/filter.h> 11 #include <linux/memory.h> 12 #include <linux/stop_machine.h> 13 #include <asm/patch.h> 14 #include "bpf_jit.h" 15 16 #define RV_FENTRY_NINSNS 2 17 18 #define RV_REG_TCC RV_REG_A6 19 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */ 20 21 static const int regmap[] = { 22 [BPF_REG_0] = RV_REG_A5, 23 [BPF_REG_1] = RV_REG_A0, 24 [BPF_REG_2] = RV_REG_A1, 25 [BPF_REG_3] = RV_REG_A2, 26 [BPF_REG_4] = RV_REG_A3, 27 [BPF_REG_5] = RV_REG_A4, 28 [BPF_REG_6] = RV_REG_S1, 29 [BPF_REG_7] = RV_REG_S2, 30 [BPF_REG_8] = RV_REG_S3, 31 [BPF_REG_9] = RV_REG_S4, 32 [BPF_REG_FP] = RV_REG_S5, 33 [BPF_REG_AX] = RV_REG_T0, 34 }; 35 36 static const int pt_regmap[] = { 37 [RV_REG_A0] = offsetof(struct pt_regs, a0), 38 [RV_REG_A1] = offsetof(struct pt_regs, a1), 39 [RV_REG_A2] = offsetof(struct pt_regs, a2), 40 [RV_REG_A3] = offsetof(struct pt_regs, a3), 41 [RV_REG_A4] = offsetof(struct pt_regs, a4), 42 [RV_REG_A5] = offsetof(struct pt_regs, a5), 43 [RV_REG_S1] = offsetof(struct pt_regs, s1), 44 [RV_REG_S2] = offsetof(struct pt_regs, s2), 45 [RV_REG_S3] = offsetof(struct pt_regs, s3), 46 [RV_REG_S4] = offsetof(struct pt_regs, s4), 47 [RV_REG_S5] = offsetof(struct pt_regs, s5), 48 [RV_REG_T0] = offsetof(struct pt_regs, t0), 49 }; 50 51 enum { 52 RV_CTX_F_SEEN_TAIL_CALL = 0, 53 RV_CTX_F_SEEN_CALL = RV_REG_RA, 54 RV_CTX_F_SEEN_S1 = RV_REG_S1, 55 RV_CTX_F_SEEN_S2 = RV_REG_S2, 56 RV_CTX_F_SEEN_S3 = RV_REG_S3, 57 RV_CTX_F_SEEN_S4 = RV_REG_S4, 58 RV_CTX_F_SEEN_S5 = RV_REG_S5, 59 RV_CTX_F_SEEN_S6 = RV_REG_S6, 60 }; 61 62 static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx) 63 { 64 u8 reg = regmap[bpf_reg]; 65 66 switch (reg) { 67 case RV_CTX_F_SEEN_S1: 68 case RV_CTX_F_SEEN_S2: 69 case RV_CTX_F_SEEN_S3: 70 case RV_CTX_F_SEEN_S4: 71 case RV_CTX_F_SEEN_S5: 72 case RV_CTX_F_SEEN_S6: 73 __set_bit(reg, &ctx->flags); 74 } 75 return reg; 76 }; 77 78 static bool seen_reg(int reg, struct rv_jit_context *ctx) 79 { 80 switch (reg) { 81 case RV_CTX_F_SEEN_CALL: 82 case RV_CTX_F_SEEN_S1: 83 case RV_CTX_F_SEEN_S2: 84 case RV_CTX_F_SEEN_S3: 85 case RV_CTX_F_SEEN_S4: 86 case RV_CTX_F_SEEN_S5: 87 case RV_CTX_F_SEEN_S6: 88 return test_bit(reg, &ctx->flags); 89 } 90 return false; 91 } 92 93 static void mark_fp(struct rv_jit_context *ctx) 94 { 95 __set_bit(RV_CTX_F_SEEN_S5, &ctx->flags); 96 } 97 98 static void mark_call(struct rv_jit_context *ctx) 99 { 100 __set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 101 } 102 103 static bool seen_call(struct rv_jit_context *ctx) 104 { 105 return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 106 } 107 108 static void mark_tail_call(struct rv_jit_context *ctx) 109 { 110 __set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 111 } 112 113 static bool seen_tail_call(struct rv_jit_context *ctx) 114 { 115 return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 116 } 117 118 static u8 rv_tail_call_reg(struct rv_jit_context *ctx) 119 { 120 mark_tail_call(ctx); 121 122 if (seen_call(ctx)) { 123 __set_bit(RV_CTX_F_SEEN_S6, &ctx->flags); 124 return RV_REG_S6; 125 } 126 return RV_REG_A6; 127 } 128 129 static bool is_32b_int(s64 val) 130 { 131 return -(1L << 31) <= val && val < (1L << 31); 132 } 133 134 static bool in_auipc_jalr_range(s64 val) 135 { 136 /* 137 * auipc+jalr can reach any signed PC-relative offset in the range 138 * [-2^31 - 2^11, 2^31 - 2^11). 139 */ 140 return (-(1L << 31) - (1L << 11)) <= val && 141 val < ((1L << 31) - (1L << 11)); 142 } 143 144 /* Emit fixed-length instructions for address */ 145 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) 146 { 147 u64 ip = (u64)(ctx->insns + ctx->ninsns); 148 s64 off = addr - ip; 149 s64 upper = (off + (1 << 11)) >> 12; 150 s64 lower = off & 0xfff; 151 152 if (extra_pass && !in_auipc_jalr_range(off)) { 153 pr_err("bpf-jit: target offset 0x%llx is out of range\n", off); 154 return -ERANGE; 155 } 156 157 emit(rv_auipc(rd, upper), ctx); 158 emit(rv_addi(rd, rd, lower), ctx); 159 return 0; 160 } 161 162 /* Emit variable-length instructions for 32-bit and 64-bit imm */ 163 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) 164 { 165 /* Note that the immediate from the add is sign-extended, 166 * which means that we need to compensate this by adding 2^12, 167 * when the 12th bit is set. A simpler way of doing this, and 168 * getting rid of the check, is to just add 2**11 before the 169 * shift. The "Loading a 32-Bit constant" example from the 170 * "Computer Organization and Design, RISC-V edition" book by 171 * Patterson/Hennessy highlights this fact. 172 * 173 * This also means that we need to process LSB to MSB. 174 */ 175 s64 upper = (val + (1 << 11)) >> 12; 176 /* Sign-extend lower 12 bits to 64 bits since immediates for li, addiw, 177 * and addi are signed and RVC checks will perform signed comparisons. 178 */ 179 s64 lower = ((val & 0xfff) << 52) >> 52; 180 int shift; 181 182 if (is_32b_int(val)) { 183 if (upper) 184 emit_lui(rd, upper, ctx); 185 186 if (!upper) { 187 emit_li(rd, lower, ctx); 188 return; 189 } 190 191 emit_addiw(rd, rd, lower, ctx); 192 return; 193 } 194 195 shift = __ffs(upper); 196 upper >>= shift; 197 shift += 12; 198 199 emit_imm(rd, upper, ctx); 200 201 emit_slli(rd, rd, shift, ctx); 202 if (lower) 203 emit_addi(rd, rd, lower, ctx); 204 } 205 206 static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx) 207 { 208 int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8; 209 210 if (seen_reg(RV_REG_RA, ctx)) { 211 emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx); 212 store_offset -= 8; 213 } 214 emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx); 215 store_offset -= 8; 216 if (seen_reg(RV_REG_S1, ctx)) { 217 emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx); 218 store_offset -= 8; 219 } 220 if (seen_reg(RV_REG_S2, ctx)) { 221 emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx); 222 store_offset -= 8; 223 } 224 if (seen_reg(RV_REG_S3, ctx)) { 225 emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx); 226 store_offset -= 8; 227 } 228 if (seen_reg(RV_REG_S4, ctx)) { 229 emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx); 230 store_offset -= 8; 231 } 232 if (seen_reg(RV_REG_S5, ctx)) { 233 emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx); 234 store_offset -= 8; 235 } 236 if (seen_reg(RV_REG_S6, ctx)) { 237 emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx); 238 store_offset -= 8; 239 } 240 241 emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx); 242 /* Set return value. */ 243 if (!is_tail_call) 244 emit_mv(RV_REG_A0, RV_REG_A5, ctx); 245 emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA, 246 is_tail_call ? (RV_FENTRY_NINSNS + 1) * 4 : 0, /* skip reserved nops and TCC init */ 247 ctx); 248 } 249 250 static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff, 251 struct rv_jit_context *ctx) 252 { 253 switch (cond) { 254 case BPF_JEQ: 255 emit(rv_beq(rd, rs, rvoff >> 1), ctx); 256 return; 257 case BPF_JGT: 258 emit(rv_bltu(rs, rd, rvoff >> 1), ctx); 259 return; 260 case BPF_JLT: 261 emit(rv_bltu(rd, rs, rvoff >> 1), ctx); 262 return; 263 case BPF_JGE: 264 emit(rv_bgeu(rd, rs, rvoff >> 1), ctx); 265 return; 266 case BPF_JLE: 267 emit(rv_bgeu(rs, rd, rvoff >> 1), ctx); 268 return; 269 case BPF_JNE: 270 emit(rv_bne(rd, rs, rvoff >> 1), ctx); 271 return; 272 case BPF_JSGT: 273 emit(rv_blt(rs, rd, rvoff >> 1), ctx); 274 return; 275 case BPF_JSLT: 276 emit(rv_blt(rd, rs, rvoff >> 1), ctx); 277 return; 278 case BPF_JSGE: 279 emit(rv_bge(rd, rs, rvoff >> 1), ctx); 280 return; 281 case BPF_JSLE: 282 emit(rv_bge(rs, rd, rvoff >> 1), ctx); 283 } 284 } 285 286 static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff, 287 struct rv_jit_context *ctx) 288 { 289 s64 upper, lower; 290 291 if (is_13b_int(rvoff)) { 292 emit_bcc(cond, rd, rs, rvoff, ctx); 293 return; 294 } 295 296 /* Adjust for jal */ 297 rvoff -= 4; 298 299 /* Transform, e.g.: 300 * bne rd,rs,foo 301 * to 302 * beq rd,rs,<.L1> 303 * (auipc foo) 304 * jal(r) foo 305 * .L1 306 */ 307 cond = invert_bpf_cond(cond); 308 if (is_21b_int(rvoff)) { 309 emit_bcc(cond, rd, rs, 8, ctx); 310 emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx); 311 return; 312 } 313 314 /* 32b No need for an additional rvoff adjustment, since we 315 * get that from the auipc at PC', where PC = PC' + 4. 316 */ 317 upper = (rvoff + (1 << 11)) >> 12; 318 lower = rvoff & 0xfff; 319 320 emit_bcc(cond, rd, rs, 12, ctx); 321 emit(rv_auipc(RV_REG_T1, upper), ctx); 322 emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx); 323 } 324 325 static void emit_zext_32(u8 reg, struct rv_jit_context *ctx) 326 { 327 emit_slli(reg, reg, 32, ctx); 328 emit_srli(reg, reg, 32, ctx); 329 } 330 331 static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) 332 { 333 int tc_ninsn, off, start_insn = ctx->ninsns; 334 u8 tcc = rv_tail_call_reg(ctx); 335 336 /* a0: &ctx 337 * a1: &array 338 * a2: index 339 * 340 * if (index >= array->map.max_entries) 341 * goto out; 342 */ 343 tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] : 344 ctx->offset[0]; 345 emit_zext_32(RV_REG_A2, ctx); 346 347 off = offsetof(struct bpf_array, map.max_entries); 348 if (is_12b_check(off, insn)) 349 return -1; 350 emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx); 351 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 352 emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx); 353 354 /* if (--TCC < 0) 355 * goto out; 356 */ 357 emit_addi(RV_REG_TCC, tcc, -1, ctx); 358 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 359 emit_branch(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx); 360 361 /* prog = array->ptrs[index]; 362 * if (!prog) 363 * goto out; 364 */ 365 emit_slli(RV_REG_T2, RV_REG_A2, 3, ctx); 366 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_A1, ctx); 367 off = offsetof(struct bpf_array, ptrs); 368 if (is_12b_check(off, insn)) 369 return -1; 370 emit_ld(RV_REG_T2, off, RV_REG_T2, ctx); 371 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 372 emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx); 373 374 /* goto *(prog->bpf_func + 4); */ 375 off = offsetof(struct bpf_prog, bpf_func); 376 if (is_12b_check(off, insn)) 377 return -1; 378 emit_ld(RV_REG_T3, off, RV_REG_T2, ctx); 379 __build_epilogue(true, ctx); 380 return 0; 381 } 382 383 static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn, 384 struct rv_jit_context *ctx) 385 { 386 u8 code = insn->code; 387 388 switch (code) { 389 case BPF_JMP | BPF_JA: 390 case BPF_JMP | BPF_CALL: 391 case BPF_JMP | BPF_EXIT: 392 case BPF_JMP | BPF_TAIL_CALL: 393 break; 394 default: 395 *rd = bpf_to_rv_reg(insn->dst_reg, ctx); 396 } 397 398 if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) || 399 code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) || 400 code & BPF_LDX || code & BPF_STX) 401 *rs = bpf_to_rv_reg(insn->src_reg, ctx); 402 } 403 404 static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) 405 { 406 emit_mv(RV_REG_T2, *rd, ctx); 407 emit_zext_32(RV_REG_T2, ctx); 408 emit_mv(RV_REG_T1, *rs, ctx); 409 emit_zext_32(RV_REG_T1, ctx); 410 *rd = RV_REG_T2; 411 *rs = RV_REG_T1; 412 } 413 414 static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) 415 { 416 emit_addiw(RV_REG_T2, *rd, 0, ctx); 417 emit_addiw(RV_REG_T1, *rs, 0, ctx); 418 *rd = RV_REG_T2; 419 *rs = RV_REG_T1; 420 } 421 422 static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx) 423 { 424 emit_mv(RV_REG_T2, *rd, ctx); 425 emit_zext_32(RV_REG_T2, ctx); 426 emit_zext_32(RV_REG_T1, ctx); 427 *rd = RV_REG_T2; 428 } 429 430 static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx) 431 { 432 emit_addiw(RV_REG_T2, *rd, 0, ctx); 433 *rd = RV_REG_T2; 434 } 435 436 static int emit_jump_and_link(u8 rd, s64 rvoff, bool fixed_addr, 437 struct rv_jit_context *ctx) 438 { 439 s64 upper, lower; 440 441 if (rvoff && fixed_addr && is_21b_int(rvoff)) { 442 emit(rv_jal(rd, rvoff >> 1), ctx); 443 return 0; 444 } else if (in_auipc_jalr_range(rvoff)) { 445 upper = (rvoff + (1 << 11)) >> 12; 446 lower = rvoff & 0xfff; 447 emit(rv_auipc(RV_REG_T1, upper), ctx); 448 emit(rv_jalr(rd, RV_REG_T1, lower), ctx); 449 return 0; 450 } 451 452 pr_err("bpf-jit: target offset 0x%llx is out of range\n", rvoff); 453 return -ERANGE; 454 } 455 456 static bool is_signed_bpf_cond(u8 cond) 457 { 458 return cond == BPF_JSGT || cond == BPF_JSLT || 459 cond == BPF_JSGE || cond == BPF_JSLE; 460 } 461 462 static int emit_call(u64 addr, bool fixed_addr, struct rv_jit_context *ctx) 463 { 464 s64 off = 0; 465 u64 ip; 466 467 if (addr && ctx->insns) { 468 ip = (u64)(long)(ctx->insns + ctx->ninsns); 469 off = addr - ip; 470 } 471 472 return emit_jump_and_link(RV_REG_RA, off, fixed_addr, ctx); 473 } 474 475 static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64, 476 struct rv_jit_context *ctx) 477 { 478 u8 r0; 479 int jmp_offset; 480 481 if (off) { 482 if (is_12b_int(off)) { 483 emit_addi(RV_REG_T1, rd, off, ctx); 484 } else { 485 emit_imm(RV_REG_T1, off, ctx); 486 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 487 } 488 rd = RV_REG_T1; 489 } 490 491 switch (imm) { 492 /* lock *(u32/u64 *)(dst_reg + off16) <op>= src_reg */ 493 case BPF_ADD: 494 emit(is64 ? rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0) : 495 rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 496 break; 497 case BPF_AND: 498 emit(is64 ? rv_amoand_d(RV_REG_ZERO, rs, rd, 0, 0) : 499 rv_amoand_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 500 break; 501 case BPF_OR: 502 emit(is64 ? rv_amoor_d(RV_REG_ZERO, rs, rd, 0, 0) : 503 rv_amoor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 504 break; 505 case BPF_XOR: 506 emit(is64 ? rv_amoxor_d(RV_REG_ZERO, rs, rd, 0, 0) : 507 rv_amoxor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 508 break; 509 /* src_reg = atomic_fetch_<op>(dst_reg + off16, src_reg) */ 510 case BPF_ADD | BPF_FETCH: 511 emit(is64 ? rv_amoadd_d(rs, rs, rd, 0, 0) : 512 rv_amoadd_w(rs, rs, rd, 0, 0), ctx); 513 if (!is64) 514 emit_zext_32(rs, ctx); 515 break; 516 case BPF_AND | BPF_FETCH: 517 emit(is64 ? rv_amoand_d(rs, rs, rd, 0, 0) : 518 rv_amoand_w(rs, rs, rd, 0, 0), ctx); 519 if (!is64) 520 emit_zext_32(rs, ctx); 521 break; 522 case BPF_OR | BPF_FETCH: 523 emit(is64 ? rv_amoor_d(rs, rs, rd, 0, 0) : 524 rv_amoor_w(rs, rs, rd, 0, 0), ctx); 525 if (!is64) 526 emit_zext_32(rs, ctx); 527 break; 528 case BPF_XOR | BPF_FETCH: 529 emit(is64 ? rv_amoxor_d(rs, rs, rd, 0, 0) : 530 rv_amoxor_w(rs, rs, rd, 0, 0), ctx); 531 if (!is64) 532 emit_zext_32(rs, ctx); 533 break; 534 /* src_reg = atomic_xchg(dst_reg + off16, src_reg); */ 535 case BPF_XCHG: 536 emit(is64 ? rv_amoswap_d(rs, rs, rd, 0, 0) : 537 rv_amoswap_w(rs, rs, rd, 0, 0), ctx); 538 if (!is64) 539 emit_zext_32(rs, ctx); 540 break; 541 /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */ 542 case BPF_CMPXCHG: 543 r0 = bpf_to_rv_reg(BPF_REG_0, ctx); 544 emit(is64 ? rv_addi(RV_REG_T2, r0, 0) : 545 rv_addiw(RV_REG_T2, r0, 0), ctx); 546 emit(is64 ? rv_lr_d(r0, 0, rd, 0, 0) : 547 rv_lr_w(r0, 0, rd, 0, 0), ctx); 548 jmp_offset = ninsns_rvoff(8); 549 emit(rv_bne(RV_REG_T2, r0, jmp_offset >> 1), ctx); 550 emit(is64 ? rv_sc_d(RV_REG_T3, rs, rd, 0, 0) : 551 rv_sc_w(RV_REG_T3, rs, rd, 0, 0), ctx); 552 jmp_offset = ninsns_rvoff(-6); 553 emit(rv_bne(RV_REG_T3, 0, jmp_offset >> 1), ctx); 554 emit(rv_fence(0x3, 0x3), ctx); 555 break; 556 } 557 } 558 559 #define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0) 560 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 561 562 bool ex_handler_bpf(const struct exception_table_entry *ex, 563 struct pt_regs *regs) 564 { 565 off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 566 int regs_offset = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 567 568 *(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0; 569 regs->epc = (unsigned long)&ex->fixup - offset; 570 571 return true; 572 } 573 574 /* For accesses to BTF pointers, add an entry to the exception table */ 575 static int add_exception_handler(const struct bpf_insn *insn, 576 struct rv_jit_context *ctx, 577 int dst_reg, int insn_len) 578 { 579 struct exception_table_entry *ex; 580 unsigned long pc; 581 off_t offset; 582 583 if (!ctx->insns || !ctx->prog->aux->extable || BPF_MODE(insn->code) != BPF_PROBE_MEM) 584 return 0; 585 586 if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries)) 587 return -EINVAL; 588 589 if (WARN_ON_ONCE(insn_len > ctx->ninsns)) 590 return -EINVAL; 591 592 if (WARN_ON_ONCE(!rvc_enabled() && insn_len == 1)) 593 return -EINVAL; 594 595 ex = &ctx->prog->aux->extable[ctx->nexentries]; 596 pc = (unsigned long)&ctx->insns[ctx->ninsns - insn_len]; 597 598 offset = pc - (long)&ex->insn; 599 if (WARN_ON_ONCE(offset >= 0 || offset < INT_MIN)) 600 return -ERANGE; 601 ex->insn = offset; 602 603 /* 604 * Since the extable follows the program, the fixup offset is always 605 * negative and limited to BPF_JIT_REGION_SIZE. Store a positive value 606 * to keep things simple, and put the destination register in the upper 607 * bits. We don't need to worry about buildtime or runtime sort 608 * modifying the upper bits because the table is already sorted, and 609 * isn't part of the main exception table. 610 */ 611 offset = (long)&ex->fixup - (pc + insn_len * sizeof(u16)); 612 if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, offset)) 613 return -ERANGE; 614 615 ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, offset) | 616 FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 617 ex->type = EX_TYPE_BPF; 618 619 ctx->nexentries++; 620 return 0; 621 } 622 623 static int gen_jump_or_nops(void *target, void *ip, u32 *insns, bool is_call) 624 { 625 s64 rvoff; 626 struct rv_jit_context ctx; 627 628 ctx.ninsns = 0; 629 ctx.insns = (u16 *)insns; 630 631 if (!target) { 632 emit(rv_nop(), &ctx); 633 emit(rv_nop(), &ctx); 634 return 0; 635 } 636 637 rvoff = (s64)(target - ip); 638 return emit_jump_and_link(is_call ? RV_REG_T0 : RV_REG_ZERO, rvoff, false, &ctx); 639 } 640 641 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type poke_type, 642 void *old_addr, void *new_addr) 643 { 644 u32 old_insns[RV_FENTRY_NINSNS], new_insns[RV_FENTRY_NINSNS]; 645 bool is_call = poke_type == BPF_MOD_CALL; 646 int ret; 647 648 if (!is_kernel_text((unsigned long)ip) && 649 !is_bpf_text_address((unsigned long)ip)) 650 return -ENOTSUPP; 651 652 ret = gen_jump_or_nops(old_addr, ip, old_insns, is_call); 653 if (ret) 654 return ret; 655 656 if (memcmp(ip, old_insns, RV_FENTRY_NINSNS * 4)) 657 return -EFAULT; 658 659 ret = gen_jump_or_nops(new_addr, ip, new_insns, is_call); 660 if (ret) 661 return ret; 662 663 cpus_read_lock(); 664 mutex_lock(&text_mutex); 665 if (memcmp(ip, new_insns, RV_FENTRY_NINSNS * 4)) 666 ret = patch_text(ip, new_insns, RV_FENTRY_NINSNS); 667 mutex_unlock(&text_mutex); 668 cpus_read_unlock(); 669 670 return ret; 671 } 672 673 static void store_args(int nregs, int args_off, struct rv_jit_context *ctx) 674 { 675 int i; 676 677 for (i = 0; i < nregs; i++) { 678 emit_sd(RV_REG_FP, -args_off, RV_REG_A0 + i, ctx); 679 args_off -= 8; 680 } 681 } 682 683 static void restore_args(int nregs, int args_off, struct rv_jit_context *ctx) 684 { 685 int i; 686 687 for (i = 0; i < nregs; i++) { 688 emit_ld(RV_REG_A0 + i, -args_off, RV_REG_FP, ctx); 689 args_off -= 8; 690 } 691 } 692 693 static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_off, 694 int run_ctx_off, bool save_ret, struct rv_jit_context *ctx) 695 { 696 int ret, branch_off; 697 struct bpf_prog *p = l->link.prog; 698 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 699 700 if (l->cookie) { 701 emit_imm(RV_REG_T1, l->cookie, ctx); 702 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_T1, ctx); 703 } else { 704 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_ZERO, ctx); 705 } 706 707 /* arg1: prog */ 708 emit_imm(RV_REG_A0, (const s64)p, ctx); 709 /* arg2: &run_ctx */ 710 emit_addi(RV_REG_A1, RV_REG_FP, -run_ctx_off, ctx); 711 ret = emit_call((const u64)bpf_trampoline_enter(p), true, ctx); 712 if (ret) 713 return ret; 714 715 /* if (__bpf_prog_enter(prog) == 0) 716 * goto skip_exec_of_prog; 717 */ 718 branch_off = ctx->ninsns; 719 /* nop reserved for conditional jump */ 720 emit(rv_nop(), ctx); 721 722 /* store prog start time */ 723 emit_mv(RV_REG_S1, RV_REG_A0, ctx); 724 725 /* arg1: &args_off */ 726 emit_addi(RV_REG_A0, RV_REG_FP, -args_off, ctx); 727 if (!p->jited) 728 /* arg2: progs[i]->insnsi for interpreter */ 729 emit_imm(RV_REG_A1, (const s64)p->insnsi, ctx); 730 ret = emit_call((const u64)p->bpf_func, true, ctx); 731 if (ret) 732 return ret; 733 734 if (save_ret) 735 emit_sd(RV_REG_FP, -retval_off, regmap[BPF_REG_0], ctx); 736 737 /* update branch with beqz */ 738 if (ctx->insns) { 739 int offset = ninsns_rvoff(ctx->ninsns - branch_off); 740 u32 insn = rv_beq(RV_REG_A0, RV_REG_ZERO, offset >> 1); 741 *(u32 *)(ctx->insns + branch_off) = insn; 742 } 743 744 /* arg1: prog */ 745 emit_imm(RV_REG_A0, (const s64)p, ctx); 746 /* arg2: prog start time */ 747 emit_mv(RV_REG_A1, RV_REG_S1, ctx); 748 /* arg3: &run_ctx */ 749 emit_addi(RV_REG_A2, RV_REG_FP, -run_ctx_off, ctx); 750 ret = emit_call((const u64)bpf_trampoline_exit(p), true, ctx); 751 752 return ret; 753 } 754 755 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, 756 const struct btf_func_model *m, 757 struct bpf_tramp_links *tlinks, 758 void *func_addr, u32 flags, 759 struct rv_jit_context *ctx) 760 { 761 int i, ret, offset; 762 int *branches_off = NULL; 763 int stack_size = 0, nregs = m->nr_args; 764 int retval_off, args_off, nregs_off, ip_off, run_ctx_off, sreg_off; 765 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 766 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 767 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 768 void *orig_call = func_addr; 769 bool save_ret; 770 u32 insn; 771 772 /* Two types of generated trampoline stack layout: 773 * 774 * 1. trampoline called from function entry 775 * -------------------------------------- 776 * FP + 8 [ RA to parent func ] return address to parent 777 * function 778 * FP + 0 [ FP of parent func ] frame pointer of parent 779 * function 780 * FP - 8 [ T0 to traced func ] return address of traced 781 * function 782 * FP - 16 [ FP of traced func ] frame pointer of traced 783 * function 784 * -------------------------------------- 785 * 786 * 2. trampoline called directly 787 * -------------------------------------- 788 * FP - 8 [ RA to caller func ] return address to caller 789 * function 790 * FP - 16 [ FP of caller func ] frame pointer of caller 791 * function 792 * -------------------------------------- 793 * 794 * FP - retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 795 * BPF_TRAMP_F_RET_FENTRY_RET 796 * [ argN ] 797 * [ ... ] 798 * FP - args_off [ arg1 ] 799 * 800 * FP - nregs_off [ regs count ] 801 * 802 * FP - ip_off [ traced func ] BPF_TRAMP_F_IP_ARG 803 * 804 * FP - run_ctx_off [ bpf_tramp_run_ctx ] 805 * 806 * FP - sreg_off [ callee saved reg ] 807 * 808 * [ pads ] pads for 16 bytes alignment 809 */ 810 811 if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY)) 812 return -ENOTSUPP; 813 814 /* extra regiters for struct arguments */ 815 for (i = 0; i < m->nr_args; i++) 816 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 817 nregs += round_up(m->arg_size[i], 8) / 8 - 1; 818 819 /* 8 arguments passed by registers */ 820 if (nregs > 8) 821 return -ENOTSUPP; 822 823 /* room of trampoline frame to store return address and frame pointer */ 824 stack_size += 16; 825 826 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 827 if (save_ret) { 828 stack_size += 8; 829 retval_off = stack_size; 830 } 831 832 stack_size += nregs * 8; 833 args_off = stack_size; 834 835 stack_size += 8; 836 nregs_off = stack_size; 837 838 if (flags & BPF_TRAMP_F_IP_ARG) { 839 stack_size += 8; 840 ip_off = stack_size; 841 } 842 843 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 844 run_ctx_off = stack_size; 845 846 stack_size += 8; 847 sreg_off = stack_size; 848 849 stack_size = round_up(stack_size, 16); 850 851 if (func_addr) { 852 /* For the trampoline called from function entry, 853 * the frame of traced function and the frame of 854 * trampoline need to be considered. 855 */ 856 emit_addi(RV_REG_SP, RV_REG_SP, -16, ctx); 857 emit_sd(RV_REG_SP, 8, RV_REG_RA, ctx); 858 emit_sd(RV_REG_SP, 0, RV_REG_FP, ctx); 859 emit_addi(RV_REG_FP, RV_REG_SP, 16, ctx); 860 861 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 862 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_T0, ctx); 863 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 864 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 865 } else { 866 /* For the trampoline called directly, just handle 867 * the frame of trampoline. 868 */ 869 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 870 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_RA, ctx); 871 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 872 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 873 } 874 875 /* callee saved register S1 to pass start time */ 876 emit_sd(RV_REG_FP, -sreg_off, RV_REG_S1, ctx); 877 878 /* store ip address of the traced function */ 879 if (flags & BPF_TRAMP_F_IP_ARG) { 880 emit_imm(RV_REG_T1, (const s64)func_addr, ctx); 881 emit_sd(RV_REG_FP, -ip_off, RV_REG_T1, ctx); 882 } 883 884 emit_li(RV_REG_T1, nregs, ctx); 885 emit_sd(RV_REG_FP, -nregs_off, RV_REG_T1, ctx); 886 887 store_args(nregs, args_off, ctx); 888 889 /* skip to actual body of traced function */ 890 if (flags & BPF_TRAMP_F_SKIP_FRAME) 891 orig_call += RV_FENTRY_NINSNS * 4; 892 893 if (flags & BPF_TRAMP_F_CALL_ORIG) { 894 emit_imm(RV_REG_A0, (const s64)im, ctx); 895 ret = emit_call((const u64)__bpf_tramp_enter, true, ctx); 896 if (ret) 897 return ret; 898 } 899 900 for (i = 0; i < fentry->nr_links; i++) { 901 ret = invoke_bpf_prog(fentry->links[i], args_off, retval_off, run_ctx_off, 902 flags & BPF_TRAMP_F_RET_FENTRY_RET, ctx); 903 if (ret) 904 return ret; 905 } 906 907 if (fmod_ret->nr_links) { 908 branches_off = kcalloc(fmod_ret->nr_links, sizeof(int), GFP_KERNEL); 909 if (!branches_off) 910 return -ENOMEM; 911 912 /* cleanup to avoid garbage return value confusion */ 913 emit_sd(RV_REG_FP, -retval_off, RV_REG_ZERO, ctx); 914 for (i = 0; i < fmod_ret->nr_links; i++) { 915 ret = invoke_bpf_prog(fmod_ret->links[i], args_off, retval_off, 916 run_ctx_off, true, ctx); 917 if (ret) 918 goto out; 919 emit_ld(RV_REG_T1, -retval_off, RV_REG_FP, ctx); 920 branches_off[i] = ctx->ninsns; 921 /* nop reserved for conditional jump */ 922 emit(rv_nop(), ctx); 923 } 924 } 925 926 if (flags & BPF_TRAMP_F_CALL_ORIG) { 927 restore_args(nregs, args_off, ctx); 928 ret = emit_call((const u64)orig_call, true, ctx); 929 if (ret) 930 goto out; 931 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx); 932 im->ip_after_call = ctx->insns + ctx->ninsns; 933 /* 2 nops reserved for auipc+jalr pair */ 934 emit(rv_nop(), ctx); 935 emit(rv_nop(), ctx); 936 } 937 938 /* update branches saved in invoke_bpf_mod_ret with bnez */ 939 for (i = 0; ctx->insns && i < fmod_ret->nr_links; i++) { 940 offset = ninsns_rvoff(ctx->ninsns - branches_off[i]); 941 insn = rv_bne(RV_REG_T1, RV_REG_ZERO, offset >> 1); 942 *(u32 *)(ctx->insns + branches_off[i]) = insn; 943 } 944 945 for (i = 0; i < fexit->nr_links; i++) { 946 ret = invoke_bpf_prog(fexit->links[i], args_off, retval_off, 947 run_ctx_off, false, ctx); 948 if (ret) 949 goto out; 950 } 951 952 if (flags & BPF_TRAMP_F_CALL_ORIG) { 953 im->ip_epilogue = ctx->insns + ctx->ninsns; 954 emit_imm(RV_REG_A0, (const s64)im, ctx); 955 ret = emit_call((const u64)__bpf_tramp_exit, true, ctx); 956 if (ret) 957 goto out; 958 } 959 960 if (flags & BPF_TRAMP_F_RESTORE_REGS) 961 restore_args(nregs, args_off, ctx); 962 963 if (save_ret) 964 emit_ld(RV_REG_A0, -retval_off, RV_REG_FP, ctx); 965 966 emit_ld(RV_REG_S1, -sreg_off, RV_REG_FP, ctx); 967 968 if (func_addr) { 969 /* trampoline called from function entry */ 970 emit_ld(RV_REG_T0, stack_size - 8, RV_REG_SP, ctx); 971 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 972 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 973 974 emit_ld(RV_REG_RA, 8, RV_REG_SP, ctx); 975 emit_ld(RV_REG_FP, 0, RV_REG_SP, ctx); 976 emit_addi(RV_REG_SP, RV_REG_SP, 16, ctx); 977 978 if (flags & BPF_TRAMP_F_SKIP_FRAME) 979 /* return to parent function */ 980 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 981 else 982 /* return to traced function */ 983 emit_jalr(RV_REG_ZERO, RV_REG_T0, 0, ctx); 984 } else { 985 /* trampoline called directly */ 986 emit_ld(RV_REG_RA, stack_size - 8, RV_REG_SP, ctx); 987 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 988 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 989 990 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 991 } 992 993 ret = ctx->ninsns; 994 out: 995 kfree(branches_off); 996 return ret; 997 } 998 999 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, 1000 void *image_end, const struct btf_func_model *m, 1001 u32 flags, struct bpf_tramp_links *tlinks, 1002 void *func_addr) 1003 { 1004 int ret; 1005 struct rv_jit_context ctx; 1006 1007 ctx.ninsns = 0; 1008 ctx.insns = NULL; 1009 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1010 if (ret < 0) 1011 return ret; 1012 1013 if (ninsns_rvoff(ret) > (long)image_end - (long)image) 1014 return -EFBIG; 1015 1016 ctx.ninsns = 0; 1017 ctx.insns = image; 1018 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1019 if (ret < 0) 1020 return ret; 1021 1022 bpf_flush_icache(ctx.insns, ctx.insns + ctx.ninsns); 1023 1024 return ninsns_rvoff(ret); 1025 } 1026 1027 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 1028 bool extra_pass) 1029 { 1030 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 || 1031 BPF_CLASS(insn->code) == BPF_JMP; 1032 int s, e, rvoff, ret, i = insn - ctx->prog->insnsi; 1033 struct bpf_prog_aux *aux = ctx->prog->aux; 1034 u8 rd = -1, rs = -1, code = insn->code; 1035 s16 off = insn->off; 1036 s32 imm = insn->imm; 1037 1038 init_regs(&rd, &rs, insn, ctx); 1039 1040 switch (code) { 1041 /* dst = src */ 1042 case BPF_ALU | BPF_MOV | BPF_X: 1043 case BPF_ALU64 | BPF_MOV | BPF_X: 1044 if (imm == 1) { 1045 /* Special mov32 for zext */ 1046 emit_zext_32(rd, ctx); 1047 break; 1048 } 1049 emit_mv(rd, rs, ctx); 1050 if (!is64 && !aux->verifier_zext) 1051 emit_zext_32(rd, ctx); 1052 break; 1053 1054 /* dst = dst OP src */ 1055 case BPF_ALU | BPF_ADD | BPF_X: 1056 case BPF_ALU64 | BPF_ADD | BPF_X: 1057 emit_add(rd, rd, rs, ctx); 1058 if (!is64 && !aux->verifier_zext) 1059 emit_zext_32(rd, ctx); 1060 break; 1061 case BPF_ALU | BPF_SUB | BPF_X: 1062 case BPF_ALU64 | BPF_SUB | BPF_X: 1063 if (is64) 1064 emit_sub(rd, rd, rs, ctx); 1065 else 1066 emit_subw(rd, rd, rs, ctx); 1067 1068 if (!is64 && !aux->verifier_zext) 1069 emit_zext_32(rd, ctx); 1070 break; 1071 case BPF_ALU | BPF_AND | BPF_X: 1072 case BPF_ALU64 | BPF_AND | BPF_X: 1073 emit_and(rd, rd, rs, ctx); 1074 if (!is64 && !aux->verifier_zext) 1075 emit_zext_32(rd, ctx); 1076 break; 1077 case BPF_ALU | BPF_OR | BPF_X: 1078 case BPF_ALU64 | BPF_OR | BPF_X: 1079 emit_or(rd, rd, rs, ctx); 1080 if (!is64 && !aux->verifier_zext) 1081 emit_zext_32(rd, ctx); 1082 break; 1083 case BPF_ALU | BPF_XOR | BPF_X: 1084 case BPF_ALU64 | BPF_XOR | BPF_X: 1085 emit_xor(rd, rd, rs, ctx); 1086 if (!is64 && !aux->verifier_zext) 1087 emit_zext_32(rd, ctx); 1088 break; 1089 case BPF_ALU | BPF_MUL | BPF_X: 1090 case BPF_ALU64 | BPF_MUL | BPF_X: 1091 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); 1092 if (!is64 && !aux->verifier_zext) 1093 emit_zext_32(rd, ctx); 1094 break; 1095 case BPF_ALU | BPF_DIV | BPF_X: 1096 case BPF_ALU64 | BPF_DIV | BPF_X: 1097 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); 1098 if (!is64 && !aux->verifier_zext) 1099 emit_zext_32(rd, ctx); 1100 break; 1101 case BPF_ALU | BPF_MOD | BPF_X: 1102 case BPF_ALU64 | BPF_MOD | BPF_X: 1103 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); 1104 if (!is64 && !aux->verifier_zext) 1105 emit_zext_32(rd, ctx); 1106 break; 1107 case BPF_ALU | BPF_LSH | BPF_X: 1108 case BPF_ALU64 | BPF_LSH | BPF_X: 1109 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); 1110 if (!is64 && !aux->verifier_zext) 1111 emit_zext_32(rd, ctx); 1112 break; 1113 case BPF_ALU | BPF_RSH | BPF_X: 1114 case BPF_ALU64 | BPF_RSH | BPF_X: 1115 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); 1116 if (!is64 && !aux->verifier_zext) 1117 emit_zext_32(rd, ctx); 1118 break; 1119 case BPF_ALU | BPF_ARSH | BPF_X: 1120 case BPF_ALU64 | BPF_ARSH | BPF_X: 1121 emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx); 1122 if (!is64 && !aux->verifier_zext) 1123 emit_zext_32(rd, ctx); 1124 break; 1125 1126 /* dst = -dst */ 1127 case BPF_ALU | BPF_NEG: 1128 case BPF_ALU64 | BPF_NEG: 1129 emit_sub(rd, RV_REG_ZERO, rd, ctx); 1130 if (!is64 && !aux->verifier_zext) 1131 emit_zext_32(rd, ctx); 1132 break; 1133 1134 /* dst = BSWAP##imm(dst) */ 1135 case BPF_ALU | BPF_END | BPF_FROM_LE: 1136 switch (imm) { 1137 case 16: 1138 emit_slli(rd, rd, 48, ctx); 1139 emit_srli(rd, rd, 48, ctx); 1140 break; 1141 case 32: 1142 if (!aux->verifier_zext) 1143 emit_zext_32(rd, ctx); 1144 break; 1145 case 64: 1146 /* Do nothing */ 1147 break; 1148 } 1149 break; 1150 1151 case BPF_ALU | BPF_END | BPF_FROM_BE: 1152 emit_li(RV_REG_T2, 0, ctx); 1153 1154 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1155 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1156 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1157 emit_srli(rd, rd, 8, ctx); 1158 if (imm == 16) 1159 goto out_be; 1160 1161 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1162 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1163 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1164 emit_srli(rd, rd, 8, ctx); 1165 1166 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1167 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1168 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1169 emit_srli(rd, rd, 8, ctx); 1170 if (imm == 32) 1171 goto out_be; 1172 1173 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1174 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1175 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1176 emit_srli(rd, rd, 8, ctx); 1177 1178 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1179 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1180 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1181 emit_srli(rd, rd, 8, ctx); 1182 1183 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1184 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1185 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1186 emit_srli(rd, rd, 8, ctx); 1187 1188 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1189 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1190 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1191 emit_srli(rd, rd, 8, ctx); 1192 out_be: 1193 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1194 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1195 1196 emit_mv(rd, RV_REG_T2, ctx); 1197 break; 1198 1199 /* dst = imm */ 1200 case BPF_ALU | BPF_MOV | BPF_K: 1201 case BPF_ALU64 | BPF_MOV | BPF_K: 1202 emit_imm(rd, imm, ctx); 1203 if (!is64 && !aux->verifier_zext) 1204 emit_zext_32(rd, ctx); 1205 break; 1206 1207 /* dst = dst OP imm */ 1208 case BPF_ALU | BPF_ADD | BPF_K: 1209 case BPF_ALU64 | BPF_ADD | BPF_K: 1210 if (is_12b_int(imm)) { 1211 emit_addi(rd, rd, imm, ctx); 1212 } else { 1213 emit_imm(RV_REG_T1, imm, ctx); 1214 emit_add(rd, rd, RV_REG_T1, ctx); 1215 } 1216 if (!is64 && !aux->verifier_zext) 1217 emit_zext_32(rd, ctx); 1218 break; 1219 case BPF_ALU | BPF_SUB | BPF_K: 1220 case BPF_ALU64 | BPF_SUB | BPF_K: 1221 if (is_12b_int(-imm)) { 1222 emit_addi(rd, rd, -imm, ctx); 1223 } else { 1224 emit_imm(RV_REG_T1, imm, ctx); 1225 emit_sub(rd, rd, RV_REG_T1, ctx); 1226 } 1227 if (!is64 && !aux->verifier_zext) 1228 emit_zext_32(rd, ctx); 1229 break; 1230 case BPF_ALU | BPF_AND | BPF_K: 1231 case BPF_ALU64 | BPF_AND | BPF_K: 1232 if (is_12b_int(imm)) { 1233 emit_andi(rd, rd, imm, ctx); 1234 } else { 1235 emit_imm(RV_REG_T1, imm, ctx); 1236 emit_and(rd, rd, RV_REG_T1, ctx); 1237 } 1238 if (!is64 && !aux->verifier_zext) 1239 emit_zext_32(rd, ctx); 1240 break; 1241 case BPF_ALU | BPF_OR | BPF_K: 1242 case BPF_ALU64 | BPF_OR | BPF_K: 1243 if (is_12b_int(imm)) { 1244 emit(rv_ori(rd, rd, imm), ctx); 1245 } else { 1246 emit_imm(RV_REG_T1, imm, ctx); 1247 emit_or(rd, rd, RV_REG_T1, ctx); 1248 } 1249 if (!is64 && !aux->verifier_zext) 1250 emit_zext_32(rd, ctx); 1251 break; 1252 case BPF_ALU | BPF_XOR | BPF_K: 1253 case BPF_ALU64 | BPF_XOR | BPF_K: 1254 if (is_12b_int(imm)) { 1255 emit(rv_xori(rd, rd, imm), ctx); 1256 } else { 1257 emit_imm(RV_REG_T1, imm, ctx); 1258 emit_xor(rd, rd, RV_REG_T1, ctx); 1259 } 1260 if (!is64 && !aux->verifier_zext) 1261 emit_zext_32(rd, ctx); 1262 break; 1263 case BPF_ALU | BPF_MUL | BPF_K: 1264 case BPF_ALU64 | BPF_MUL | BPF_K: 1265 emit_imm(RV_REG_T1, imm, ctx); 1266 emit(is64 ? rv_mul(rd, rd, RV_REG_T1) : 1267 rv_mulw(rd, rd, RV_REG_T1), ctx); 1268 if (!is64 && !aux->verifier_zext) 1269 emit_zext_32(rd, ctx); 1270 break; 1271 case BPF_ALU | BPF_DIV | BPF_K: 1272 case BPF_ALU64 | BPF_DIV | BPF_K: 1273 emit_imm(RV_REG_T1, imm, ctx); 1274 emit(is64 ? rv_divu(rd, rd, RV_REG_T1) : 1275 rv_divuw(rd, rd, RV_REG_T1), ctx); 1276 if (!is64 && !aux->verifier_zext) 1277 emit_zext_32(rd, ctx); 1278 break; 1279 case BPF_ALU | BPF_MOD | BPF_K: 1280 case BPF_ALU64 | BPF_MOD | BPF_K: 1281 emit_imm(RV_REG_T1, imm, ctx); 1282 emit(is64 ? rv_remu(rd, rd, RV_REG_T1) : 1283 rv_remuw(rd, rd, RV_REG_T1), ctx); 1284 if (!is64 && !aux->verifier_zext) 1285 emit_zext_32(rd, ctx); 1286 break; 1287 case BPF_ALU | BPF_LSH | BPF_K: 1288 case BPF_ALU64 | BPF_LSH | BPF_K: 1289 emit_slli(rd, rd, imm, ctx); 1290 1291 if (!is64 && !aux->verifier_zext) 1292 emit_zext_32(rd, ctx); 1293 break; 1294 case BPF_ALU | BPF_RSH | BPF_K: 1295 case BPF_ALU64 | BPF_RSH | BPF_K: 1296 if (is64) 1297 emit_srli(rd, rd, imm, ctx); 1298 else 1299 emit(rv_srliw(rd, rd, imm), ctx); 1300 1301 if (!is64 && !aux->verifier_zext) 1302 emit_zext_32(rd, ctx); 1303 break; 1304 case BPF_ALU | BPF_ARSH | BPF_K: 1305 case BPF_ALU64 | BPF_ARSH | BPF_K: 1306 if (is64) 1307 emit_srai(rd, rd, imm, ctx); 1308 else 1309 emit(rv_sraiw(rd, rd, imm), ctx); 1310 1311 if (!is64 && !aux->verifier_zext) 1312 emit_zext_32(rd, ctx); 1313 break; 1314 1315 /* JUMP off */ 1316 case BPF_JMP | BPF_JA: 1317 rvoff = rv_offset(i, off, ctx); 1318 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1319 if (ret) 1320 return ret; 1321 break; 1322 1323 /* IF (dst COND src) JUMP off */ 1324 case BPF_JMP | BPF_JEQ | BPF_X: 1325 case BPF_JMP32 | BPF_JEQ | BPF_X: 1326 case BPF_JMP | BPF_JGT | BPF_X: 1327 case BPF_JMP32 | BPF_JGT | BPF_X: 1328 case BPF_JMP | BPF_JLT | BPF_X: 1329 case BPF_JMP32 | BPF_JLT | BPF_X: 1330 case BPF_JMP | BPF_JGE | BPF_X: 1331 case BPF_JMP32 | BPF_JGE | BPF_X: 1332 case BPF_JMP | BPF_JLE | BPF_X: 1333 case BPF_JMP32 | BPF_JLE | BPF_X: 1334 case BPF_JMP | BPF_JNE | BPF_X: 1335 case BPF_JMP32 | BPF_JNE | BPF_X: 1336 case BPF_JMP | BPF_JSGT | BPF_X: 1337 case BPF_JMP32 | BPF_JSGT | BPF_X: 1338 case BPF_JMP | BPF_JSLT | BPF_X: 1339 case BPF_JMP32 | BPF_JSLT | BPF_X: 1340 case BPF_JMP | BPF_JSGE | BPF_X: 1341 case BPF_JMP32 | BPF_JSGE | BPF_X: 1342 case BPF_JMP | BPF_JSLE | BPF_X: 1343 case BPF_JMP32 | BPF_JSLE | BPF_X: 1344 case BPF_JMP | BPF_JSET | BPF_X: 1345 case BPF_JMP32 | BPF_JSET | BPF_X: 1346 rvoff = rv_offset(i, off, ctx); 1347 if (!is64) { 1348 s = ctx->ninsns; 1349 if (is_signed_bpf_cond(BPF_OP(code))) 1350 emit_sext_32_rd_rs(&rd, &rs, ctx); 1351 else 1352 emit_zext_32_rd_rs(&rd, &rs, ctx); 1353 e = ctx->ninsns; 1354 1355 /* Adjust for extra insns */ 1356 rvoff -= ninsns_rvoff(e - s); 1357 } 1358 1359 if (BPF_OP(code) == BPF_JSET) { 1360 /* Adjust for and */ 1361 rvoff -= 4; 1362 emit_and(RV_REG_T1, rd, rs, ctx); 1363 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, 1364 ctx); 1365 } else { 1366 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1367 } 1368 break; 1369 1370 /* IF (dst COND imm) JUMP off */ 1371 case BPF_JMP | BPF_JEQ | BPF_K: 1372 case BPF_JMP32 | BPF_JEQ | BPF_K: 1373 case BPF_JMP | BPF_JGT | BPF_K: 1374 case BPF_JMP32 | BPF_JGT | BPF_K: 1375 case BPF_JMP | BPF_JLT | BPF_K: 1376 case BPF_JMP32 | BPF_JLT | BPF_K: 1377 case BPF_JMP | BPF_JGE | BPF_K: 1378 case BPF_JMP32 | BPF_JGE | BPF_K: 1379 case BPF_JMP | BPF_JLE | BPF_K: 1380 case BPF_JMP32 | BPF_JLE | BPF_K: 1381 case BPF_JMP | BPF_JNE | BPF_K: 1382 case BPF_JMP32 | BPF_JNE | BPF_K: 1383 case BPF_JMP | BPF_JSGT | BPF_K: 1384 case BPF_JMP32 | BPF_JSGT | BPF_K: 1385 case BPF_JMP | BPF_JSLT | BPF_K: 1386 case BPF_JMP32 | BPF_JSLT | BPF_K: 1387 case BPF_JMP | BPF_JSGE | BPF_K: 1388 case BPF_JMP32 | BPF_JSGE | BPF_K: 1389 case BPF_JMP | BPF_JSLE | BPF_K: 1390 case BPF_JMP32 | BPF_JSLE | BPF_K: 1391 rvoff = rv_offset(i, off, ctx); 1392 s = ctx->ninsns; 1393 if (imm) { 1394 emit_imm(RV_REG_T1, imm, ctx); 1395 rs = RV_REG_T1; 1396 } else { 1397 /* If imm is 0, simply use zero register. */ 1398 rs = RV_REG_ZERO; 1399 } 1400 if (!is64) { 1401 if (is_signed_bpf_cond(BPF_OP(code))) 1402 emit_sext_32_rd(&rd, ctx); 1403 else 1404 emit_zext_32_rd_t1(&rd, ctx); 1405 } 1406 e = ctx->ninsns; 1407 1408 /* Adjust for extra insns */ 1409 rvoff -= ninsns_rvoff(e - s); 1410 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1411 break; 1412 1413 case BPF_JMP | BPF_JSET | BPF_K: 1414 case BPF_JMP32 | BPF_JSET | BPF_K: 1415 rvoff = rv_offset(i, off, ctx); 1416 s = ctx->ninsns; 1417 if (is_12b_int(imm)) { 1418 emit_andi(RV_REG_T1, rd, imm, ctx); 1419 } else { 1420 emit_imm(RV_REG_T1, imm, ctx); 1421 emit_and(RV_REG_T1, rd, RV_REG_T1, ctx); 1422 } 1423 /* For jset32, we should clear the upper 32 bits of t1, but 1424 * sign-extension is sufficient here and saves one instruction, 1425 * as t1 is used only in comparison against zero. 1426 */ 1427 if (!is64 && imm < 0) 1428 emit_addiw(RV_REG_T1, RV_REG_T1, 0, ctx); 1429 e = ctx->ninsns; 1430 rvoff -= ninsns_rvoff(e - s); 1431 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); 1432 break; 1433 1434 /* function call */ 1435 case BPF_JMP | BPF_CALL: 1436 { 1437 bool fixed_addr; 1438 u64 addr; 1439 1440 mark_call(ctx); 1441 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1442 &addr, &fixed_addr); 1443 if (ret < 0) 1444 return ret; 1445 1446 ret = emit_call(addr, fixed_addr, ctx); 1447 if (ret) 1448 return ret; 1449 1450 emit_mv(bpf_to_rv_reg(BPF_REG_0, ctx), RV_REG_A0, ctx); 1451 break; 1452 } 1453 /* tail call */ 1454 case BPF_JMP | BPF_TAIL_CALL: 1455 if (emit_bpf_tail_call(i, ctx)) 1456 return -1; 1457 break; 1458 1459 /* function return */ 1460 case BPF_JMP | BPF_EXIT: 1461 if (i == ctx->prog->len - 1) 1462 break; 1463 1464 rvoff = epilogue_offset(ctx); 1465 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1466 if (ret) 1467 return ret; 1468 break; 1469 1470 /* dst = imm64 */ 1471 case BPF_LD | BPF_IMM | BPF_DW: 1472 { 1473 struct bpf_insn insn1 = insn[1]; 1474 u64 imm64; 1475 1476 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1477 if (bpf_pseudo_func(insn)) { 1478 /* fixed-length insns for extra jit pass */ 1479 ret = emit_addr(rd, imm64, extra_pass, ctx); 1480 if (ret) 1481 return ret; 1482 } else { 1483 emit_imm(rd, imm64, ctx); 1484 } 1485 1486 return 1; 1487 } 1488 1489 /* LDX: dst = *(size *)(src + off) */ 1490 case BPF_LDX | BPF_MEM | BPF_B: 1491 case BPF_LDX | BPF_MEM | BPF_H: 1492 case BPF_LDX | BPF_MEM | BPF_W: 1493 case BPF_LDX | BPF_MEM | BPF_DW: 1494 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1495 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1496 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1497 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1498 { 1499 int insn_len, insns_start; 1500 1501 switch (BPF_SIZE(code)) { 1502 case BPF_B: 1503 if (is_12b_int(off)) { 1504 insns_start = ctx->ninsns; 1505 emit(rv_lbu(rd, off, rs), ctx); 1506 insn_len = ctx->ninsns - insns_start; 1507 break; 1508 } 1509 1510 emit_imm(RV_REG_T1, off, ctx); 1511 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1512 insns_start = ctx->ninsns; 1513 emit(rv_lbu(rd, 0, RV_REG_T1), ctx); 1514 insn_len = ctx->ninsns - insns_start; 1515 if (insn_is_zext(&insn[1])) 1516 return 1; 1517 break; 1518 case BPF_H: 1519 if (is_12b_int(off)) { 1520 insns_start = ctx->ninsns; 1521 emit(rv_lhu(rd, off, rs), ctx); 1522 insn_len = ctx->ninsns - insns_start; 1523 break; 1524 } 1525 1526 emit_imm(RV_REG_T1, off, ctx); 1527 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1528 insns_start = ctx->ninsns; 1529 emit(rv_lhu(rd, 0, RV_REG_T1), ctx); 1530 insn_len = ctx->ninsns - insns_start; 1531 if (insn_is_zext(&insn[1])) 1532 return 1; 1533 break; 1534 case BPF_W: 1535 if (is_12b_int(off)) { 1536 insns_start = ctx->ninsns; 1537 emit(rv_lwu(rd, off, rs), ctx); 1538 insn_len = ctx->ninsns - insns_start; 1539 break; 1540 } 1541 1542 emit_imm(RV_REG_T1, off, ctx); 1543 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1544 insns_start = ctx->ninsns; 1545 emit(rv_lwu(rd, 0, RV_REG_T1), ctx); 1546 insn_len = ctx->ninsns - insns_start; 1547 if (insn_is_zext(&insn[1])) 1548 return 1; 1549 break; 1550 case BPF_DW: 1551 if (is_12b_int(off)) { 1552 insns_start = ctx->ninsns; 1553 emit_ld(rd, off, rs, ctx); 1554 insn_len = ctx->ninsns - insns_start; 1555 break; 1556 } 1557 1558 emit_imm(RV_REG_T1, off, ctx); 1559 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1560 insns_start = ctx->ninsns; 1561 emit_ld(rd, 0, RV_REG_T1, ctx); 1562 insn_len = ctx->ninsns - insns_start; 1563 break; 1564 } 1565 1566 ret = add_exception_handler(insn, ctx, rd, insn_len); 1567 if (ret) 1568 return ret; 1569 break; 1570 } 1571 /* speculation barrier */ 1572 case BPF_ST | BPF_NOSPEC: 1573 break; 1574 1575 /* ST: *(size *)(dst + off) = imm */ 1576 case BPF_ST | BPF_MEM | BPF_B: 1577 emit_imm(RV_REG_T1, imm, ctx); 1578 if (is_12b_int(off)) { 1579 emit(rv_sb(rd, off, RV_REG_T1), ctx); 1580 break; 1581 } 1582 1583 emit_imm(RV_REG_T2, off, ctx); 1584 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1585 emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx); 1586 break; 1587 1588 case BPF_ST | BPF_MEM | BPF_H: 1589 emit_imm(RV_REG_T1, imm, ctx); 1590 if (is_12b_int(off)) { 1591 emit(rv_sh(rd, off, RV_REG_T1), ctx); 1592 break; 1593 } 1594 1595 emit_imm(RV_REG_T2, off, ctx); 1596 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1597 emit(rv_sh(RV_REG_T2, 0, RV_REG_T1), ctx); 1598 break; 1599 case BPF_ST | BPF_MEM | BPF_W: 1600 emit_imm(RV_REG_T1, imm, ctx); 1601 if (is_12b_int(off)) { 1602 emit_sw(rd, off, RV_REG_T1, ctx); 1603 break; 1604 } 1605 1606 emit_imm(RV_REG_T2, off, ctx); 1607 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1608 emit_sw(RV_REG_T2, 0, RV_REG_T1, ctx); 1609 break; 1610 case BPF_ST | BPF_MEM | BPF_DW: 1611 emit_imm(RV_REG_T1, imm, ctx); 1612 if (is_12b_int(off)) { 1613 emit_sd(rd, off, RV_REG_T1, ctx); 1614 break; 1615 } 1616 1617 emit_imm(RV_REG_T2, off, ctx); 1618 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1619 emit_sd(RV_REG_T2, 0, RV_REG_T1, ctx); 1620 break; 1621 1622 /* STX: *(size *)(dst + off) = src */ 1623 case BPF_STX | BPF_MEM | BPF_B: 1624 if (is_12b_int(off)) { 1625 emit(rv_sb(rd, off, rs), ctx); 1626 break; 1627 } 1628 1629 emit_imm(RV_REG_T1, off, ctx); 1630 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1631 emit(rv_sb(RV_REG_T1, 0, rs), ctx); 1632 break; 1633 case BPF_STX | BPF_MEM | BPF_H: 1634 if (is_12b_int(off)) { 1635 emit(rv_sh(rd, off, rs), ctx); 1636 break; 1637 } 1638 1639 emit_imm(RV_REG_T1, off, ctx); 1640 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1641 emit(rv_sh(RV_REG_T1, 0, rs), ctx); 1642 break; 1643 case BPF_STX | BPF_MEM | BPF_W: 1644 if (is_12b_int(off)) { 1645 emit_sw(rd, off, rs, ctx); 1646 break; 1647 } 1648 1649 emit_imm(RV_REG_T1, off, ctx); 1650 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1651 emit_sw(RV_REG_T1, 0, rs, ctx); 1652 break; 1653 case BPF_STX | BPF_MEM | BPF_DW: 1654 if (is_12b_int(off)) { 1655 emit_sd(rd, off, rs, ctx); 1656 break; 1657 } 1658 1659 emit_imm(RV_REG_T1, off, ctx); 1660 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1661 emit_sd(RV_REG_T1, 0, rs, ctx); 1662 break; 1663 case BPF_STX | BPF_ATOMIC | BPF_W: 1664 case BPF_STX | BPF_ATOMIC | BPF_DW: 1665 emit_atomic(rd, rs, off, imm, 1666 BPF_SIZE(code) == BPF_DW, ctx); 1667 break; 1668 default: 1669 pr_err("bpf-jit: unknown opcode %02x\n", code); 1670 return -EINVAL; 1671 } 1672 1673 return 0; 1674 } 1675 1676 void bpf_jit_build_prologue(struct rv_jit_context *ctx) 1677 { 1678 int i, stack_adjust = 0, store_offset, bpf_stack_adjust; 1679 1680 bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, 16); 1681 if (bpf_stack_adjust) 1682 mark_fp(ctx); 1683 1684 if (seen_reg(RV_REG_RA, ctx)) 1685 stack_adjust += 8; 1686 stack_adjust += 8; /* RV_REG_FP */ 1687 if (seen_reg(RV_REG_S1, ctx)) 1688 stack_adjust += 8; 1689 if (seen_reg(RV_REG_S2, ctx)) 1690 stack_adjust += 8; 1691 if (seen_reg(RV_REG_S3, ctx)) 1692 stack_adjust += 8; 1693 if (seen_reg(RV_REG_S4, ctx)) 1694 stack_adjust += 8; 1695 if (seen_reg(RV_REG_S5, ctx)) 1696 stack_adjust += 8; 1697 if (seen_reg(RV_REG_S6, ctx)) 1698 stack_adjust += 8; 1699 1700 stack_adjust = round_up(stack_adjust, 16); 1701 stack_adjust += bpf_stack_adjust; 1702 1703 store_offset = stack_adjust - 8; 1704 1705 /* nops reserved for auipc+jalr pair */ 1706 for (i = 0; i < RV_FENTRY_NINSNS; i++) 1707 emit(rv_nop(), ctx); 1708 1709 /* First instruction is always setting the tail-call-counter 1710 * (TCC) register. This instruction is skipped for tail calls. 1711 * Force using a 4-byte (non-compressed) instruction. 1712 */ 1713 emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx); 1714 1715 emit_addi(RV_REG_SP, RV_REG_SP, -stack_adjust, ctx); 1716 1717 if (seen_reg(RV_REG_RA, ctx)) { 1718 emit_sd(RV_REG_SP, store_offset, RV_REG_RA, ctx); 1719 store_offset -= 8; 1720 } 1721 emit_sd(RV_REG_SP, store_offset, RV_REG_FP, ctx); 1722 store_offset -= 8; 1723 if (seen_reg(RV_REG_S1, ctx)) { 1724 emit_sd(RV_REG_SP, store_offset, RV_REG_S1, ctx); 1725 store_offset -= 8; 1726 } 1727 if (seen_reg(RV_REG_S2, ctx)) { 1728 emit_sd(RV_REG_SP, store_offset, RV_REG_S2, ctx); 1729 store_offset -= 8; 1730 } 1731 if (seen_reg(RV_REG_S3, ctx)) { 1732 emit_sd(RV_REG_SP, store_offset, RV_REG_S3, ctx); 1733 store_offset -= 8; 1734 } 1735 if (seen_reg(RV_REG_S4, ctx)) { 1736 emit_sd(RV_REG_SP, store_offset, RV_REG_S4, ctx); 1737 store_offset -= 8; 1738 } 1739 if (seen_reg(RV_REG_S5, ctx)) { 1740 emit_sd(RV_REG_SP, store_offset, RV_REG_S5, ctx); 1741 store_offset -= 8; 1742 } 1743 if (seen_reg(RV_REG_S6, ctx)) { 1744 emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx); 1745 store_offset -= 8; 1746 } 1747 1748 emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx); 1749 1750 if (bpf_stack_adjust) 1751 emit_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust, ctx); 1752 1753 /* Program contains calls and tail calls, so RV_REG_TCC need 1754 * to be saved across calls. 1755 */ 1756 if (seen_tail_call(ctx) && seen_call(ctx)) 1757 emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx); 1758 1759 ctx->stack_size = stack_adjust; 1760 } 1761 1762 void bpf_jit_build_epilogue(struct rv_jit_context *ctx) 1763 { 1764 __build_epilogue(false, ctx); 1765 } 1766 1767 bool bpf_jit_supports_kfunc_call(void) 1768 { 1769 return true; 1770 } 1771