xref: /openbmc/linux/arch/riscv/kvm/mmu.c (revision ca2478a7d974f38d29d27acb42a952c7f168916e)
199cdc6c1SAnup Patel // SPDX-License-Identifier: GPL-2.0
299cdc6c1SAnup Patel /*
399cdc6c1SAnup Patel  * Copyright (C) 2019 Western Digital Corporation or its affiliates.
499cdc6c1SAnup Patel  *
599cdc6c1SAnup Patel  * Authors:
699cdc6c1SAnup Patel  *     Anup Patel <anup.patel@wdc.com>
799cdc6c1SAnup Patel  */
899cdc6c1SAnup Patel 
999cdc6c1SAnup Patel #include <linux/bitops.h>
1099cdc6c1SAnup Patel #include <linux/errno.h>
1199cdc6c1SAnup Patel #include <linux/err.h>
1299cdc6c1SAnup Patel #include <linux/hugetlb.h>
1399cdc6c1SAnup Patel #include <linux/module.h>
1499cdc6c1SAnup Patel #include <linux/uaccess.h>
1599cdc6c1SAnup Patel #include <linux/vmalloc.h>
1699cdc6c1SAnup Patel #include <linux/kvm_host.h>
1799cdc6c1SAnup Patel #include <linux/sched/signal.h>
189d05c1feSAnup Patel #include <asm/csr.h>
1999cdc6c1SAnup Patel #include <asm/page.h>
2099cdc6c1SAnup Patel #include <asm/pgtable.h>
219d05c1feSAnup Patel 
229d05c1feSAnup Patel #ifdef CONFIG_64BIT
2345b66dc1SSean Christopherson static unsigned long gstage_mode __ro_after_init = (HGATP_MODE_SV39X4 << HGATP_MODE_SHIFT);
2445b66dc1SSean Christopherson static unsigned long gstage_pgd_levels __ro_after_init = 3;
2526708234SAnup Patel #define gstage_index_bits	9
269d05c1feSAnup Patel #else
2745b66dc1SSean Christopherson static unsigned long gstage_mode __ro_after_init = (HGATP_MODE_SV32X4 << HGATP_MODE_SHIFT);
2845b66dc1SSean Christopherson static unsigned long gstage_pgd_levels __ro_after_init = 2;
2926708234SAnup Patel #define gstage_index_bits	10
309d05c1feSAnup Patel #endif
319d05c1feSAnup Patel 
3226708234SAnup Patel #define gstage_pgd_xbits	2
3326708234SAnup Patel #define gstage_pgd_size	(1UL << (HGATP_PAGE_SHIFT + gstage_pgd_xbits))
3426708234SAnup Patel #define gstage_gpa_bits	(HGATP_PAGE_SHIFT + \
3526708234SAnup Patel 			 (gstage_pgd_levels * gstage_index_bits) + \
3626708234SAnup Patel 			 gstage_pgd_xbits)
3726708234SAnup Patel #define gstage_gpa_size	((gpa_t)(1ULL << gstage_gpa_bits))
389d05c1feSAnup Patel 
3926708234SAnup Patel #define gstage_pte_leaf(__ptep)	\
409d05c1feSAnup Patel 	(pte_val(*(__ptep)) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC))
419d05c1feSAnup Patel 
gstage_pte_index(gpa_t addr,u32 level)4226708234SAnup Patel static inline unsigned long gstage_pte_index(gpa_t addr, u32 level)
439d05c1feSAnup Patel {
449d05c1feSAnup Patel 	unsigned long mask;
4526708234SAnup Patel 	unsigned long shift = HGATP_PAGE_SHIFT + (gstage_index_bits * level);
469d05c1feSAnup Patel 
4726708234SAnup Patel 	if (level == (gstage_pgd_levels - 1))
4826708234SAnup Patel 		mask = (PTRS_PER_PTE * (1UL << gstage_pgd_xbits)) - 1;
499d05c1feSAnup Patel 	else
509d05c1feSAnup Patel 		mask = PTRS_PER_PTE - 1;
519d05c1feSAnup Patel 
529d05c1feSAnup Patel 	return (addr >> shift) & mask;
539d05c1feSAnup Patel }
549d05c1feSAnup Patel 
gstage_pte_page_vaddr(pte_t pte)5526708234SAnup Patel static inline unsigned long gstage_pte_page_vaddr(pte_t pte)
569d05c1feSAnup Patel {
5788573389SAlexandre Ghiti 	return (unsigned long)pfn_to_virt(__page_val_to_pfn(pte_val(pte)));
589d05c1feSAnup Patel }
599d05c1feSAnup Patel 
gstage_page_size_to_level(unsigned long page_size,u32 * out_level)6026708234SAnup Patel static int gstage_page_size_to_level(unsigned long page_size, u32 *out_level)
619d05c1feSAnup Patel {
629d05c1feSAnup Patel 	u32 i;
639d05c1feSAnup Patel 	unsigned long psz = 1UL << 12;
649d05c1feSAnup Patel 
6526708234SAnup Patel 	for (i = 0; i < gstage_pgd_levels; i++) {
6626708234SAnup Patel 		if (page_size == (psz << (i * gstage_index_bits))) {
679d05c1feSAnup Patel 			*out_level = i;
689d05c1feSAnup Patel 			return 0;
699d05c1feSAnup Patel 		}
709d05c1feSAnup Patel 	}
719d05c1feSAnup Patel 
729d05c1feSAnup Patel 	return -EINVAL;
739d05c1feSAnup Patel }
749d05c1feSAnup Patel 
gstage_level_to_page_order(u32 level,unsigned long * out_pgorder)7513acfec2SAnup Patel static int gstage_level_to_page_order(u32 level, unsigned long *out_pgorder)
769d05c1feSAnup Patel {
7726708234SAnup Patel 	if (gstage_pgd_levels < level)
789d05c1feSAnup Patel 		return -EINVAL;
799d05c1feSAnup Patel 
8013acfec2SAnup Patel 	*out_pgorder = 12 + (level * gstage_index_bits);
8113acfec2SAnup Patel 	return 0;
8213acfec2SAnup Patel }
839d05c1feSAnup Patel 
gstage_level_to_page_size(u32 level,unsigned long * out_pgsize)8413acfec2SAnup Patel static int gstage_level_to_page_size(u32 level, unsigned long *out_pgsize)
8513acfec2SAnup Patel {
8613acfec2SAnup Patel 	int rc;
8713acfec2SAnup Patel 	unsigned long page_order = PAGE_SHIFT;
8813acfec2SAnup Patel 
8913acfec2SAnup Patel 	rc = gstage_level_to_page_order(level, &page_order);
9013acfec2SAnup Patel 	if (rc)
9113acfec2SAnup Patel 		return rc;
9213acfec2SAnup Patel 
9313acfec2SAnup Patel 	*out_pgsize = BIT(page_order);
949d05c1feSAnup Patel 	return 0;
959d05c1feSAnup Patel }
969d05c1feSAnup Patel 
gstage_get_leaf_entry(struct kvm * kvm,gpa_t addr,pte_t ** ptepp,u32 * ptep_level)9726708234SAnup Patel static bool gstage_get_leaf_entry(struct kvm *kvm, gpa_t addr,
989d05c1feSAnup Patel 				  pte_t **ptepp, u32 *ptep_level)
999d05c1feSAnup Patel {
1009d05c1feSAnup Patel 	pte_t *ptep;
10126708234SAnup Patel 	u32 current_level = gstage_pgd_levels - 1;
1029d05c1feSAnup Patel 
1039d05c1feSAnup Patel 	*ptep_level = current_level;
1049d05c1feSAnup Patel 	ptep = (pte_t *)kvm->arch.pgd;
10526708234SAnup Patel 	ptep = &ptep[gstage_pte_index(addr, current_level)];
106*e0316069SAlexandre Ghiti 	while (ptep && pte_val(ptep_get(ptep))) {
10726708234SAnup Patel 		if (gstage_pte_leaf(ptep)) {
1089d05c1feSAnup Patel 			*ptep_level = current_level;
1099d05c1feSAnup Patel 			*ptepp = ptep;
1109d05c1feSAnup Patel 			return true;
1119d05c1feSAnup Patel 		}
1129d05c1feSAnup Patel 
1139d05c1feSAnup Patel 		if (current_level) {
1149d05c1feSAnup Patel 			current_level--;
1159d05c1feSAnup Patel 			*ptep_level = current_level;
116*e0316069SAlexandre Ghiti 			ptep = (pte_t *)gstage_pte_page_vaddr(ptep_get(ptep));
11726708234SAnup Patel 			ptep = &ptep[gstage_pte_index(addr, current_level)];
1189d05c1feSAnup Patel 		} else {
1199d05c1feSAnup Patel 			ptep = NULL;
1209d05c1feSAnup Patel 		}
1219d05c1feSAnup Patel 	}
1229d05c1feSAnup Patel 
1239d05c1feSAnup Patel 	return false;
1249d05c1feSAnup Patel }
1259d05c1feSAnup Patel 
gstage_remote_tlb_flush(struct kvm * kvm,u32 level,gpa_t addr)12626708234SAnup Patel static void gstage_remote_tlb_flush(struct kvm *kvm, u32 level, gpa_t addr)
1279d05c1feSAnup Patel {
12813acfec2SAnup Patel 	unsigned long order = PAGE_SHIFT;
1299d05c1feSAnup Patel 
13013acfec2SAnup Patel 	if (gstage_level_to_page_order(level, &order))
1319d05c1feSAnup Patel 		return;
13213acfec2SAnup Patel 	addr &= ~(BIT(order) - 1);
1339d05c1feSAnup Patel 
13413acfec2SAnup Patel 	kvm_riscv_hfence_gvma_vmid_gpa(kvm, -1UL, 0, addr, BIT(order), order);
1359d05c1feSAnup Patel }
1369d05c1feSAnup Patel 
gstage_set_pte(struct kvm * kvm,u32 level,struct kvm_mmu_memory_cache * pcache,gpa_t addr,const pte_t * new_pte)13726708234SAnup Patel static int gstage_set_pte(struct kvm *kvm, u32 level,
138cc4f602bSSean Christopherson 			   struct kvm_mmu_memory_cache *pcache,
1399d05c1feSAnup Patel 			   gpa_t addr, const pte_t *new_pte)
1409d05c1feSAnup Patel {
14126708234SAnup Patel 	u32 current_level = gstage_pgd_levels - 1;
1429d05c1feSAnup Patel 	pte_t *next_ptep = (pte_t *)kvm->arch.pgd;
14326708234SAnup Patel 	pte_t *ptep = &next_ptep[gstage_pte_index(addr, current_level)];
1449d05c1feSAnup Patel 
1459d05c1feSAnup Patel 	if (current_level < level)
1469d05c1feSAnup Patel 		return -EINVAL;
1479d05c1feSAnup Patel 
1489d05c1feSAnup Patel 	while (current_level != level) {
14926708234SAnup Patel 		if (gstage_pte_leaf(ptep))
1509d05c1feSAnup Patel 			return -EEXIST;
1519d05c1feSAnup Patel 
152*e0316069SAlexandre Ghiti 		if (!pte_val(ptep_get(ptep))) {
153cc4f602bSSean Christopherson 			if (!pcache)
154cc4f602bSSean Christopherson 				return -ENOMEM;
155cc4f602bSSean Christopherson 			next_ptep = kvm_mmu_memory_cache_alloc(pcache);
1569d05c1feSAnup Patel 			if (!next_ptep)
1579d05c1feSAnup Patel 				return -ENOMEM;
158*e0316069SAlexandre Ghiti 			set_pte(ptep, pfn_pte(PFN_DOWN(__pa(next_ptep)),
159*e0316069SAlexandre Ghiti 					      __pgprot(_PAGE_TABLE)));
1609d05c1feSAnup Patel 		} else {
16126708234SAnup Patel 			if (gstage_pte_leaf(ptep))
1629d05c1feSAnup Patel 				return -EEXIST;
163*e0316069SAlexandre Ghiti 			next_ptep = (pte_t *)gstage_pte_page_vaddr(ptep_get(ptep));
1649d05c1feSAnup Patel 		}
1659d05c1feSAnup Patel 
1669d05c1feSAnup Patel 		current_level--;
16726708234SAnup Patel 		ptep = &next_ptep[gstage_pte_index(addr, current_level)];
1689d05c1feSAnup Patel 	}
1699d05c1feSAnup Patel 
170*e0316069SAlexandre Ghiti 	set_pte(ptep, *new_pte);
17126708234SAnup Patel 	if (gstage_pte_leaf(ptep))
17226708234SAnup Patel 		gstage_remote_tlb_flush(kvm, current_level, addr);
1739d05c1feSAnup Patel 
1749d05c1feSAnup Patel 	return 0;
1759d05c1feSAnup Patel }
1769d05c1feSAnup Patel 
gstage_map_page(struct kvm * kvm,struct kvm_mmu_memory_cache * pcache,gpa_t gpa,phys_addr_t hpa,unsigned long page_size,bool page_rdonly,bool page_exec)17726708234SAnup Patel static int gstage_map_page(struct kvm *kvm,
178cc4f602bSSean Christopherson 			   struct kvm_mmu_memory_cache *pcache,
1799d05c1feSAnup Patel 			   gpa_t gpa, phys_addr_t hpa,
1809d05c1feSAnup Patel 			   unsigned long page_size,
1819d05c1feSAnup Patel 			   bool page_rdonly, bool page_exec)
1829d05c1feSAnup Patel {
1839d05c1feSAnup Patel 	int ret;
1849d05c1feSAnup Patel 	u32 level = 0;
1859d05c1feSAnup Patel 	pte_t new_pte;
1869d05c1feSAnup Patel 	pgprot_t prot;
1879d05c1feSAnup Patel 
18826708234SAnup Patel 	ret = gstage_page_size_to_level(page_size, &level);
1899d05c1feSAnup Patel 	if (ret)
1909d05c1feSAnup Patel 		return ret;
1919d05c1feSAnup Patel 
1929d05c1feSAnup Patel 	/*
1939d05c1feSAnup Patel 	 * A RISC-V implementation can choose to either:
1949d05c1feSAnup Patel 	 * 1) Update 'A' and 'D' PTE bits in hardware
1959d05c1feSAnup Patel 	 * 2) Generate page fault when 'A' and/or 'D' bits are not set
1969d05c1feSAnup Patel 	 *    PTE so that software can update these bits.
1979d05c1feSAnup Patel 	 *
1989d05c1feSAnup Patel 	 * We support both options mentioned above. To achieve this, we
19926708234SAnup Patel 	 * always set 'A' and 'D' PTE bits at time of creating G-stage
2009d05c1feSAnup Patel 	 * mapping. To support KVM dirty page logging with both options
20126708234SAnup Patel 	 * mentioned above, we will write-protect G-stage PTEs to track
2029d05c1feSAnup Patel 	 * dirty pages.
2039d05c1feSAnup Patel 	 */
2049d05c1feSAnup Patel 
2059d05c1feSAnup Patel 	if (page_exec) {
2069d05c1feSAnup Patel 		if (page_rdonly)
2079d05c1feSAnup Patel 			prot = PAGE_READ_EXEC;
2089d05c1feSAnup Patel 		else
2099d05c1feSAnup Patel 			prot = PAGE_WRITE_EXEC;
2109d05c1feSAnup Patel 	} else {
2119d05c1feSAnup Patel 		if (page_rdonly)
2129d05c1feSAnup Patel 			prot = PAGE_READ;
2139d05c1feSAnup Patel 		else
2149d05c1feSAnup Patel 			prot = PAGE_WRITE;
2159d05c1feSAnup Patel 	}
2169d05c1feSAnup Patel 	new_pte = pfn_pte(PFN_DOWN(hpa), prot);
2179d05c1feSAnup Patel 	new_pte = pte_mkdirty(new_pte);
2189d05c1feSAnup Patel 
21926708234SAnup Patel 	return gstage_set_pte(kvm, level, pcache, gpa, &new_pte);
2209d05c1feSAnup Patel }
2219d05c1feSAnup Patel 
22226708234SAnup Patel enum gstage_op {
22326708234SAnup Patel 	GSTAGE_OP_NOP = 0,	/* Nothing */
22426708234SAnup Patel 	GSTAGE_OP_CLEAR,	/* Clear/Unmap */
22526708234SAnup Patel 	GSTAGE_OP_WP,		/* Write-protect */
2269d05c1feSAnup Patel };
2279d05c1feSAnup Patel 
gstage_op_pte(struct kvm * kvm,gpa_t addr,pte_t * ptep,u32 ptep_level,enum gstage_op op)22826708234SAnup Patel static void gstage_op_pte(struct kvm *kvm, gpa_t addr,
22926708234SAnup Patel 			  pte_t *ptep, u32 ptep_level, enum gstage_op op)
2309d05c1feSAnup Patel {
2319d05c1feSAnup Patel 	int i, ret;
2329d05c1feSAnup Patel 	pte_t *next_ptep;
2339d05c1feSAnup Patel 	u32 next_ptep_level;
2349d05c1feSAnup Patel 	unsigned long next_page_size, page_size;
2359d05c1feSAnup Patel 
23626708234SAnup Patel 	ret = gstage_level_to_page_size(ptep_level, &page_size);
2379d05c1feSAnup Patel 	if (ret)
2389d05c1feSAnup Patel 		return;
2399d05c1feSAnup Patel 
2409d05c1feSAnup Patel 	BUG_ON(addr & (page_size - 1));
2419d05c1feSAnup Patel 
242*e0316069SAlexandre Ghiti 	if (!pte_val(ptep_get(ptep)))
2439d05c1feSAnup Patel 		return;
2449d05c1feSAnup Patel 
24526708234SAnup Patel 	if (ptep_level && !gstage_pte_leaf(ptep)) {
246*e0316069SAlexandre Ghiti 		next_ptep = (pte_t *)gstage_pte_page_vaddr(ptep_get(ptep));
2479d05c1feSAnup Patel 		next_ptep_level = ptep_level - 1;
24826708234SAnup Patel 		ret = gstage_level_to_page_size(next_ptep_level,
2499d05c1feSAnup Patel 						&next_page_size);
2509d05c1feSAnup Patel 		if (ret)
2519d05c1feSAnup Patel 			return;
2529d05c1feSAnup Patel 
25326708234SAnup Patel 		if (op == GSTAGE_OP_CLEAR)
2549d05c1feSAnup Patel 			set_pte(ptep, __pte(0));
2559d05c1feSAnup Patel 		for (i = 0; i < PTRS_PER_PTE; i++)
25626708234SAnup Patel 			gstage_op_pte(kvm, addr + i * next_page_size,
2579d05c1feSAnup Patel 					&next_ptep[i], next_ptep_level, op);
25826708234SAnup Patel 		if (op == GSTAGE_OP_CLEAR)
2599d05c1feSAnup Patel 			put_page(virt_to_page(next_ptep));
2609d05c1feSAnup Patel 	} else {
26126708234SAnup Patel 		if (op == GSTAGE_OP_CLEAR)
2629d05c1feSAnup Patel 			set_pte(ptep, __pte(0));
26326708234SAnup Patel 		else if (op == GSTAGE_OP_WP)
264*e0316069SAlexandre Ghiti 			set_pte(ptep, __pte(pte_val(ptep_get(ptep)) & ~_PAGE_WRITE));
26526708234SAnup Patel 		gstage_remote_tlb_flush(kvm, ptep_level, addr);
2669d05c1feSAnup Patel 	}
2679d05c1feSAnup Patel }
2689d05c1feSAnup Patel 
gstage_unmap_range(struct kvm * kvm,gpa_t start,gpa_t size,bool may_block)26926708234SAnup Patel static void gstage_unmap_range(struct kvm *kvm, gpa_t start,
2709955371cSAnup Patel 			       gpa_t size, bool may_block)
2719d05c1feSAnup Patel {
2729d05c1feSAnup Patel 	int ret;
2739d05c1feSAnup Patel 	pte_t *ptep;
2749d05c1feSAnup Patel 	u32 ptep_level;
2759d05c1feSAnup Patel 	bool found_leaf;
2769d05c1feSAnup Patel 	unsigned long page_size;
2779d05c1feSAnup Patel 	gpa_t addr = start, end = start + size;
2789d05c1feSAnup Patel 
2799d05c1feSAnup Patel 	while (addr < end) {
28026708234SAnup Patel 		found_leaf = gstage_get_leaf_entry(kvm, addr,
2819d05c1feSAnup Patel 						   &ptep, &ptep_level);
28226708234SAnup Patel 		ret = gstage_level_to_page_size(ptep_level, &page_size);
2839d05c1feSAnup Patel 		if (ret)
2849d05c1feSAnup Patel 			break;
2859d05c1feSAnup Patel 
2869d05c1feSAnup Patel 		if (!found_leaf)
2879d05c1feSAnup Patel 			goto next;
2889d05c1feSAnup Patel 
2899d05c1feSAnup Patel 		if (!(addr & (page_size - 1)) && ((end - addr) >= page_size))
29026708234SAnup Patel 			gstage_op_pte(kvm, addr, ptep,
29126708234SAnup Patel 				      ptep_level, GSTAGE_OP_CLEAR);
2929d05c1feSAnup Patel 
2939d05c1feSAnup Patel next:
2949d05c1feSAnup Patel 		addr += page_size;
2959955371cSAnup Patel 
2969955371cSAnup Patel 		/*
2979955371cSAnup Patel 		 * If the range is too large, release the kvm->mmu_lock
2989955371cSAnup Patel 		 * to prevent starvation and lockup detector warnings.
2999955371cSAnup Patel 		 */
3009955371cSAnup Patel 		if (may_block && addr < end)
3019955371cSAnup Patel 			cond_resched_lock(&kvm->mmu_lock);
3029d05c1feSAnup Patel 	}
3039d05c1feSAnup Patel }
3049d05c1feSAnup Patel 
gstage_wp_range(struct kvm * kvm,gpa_t start,gpa_t end)30526708234SAnup Patel static void gstage_wp_range(struct kvm *kvm, gpa_t start, gpa_t end)
3069d05c1feSAnup Patel {
3079d05c1feSAnup Patel 	int ret;
3089d05c1feSAnup Patel 	pte_t *ptep;
3099d05c1feSAnup Patel 	u32 ptep_level;
3109d05c1feSAnup Patel 	bool found_leaf;
3119d05c1feSAnup Patel 	gpa_t addr = start;
3129d05c1feSAnup Patel 	unsigned long page_size;
3139d05c1feSAnup Patel 
3149d05c1feSAnup Patel 	while (addr < end) {
31526708234SAnup Patel 		found_leaf = gstage_get_leaf_entry(kvm, addr,
3169d05c1feSAnup Patel 						   &ptep, &ptep_level);
31726708234SAnup Patel 		ret = gstage_level_to_page_size(ptep_level, &page_size);
3189d05c1feSAnup Patel 		if (ret)
3199d05c1feSAnup Patel 			break;
3209d05c1feSAnup Patel 
3219d05c1feSAnup Patel 		if (!found_leaf)
3229d05c1feSAnup Patel 			goto next;
3239d05c1feSAnup Patel 
3249d05c1feSAnup Patel 		if (!(addr & (page_size - 1)) && ((end - addr) >= page_size))
32526708234SAnup Patel 			gstage_op_pte(kvm, addr, ptep,
32626708234SAnup Patel 				      ptep_level, GSTAGE_OP_WP);
3279d05c1feSAnup Patel 
3289d05c1feSAnup Patel next:
3299d05c1feSAnup Patel 		addr += page_size;
3309d05c1feSAnup Patel 	}
3319d05c1feSAnup Patel }
3329d05c1feSAnup Patel 
gstage_wp_memory_region(struct kvm * kvm,int slot)33326708234SAnup Patel static void gstage_wp_memory_region(struct kvm *kvm, int slot)
3349d05c1feSAnup Patel {
3359d05c1feSAnup Patel 	struct kvm_memslots *slots = kvm_memslots(kvm);
3369d05c1feSAnup Patel 	struct kvm_memory_slot *memslot = id_to_memslot(slots, slot);
3379d05c1feSAnup Patel 	phys_addr_t start = memslot->base_gfn << PAGE_SHIFT;
3389d05c1feSAnup Patel 	phys_addr_t end = (memslot->base_gfn + memslot->npages) << PAGE_SHIFT;
3399d05c1feSAnup Patel 
3409d05c1feSAnup Patel 	spin_lock(&kvm->mmu_lock);
34126708234SAnup Patel 	gstage_wp_range(kvm, start, end);
3429d05c1feSAnup Patel 	spin_unlock(&kvm->mmu_lock);
3439d05c1feSAnup Patel 	kvm_flush_remote_tlbs(kvm);
3449d05c1feSAnup Patel }
3459d05c1feSAnup Patel 
kvm_riscv_gstage_ioremap(struct kvm * kvm,gpa_t gpa,phys_addr_t hpa,unsigned long size,bool writable,bool in_atomic)346c9d57373SAnup Patel int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa,
347c9d57373SAnup Patel 			     phys_addr_t hpa, unsigned long size,
348c9d57373SAnup Patel 			     bool writable, bool in_atomic)
3499d05c1feSAnup Patel {
3509d05c1feSAnup Patel 	pte_t pte;
3519d05c1feSAnup Patel 	int ret = 0;
3529d05c1feSAnup Patel 	unsigned long pfn;
3539d05c1feSAnup Patel 	phys_addr_t addr, end;
35463f4b210SPaolo Bonzini 	struct kvm_mmu_memory_cache pcache = {
35563f4b210SPaolo Bonzini 		.gfp_custom = (in_atomic) ? GFP_ATOMIC | __GFP_ACCOUNT : 0,
35663f4b210SPaolo Bonzini 		.gfp_zero = __GFP_ZERO,
35763f4b210SPaolo Bonzini 	};
3589d05c1feSAnup Patel 
3599d05c1feSAnup Patel 	end = (gpa + size + PAGE_SIZE - 1) & PAGE_MASK;
3609d05c1feSAnup Patel 	pfn = __phys_to_pfn(hpa);
3619d05c1feSAnup Patel 
3629d05c1feSAnup Patel 	for (addr = gpa; addr < end; addr += PAGE_SIZE) {
363659ad6d8SAnup Patel 		pte = pfn_pte(pfn, PAGE_KERNEL_IO);
3649d05c1feSAnup Patel 
3659d05c1feSAnup Patel 		if (!writable)
3669d05c1feSAnup Patel 			pte = pte_wrprotect(pte);
3679d05c1feSAnup Patel 
36826708234SAnup Patel 		ret = kvm_mmu_topup_memory_cache(&pcache, gstage_pgd_levels);
3699d05c1feSAnup Patel 		if (ret)
3709d05c1feSAnup Patel 			goto out;
3719d05c1feSAnup Patel 
3729d05c1feSAnup Patel 		spin_lock(&kvm->mmu_lock);
37326708234SAnup Patel 		ret = gstage_set_pte(kvm, 0, &pcache, addr, &pte);
3749d05c1feSAnup Patel 		spin_unlock(&kvm->mmu_lock);
3759d05c1feSAnup Patel 		if (ret)
3769d05c1feSAnup Patel 			goto out;
3779d05c1feSAnup Patel 
3789d05c1feSAnup Patel 		pfn++;
3799d05c1feSAnup Patel 	}
3809d05c1feSAnup Patel 
3819d05c1feSAnup Patel out:
382cc4f602bSSean Christopherson 	kvm_mmu_free_memory_cache(&pcache);
3839d05c1feSAnup Patel 	return ret;
3849d05c1feSAnup Patel }
3859d05c1feSAnup Patel 
kvm_riscv_gstage_iounmap(struct kvm * kvm,gpa_t gpa,unsigned long size)386c9d57373SAnup Patel void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, unsigned long size)
387c9d57373SAnup Patel {
388c9d57373SAnup Patel 	spin_lock(&kvm->mmu_lock);
389c9d57373SAnup Patel 	gstage_unmap_range(kvm, gpa, size, false);
390c9d57373SAnup Patel 	spin_unlock(&kvm->mmu_lock);
391c9d57373SAnup Patel }
392c9d57373SAnup Patel 
kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm * kvm,struct kvm_memory_slot * slot,gfn_t gfn_offset,unsigned long mask)3939d05c1feSAnup Patel void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
3949d05c1feSAnup Patel 					     struct kvm_memory_slot *slot,
3959d05c1feSAnup Patel 					     gfn_t gfn_offset,
3969d05c1feSAnup Patel 					     unsigned long mask)
3979d05c1feSAnup Patel {
3989d05c1feSAnup Patel 	phys_addr_t base_gfn = slot->base_gfn + gfn_offset;
3999d05c1feSAnup Patel 	phys_addr_t start = (base_gfn +  __ffs(mask)) << PAGE_SHIFT;
4009d05c1feSAnup Patel 	phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT;
4019d05c1feSAnup Patel 
40226708234SAnup Patel 	gstage_wp_range(kvm, start, end);
4039d05c1feSAnup Patel }
40499cdc6c1SAnup Patel 
kvm_arch_sync_dirty_log(struct kvm * kvm,struct kvm_memory_slot * memslot)40599cdc6c1SAnup Patel void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
40699cdc6c1SAnup Patel {
40799cdc6c1SAnup Patel }
40899cdc6c1SAnup Patel 
kvm_arch_free_memslot(struct kvm * kvm,struct kvm_memory_slot * free)40999cdc6c1SAnup Patel void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free)
41099cdc6c1SAnup Patel {
41199cdc6c1SAnup Patel }
41299cdc6c1SAnup Patel 
kvm_arch_memslots_updated(struct kvm * kvm,u64 gen)41399cdc6c1SAnup Patel void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
41499cdc6c1SAnup Patel {
41599cdc6c1SAnup Patel }
41699cdc6c1SAnup Patel 
kvm_arch_flush_shadow_all(struct kvm * kvm)41799cdc6c1SAnup Patel void kvm_arch_flush_shadow_all(struct kvm *kvm)
41899cdc6c1SAnup Patel {
41926708234SAnup Patel 	kvm_riscv_gstage_free_pgd(kvm);
42099cdc6c1SAnup Patel }
42199cdc6c1SAnup Patel 
kvm_arch_flush_shadow_memslot(struct kvm * kvm,struct kvm_memory_slot * slot)42299cdc6c1SAnup Patel void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
42399cdc6c1SAnup Patel 				   struct kvm_memory_slot *slot)
42499cdc6c1SAnup Patel {
425756e1fc1SSean Christopherson 	gpa_t gpa = slot->base_gfn << PAGE_SHIFT;
426756e1fc1SSean Christopherson 	phys_addr_t size = slot->npages << PAGE_SHIFT;
427756e1fc1SSean Christopherson 
428756e1fc1SSean Christopherson 	spin_lock(&kvm->mmu_lock);
42926708234SAnup Patel 	gstage_unmap_range(kvm, gpa, size, false);
430756e1fc1SSean Christopherson 	spin_unlock(&kvm->mmu_lock);
43199cdc6c1SAnup Patel }
43299cdc6c1SAnup Patel 
kvm_arch_commit_memory_region(struct kvm * kvm,struct kvm_memory_slot * old,const struct kvm_memory_slot * new,enum kvm_mr_change change)43399cdc6c1SAnup Patel void kvm_arch_commit_memory_region(struct kvm *kvm,
43499cdc6c1SAnup Patel 				struct kvm_memory_slot *old,
43599cdc6c1SAnup Patel 				const struct kvm_memory_slot *new,
43699cdc6c1SAnup Patel 				enum kvm_mr_change change)
43799cdc6c1SAnup Patel {
4389d05c1feSAnup Patel 	/*
4399d05c1feSAnup Patel 	 * At this point memslot has been committed and there is an
4409d05c1feSAnup Patel 	 * allocated dirty_bitmap[], dirty pages will be tracked while
4419d05c1feSAnup Patel 	 * the memory slot is write protected.
4429d05c1feSAnup Patel 	 */
443d01495d4SSean Christopherson 	if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES)
44426708234SAnup Patel 		gstage_wp_memory_region(kvm, new->id);
44599cdc6c1SAnup Patel }
44699cdc6c1SAnup Patel 
kvm_arch_prepare_memory_region(struct kvm * kvm,const struct kvm_memory_slot * old,struct kvm_memory_slot * new,enum kvm_mr_change change)44799cdc6c1SAnup Patel int kvm_arch_prepare_memory_region(struct kvm *kvm,
448537a17b3SSean Christopherson 				const struct kvm_memory_slot *old,
449537a17b3SSean Christopherson 				struct kvm_memory_slot *new,
45099cdc6c1SAnup Patel 				enum kvm_mr_change change)
45199cdc6c1SAnup Patel {
452d01495d4SSean Christopherson 	hva_t hva, reg_end, size;
453d01495d4SSean Christopherson 	gpa_t base_gpa;
454d01495d4SSean Christopherson 	bool writable;
4559d05c1feSAnup Patel 	int ret = 0;
4569d05c1feSAnup Patel 
4579d05c1feSAnup Patel 	if (change != KVM_MR_CREATE && change != KVM_MR_MOVE &&
4589d05c1feSAnup Patel 			change != KVM_MR_FLAGS_ONLY)
45999cdc6c1SAnup Patel 		return 0;
4609d05c1feSAnup Patel 
4619d05c1feSAnup Patel 	/*
4629d05c1feSAnup Patel 	 * Prevent userspace from creating a memory region outside of the GPA
4639d05c1feSAnup Patel 	 * space addressable by the KVM guest GPA space.
4649d05c1feSAnup Patel 	 */
465537a17b3SSean Christopherson 	if ((new->base_gfn + new->npages) >=
46626708234SAnup Patel 	    (gstage_gpa_size >> PAGE_SHIFT))
4679d05c1feSAnup Patel 		return -EFAULT;
4689d05c1feSAnup Patel 
469d01495d4SSean Christopherson 	hva = new->userspace_addr;
470d01495d4SSean Christopherson 	size = new->npages << PAGE_SHIFT;
471d01495d4SSean Christopherson 	reg_end = hva + size;
472d01495d4SSean Christopherson 	base_gpa = new->base_gfn << PAGE_SHIFT;
473d01495d4SSean Christopherson 	writable = !(new->flags & KVM_MEM_READONLY);
474d01495d4SSean Christopherson 
4759d05c1feSAnup Patel 	mmap_read_lock(current->mm);
4769d05c1feSAnup Patel 
4779d05c1feSAnup Patel 	/*
4789d05c1feSAnup Patel 	 * A memory region could potentially cover multiple VMAs, and
4799d05c1feSAnup Patel 	 * any holes between them, so iterate over all of them to find
4809d05c1feSAnup Patel 	 * out if we can map any of them right now.
4819d05c1feSAnup Patel 	 *
4829d05c1feSAnup Patel 	 *     +--------------------------------------------+
4839d05c1feSAnup Patel 	 * +---------------+----------------+   +----------------+
4849d05c1feSAnup Patel 	 * |   : VMA 1     |      VMA 2     |   |    VMA 3  :    |
4859d05c1feSAnup Patel 	 * +---------------+----------------+   +----------------+
4869d05c1feSAnup Patel 	 *     |               memory region                |
4879d05c1feSAnup Patel 	 *     +--------------------------------------------+
4889d05c1feSAnup Patel 	 */
4899d05c1feSAnup Patel 	do {
4909d05c1feSAnup Patel 		struct vm_area_struct *vma = find_vma(current->mm, hva);
4919d05c1feSAnup Patel 		hva_t vm_start, vm_end;
4929d05c1feSAnup Patel 
4939d05c1feSAnup Patel 		if (!vma || vma->vm_start >= reg_end)
4949d05c1feSAnup Patel 			break;
4959d05c1feSAnup Patel 
4969d05c1feSAnup Patel 		/*
4979d05c1feSAnup Patel 		 * Mapping a read-only VMA is only allowed if the
4989d05c1feSAnup Patel 		 * memory region is configured as read-only.
4999d05c1feSAnup Patel 		 */
5009d05c1feSAnup Patel 		if (writable && !(vma->vm_flags & VM_WRITE)) {
5019d05c1feSAnup Patel 			ret = -EPERM;
5029d05c1feSAnup Patel 			break;
5039d05c1feSAnup Patel 		}
5049d05c1feSAnup Patel 
5059d05c1feSAnup Patel 		/* Take the intersection of this VMA with the memory region */
5069d05c1feSAnup Patel 		vm_start = max(hva, vma->vm_start);
5079d05c1feSAnup Patel 		vm_end = min(reg_end, vma->vm_end);
5089d05c1feSAnup Patel 
5099d05c1feSAnup Patel 		if (vma->vm_flags & VM_PFNMAP) {
510d01495d4SSean Christopherson 			gpa_t gpa = base_gpa + (vm_start - hva);
5119d05c1feSAnup Patel 			phys_addr_t pa;
5129d05c1feSAnup Patel 
5139d05c1feSAnup Patel 			pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
5149d05c1feSAnup Patel 			pa += vm_start - vma->vm_start;
5159d05c1feSAnup Patel 
5169d05c1feSAnup Patel 			/* IO region dirty page logging not allowed */
517537a17b3SSean Christopherson 			if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
5189d05c1feSAnup Patel 				ret = -EINVAL;
5199d05c1feSAnup Patel 				goto out;
5209d05c1feSAnup Patel 			}
5219d05c1feSAnup Patel 
522c9d57373SAnup Patel 			ret = kvm_riscv_gstage_ioremap(kvm, gpa, pa,
523c9d57373SAnup Patel 						       vm_end - vm_start,
524c9d57373SAnup Patel 						       writable, false);
5259d05c1feSAnup Patel 			if (ret)
5269d05c1feSAnup Patel 				break;
5279d05c1feSAnup Patel 		}
5289d05c1feSAnup Patel 		hva = vm_end;
5299d05c1feSAnup Patel 	} while (hva < reg_end);
5309d05c1feSAnup Patel 
5319d05c1feSAnup Patel 	if (change == KVM_MR_FLAGS_ONLY)
5329d05c1feSAnup Patel 		goto out;
5339d05c1feSAnup Patel 
5349d05c1feSAnup Patel 	if (ret)
5353e2d4756SChristophe JAILLET 		kvm_riscv_gstage_iounmap(kvm, base_gpa, size);
5369d05c1feSAnup Patel 
5379d05c1feSAnup Patel out:
5389d05c1feSAnup Patel 	mmap_read_unlock(current->mm);
5399d05c1feSAnup Patel 	return ret;
54099cdc6c1SAnup Patel }
54199cdc6c1SAnup Patel 
kvm_unmap_gfn_range(struct kvm * kvm,struct kvm_gfn_range * range)5429955371cSAnup Patel bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
5439955371cSAnup Patel {
5449955371cSAnup Patel 	if (!kvm->arch.pgd)
545bbd5ba8dSBixuan Cui 		return false;
5469955371cSAnup Patel 
54726708234SAnup Patel 	gstage_unmap_range(kvm, range->start << PAGE_SHIFT,
5489955371cSAnup Patel 			   (range->end - range->start) << PAGE_SHIFT,
5499955371cSAnup Patel 			   range->may_block);
550bbd5ba8dSBixuan Cui 	return false;
5519955371cSAnup Patel }
5529955371cSAnup Patel 
kvm_set_spte_gfn(struct kvm * kvm,struct kvm_gfn_range * range)5539955371cSAnup Patel bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
5549955371cSAnup Patel {
5559955371cSAnup Patel 	int ret;
5563e1efe2bSSean Christopherson 	kvm_pfn_t pfn = pte_pfn(range->arg.pte);
5579955371cSAnup Patel 
5589955371cSAnup Patel 	if (!kvm->arch.pgd)
559bbd5ba8dSBixuan Cui 		return false;
5609955371cSAnup Patel 
5619955371cSAnup Patel 	WARN_ON(range->end - range->start != 1);
5629955371cSAnup Patel 
56326708234SAnup Patel 	ret = gstage_map_page(kvm, NULL, range->start << PAGE_SHIFT,
5649955371cSAnup Patel 			      __pfn_to_phys(pfn), PAGE_SIZE, true, true);
5659955371cSAnup Patel 	if (ret) {
56626708234SAnup Patel 		kvm_debug("Failed to map G-stage page (error %d)\n", ret);
567bbd5ba8dSBixuan Cui 		return true;
5689955371cSAnup Patel 	}
5699955371cSAnup Patel 
570bbd5ba8dSBixuan Cui 	return false;
5719955371cSAnup Patel }
5729955371cSAnup Patel 
kvm_age_gfn(struct kvm * kvm,struct kvm_gfn_range * range)5739955371cSAnup Patel bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
5749955371cSAnup Patel {
5759955371cSAnup Patel 	pte_t *ptep;
5769955371cSAnup Patel 	u32 ptep_level = 0;
5779955371cSAnup Patel 	u64 size = (range->end - range->start) << PAGE_SHIFT;
5789955371cSAnup Patel 
5799955371cSAnup Patel 	if (!kvm->arch.pgd)
580bbd5ba8dSBixuan Cui 		return false;
5819955371cSAnup Patel 
582c25a6dddSAlexandre Ghiti 	WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE);
5839955371cSAnup Patel 
58426708234SAnup Patel 	if (!gstage_get_leaf_entry(kvm, range->start << PAGE_SHIFT,
5859955371cSAnup Patel 				   &ptep, &ptep_level))
586bbd5ba8dSBixuan Cui 		return false;
5879955371cSAnup Patel 
5889955371cSAnup Patel 	return ptep_test_and_clear_young(NULL, 0, ptep);
5899955371cSAnup Patel }
5909955371cSAnup Patel 
kvm_test_age_gfn(struct kvm * kvm,struct kvm_gfn_range * range)5919955371cSAnup Patel bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
5929955371cSAnup Patel {
5939955371cSAnup Patel 	pte_t *ptep;
5949955371cSAnup Patel 	u32 ptep_level = 0;
5959955371cSAnup Patel 	u64 size = (range->end - range->start) << PAGE_SHIFT;
5969955371cSAnup Patel 
5979955371cSAnup Patel 	if (!kvm->arch.pgd)
598bbd5ba8dSBixuan Cui 		return false;
5999955371cSAnup Patel 
600c25a6dddSAlexandre Ghiti 	WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE);
6019955371cSAnup Patel 
60226708234SAnup Patel 	if (!gstage_get_leaf_entry(kvm, range->start << PAGE_SHIFT,
6039955371cSAnup Patel 				   &ptep, &ptep_level))
604bbd5ba8dSBixuan Cui 		return false;
6059955371cSAnup Patel 
606*e0316069SAlexandre Ghiti 	return pte_young(ptep_get(ptep));
6079955371cSAnup Patel }
6089955371cSAnup Patel 
kvm_riscv_gstage_map(struct kvm_vcpu * vcpu,struct kvm_memory_slot * memslot,gpa_t gpa,unsigned long hva,bool is_write)60926708234SAnup Patel int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu,
6109f701326SAnup Patel 			 struct kvm_memory_slot *memslot,
6119f701326SAnup Patel 			 gpa_t gpa, unsigned long hva, bool is_write)
6129f701326SAnup Patel {
6139d05c1feSAnup Patel 	int ret;
6149d05c1feSAnup Patel 	kvm_pfn_t hfn;
6156259d2f8SZhang Jiaming 	bool writable;
6169d05c1feSAnup Patel 	short vma_pageshift;
6179d05c1feSAnup Patel 	gfn_t gfn = gpa >> PAGE_SHIFT;
6189d05c1feSAnup Patel 	struct vm_area_struct *vma;
6199d05c1feSAnup Patel 	struct kvm *kvm = vcpu->kvm;
620cc4f602bSSean Christopherson 	struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache;
6219d05c1feSAnup Patel 	bool logging = (memslot->dirty_bitmap &&
6229d05c1feSAnup Patel 			!(memslot->flags & KVM_MEM_READONLY)) ? true : false;
6239955371cSAnup Patel 	unsigned long vma_pagesize, mmu_seq;
6249d05c1feSAnup Patel 
6252ed90cb0SDavid Matlack 	/* We need minimum second+third level pages */
6262ed90cb0SDavid Matlack 	ret = kvm_mmu_topup_memory_cache(pcache, gstage_pgd_levels);
6272ed90cb0SDavid Matlack 	if (ret) {
6282ed90cb0SDavid Matlack 		kvm_err("Failed to topup G-stage cache\n");
6292ed90cb0SDavid Matlack 		return ret;
6302ed90cb0SDavid Matlack 	}
6312ed90cb0SDavid Matlack 
6329d05c1feSAnup Patel 	mmap_read_lock(current->mm);
6339d05c1feSAnup Patel 
634b3f2575aSBo Liu 	vma = vma_lookup(current->mm, hva);
6359d05c1feSAnup Patel 	if (unlikely(!vma)) {
6369d05c1feSAnup Patel 		kvm_err("Failed to find VMA for hva 0x%lx\n", hva);
6379d05c1feSAnup Patel 		mmap_read_unlock(current->mm);
6389d05c1feSAnup Patel 		return -EFAULT;
6399d05c1feSAnup Patel 	}
6409d05c1feSAnup Patel 
6419d05c1feSAnup Patel 	if (is_vm_hugetlb_page(vma))
6429d05c1feSAnup Patel 		vma_pageshift = huge_page_shift(hstate_vma(vma));
6439d05c1feSAnup Patel 	else
6449d05c1feSAnup Patel 		vma_pageshift = PAGE_SHIFT;
6459d05c1feSAnup Patel 	vma_pagesize = 1ULL << vma_pageshift;
6469d05c1feSAnup Patel 	if (logging || (vma->vm_flags & VM_PFNMAP))
6479d05c1feSAnup Patel 		vma_pagesize = PAGE_SIZE;
6489d05c1feSAnup Patel 
649c25a6dddSAlexandre Ghiti 	if (vma_pagesize == PMD_SIZE || vma_pagesize == PUD_SIZE)
6509d05c1feSAnup Patel 		gfn = (gpa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT;
6519d05c1feSAnup Patel 
6522ed90cb0SDavid Matlack 	/*
6532ed90cb0SDavid Matlack 	 * Read mmu_invalidate_seq so that KVM can detect if the results of
6542ed90cb0SDavid Matlack 	 * vma_lookup() or gfn_to_pfn_prot() become stale priort to acquiring
6552ed90cb0SDavid Matlack 	 * kvm->mmu_lock.
6562ed90cb0SDavid Matlack 	 *
6572ed90cb0SDavid Matlack 	 * Rely on mmap_read_unlock() for an implicit smp_rmb(), which pairs
6582ed90cb0SDavid Matlack 	 * with the smp_wmb() in kvm_mmu_invalidate_end().
6592ed90cb0SDavid Matlack 	 */
6602ed90cb0SDavid Matlack 	mmu_seq = kvm->mmu_invalidate_seq;
6619d05c1feSAnup Patel 	mmap_read_unlock(current->mm);
6629d05c1feSAnup Patel 
663c25a6dddSAlexandre Ghiti 	if (vma_pagesize != PUD_SIZE &&
6649d05c1feSAnup Patel 	    vma_pagesize != PMD_SIZE &&
6659d05c1feSAnup Patel 	    vma_pagesize != PAGE_SIZE) {
6669d05c1feSAnup Patel 		kvm_err("Invalid VMA page size 0x%lx\n", vma_pagesize);
6679d05c1feSAnup Patel 		return -EFAULT;
6689d05c1feSAnup Patel 	}
6699d05c1feSAnup Patel 
6706259d2f8SZhang Jiaming 	hfn = gfn_to_pfn_prot(kvm, gfn, is_write, &writable);
6719d05c1feSAnup Patel 	if (hfn == KVM_PFN_ERR_HWPOISON) {
6729d05c1feSAnup Patel 		send_sig_mceerr(BUS_MCEERR_AR, (void __user *)hva,
6739d05c1feSAnup Patel 				vma_pageshift, current);
6749f701326SAnup Patel 		return 0;
6759f701326SAnup Patel 	}
6769d05c1feSAnup Patel 	if (is_error_noslot_pfn(hfn))
6779d05c1feSAnup Patel 		return -EFAULT;
6789d05c1feSAnup Patel 
6799d05c1feSAnup Patel 	/*
6809d05c1feSAnup Patel 	 * If logging is active then we allow writable pages only
6819d05c1feSAnup Patel 	 * for write faults.
6829d05c1feSAnup Patel 	 */
6839d05c1feSAnup Patel 	if (logging && !is_write)
6846259d2f8SZhang Jiaming 		writable = false;
6859d05c1feSAnup Patel 
6869d05c1feSAnup Patel 	spin_lock(&kvm->mmu_lock);
6879d05c1feSAnup Patel 
68820ec3ebdSChao Peng 	if (mmu_invalidate_retry(kvm, mmu_seq))
6899955371cSAnup Patel 		goto out_unlock;
6909955371cSAnup Patel 
6916259d2f8SZhang Jiaming 	if (writable) {
6929d05c1feSAnup Patel 		kvm_set_pfn_dirty(hfn);
6939d05c1feSAnup Patel 		mark_page_dirty(kvm, gfn);
69426708234SAnup Patel 		ret = gstage_map_page(kvm, pcache, gpa, hfn << PAGE_SHIFT,
6959d05c1feSAnup Patel 				      vma_pagesize, false, true);
6969d05c1feSAnup Patel 	} else {
69726708234SAnup Patel 		ret = gstage_map_page(kvm, pcache, gpa, hfn << PAGE_SHIFT,
6989d05c1feSAnup Patel 				      vma_pagesize, true, true);
6999d05c1feSAnup Patel 	}
7009d05c1feSAnup Patel 
7019d05c1feSAnup Patel 	if (ret)
70226708234SAnup Patel 		kvm_err("Failed to map in G-stage\n");
7039d05c1feSAnup Patel 
7049955371cSAnup Patel out_unlock:
7059d05c1feSAnup Patel 	spin_unlock(&kvm->mmu_lock);
7069d05c1feSAnup Patel 	kvm_set_pfn_accessed(hfn);
7079d05c1feSAnup Patel 	kvm_release_pfn_clean(hfn);
7089d05c1feSAnup Patel 	return ret;
7099d05c1feSAnup Patel }
7109f701326SAnup Patel 
kvm_riscv_gstage_alloc_pgd(struct kvm * kvm)71126708234SAnup Patel int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm)
71299cdc6c1SAnup Patel {
7139d05c1feSAnup Patel 	struct page *pgd_page;
7149d05c1feSAnup Patel 
7159d05c1feSAnup Patel 	if (kvm->arch.pgd != NULL) {
7169d05c1feSAnup Patel 		kvm_err("kvm_arch already initialized?\n");
7179d05c1feSAnup Patel 		return -EINVAL;
7189d05c1feSAnup Patel 	}
7199d05c1feSAnup Patel 
7209d05c1feSAnup Patel 	pgd_page = alloc_pages(GFP_KERNEL | __GFP_ZERO,
72126708234SAnup Patel 				get_order(gstage_pgd_size));
7229d05c1feSAnup Patel 	if (!pgd_page)
7239d05c1feSAnup Patel 		return -ENOMEM;
7249d05c1feSAnup Patel 	kvm->arch.pgd = page_to_virt(pgd_page);
7259d05c1feSAnup Patel 	kvm->arch.pgd_phys = page_to_phys(pgd_page);
7269d05c1feSAnup Patel 
72799cdc6c1SAnup Patel 	return 0;
72899cdc6c1SAnup Patel }
72999cdc6c1SAnup Patel 
kvm_riscv_gstage_free_pgd(struct kvm * kvm)73026708234SAnup Patel void kvm_riscv_gstage_free_pgd(struct kvm *kvm)
73199cdc6c1SAnup Patel {
7329d05c1feSAnup Patel 	void *pgd = NULL;
7339d05c1feSAnup Patel 
7349d05c1feSAnup Patel 	spin_lock(&kvm->mmu_lock);
7359d05c1feSAnup Patel 	if (kvm->arch.pgd) {
73626708234SAnup Patel 		gstage_unmap_range(kvm, 0UL, gstage_gpa_size, false);
7379d05c1feSAnup Patel 		pgd = READ_ONCE(kvm->arch.pgd);
7389d05c1feSAnup Patel 		kvm->arch.pgd = NULL;
7399d05c1feSAnup Patel 		kvm->arch.pgd_phys = 0;
7409d05c1feSAnup Patel 	}
7419d05c1feSAnup Patel 	spin_unlock(&kvm->mmu_lock);
7429d05c1feSAnup Patel 
7439d05c1feSAnup Patel 	if (pgd)
74426708234SAnup Patel 		free_pages((unsigned long)pgd, get_order(gstage_pgd_size));
74599cdc6c1SAnup Patel }
74699cdc6c1SAnup Patel 
kvm_riscv_gstage_update_hgatp(struct kvm_vcpu * vcpu)74726708234SAnup Patel void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu)
74899cdc6c1SAnup Patel {
74926708234SAnup Patel 	unsigned long hgatp = gstage_mode;
7509d05c1feSAnup Patel 	struct kvm_arch *k = &vcpu->kvm->arch;
7519d05c1feSAnup Patel 
752e290dbb7SAnup Patel 	hgatp |= (READ_ONCE(k->vmid.vmid) << HGATP_VMID_SHIFT) & HGATP_VMID;
7539d05c1feSAnup Patel 	hgatp |= (k->pgd_phys >> PAGE_SHIFT) & HGATP_PPN;
7549d05c1feSAnup Patel 
7559d05c1feSAnup Patel 	csr_write(CSR_HGATP, hgatp);
7569d05c1feSAnup Patel 
75726708234SAnup Patel 	if (!kvm_riscv_gstage_vmid_bits())
7582415e46eSAnup Patel 		kvm_riscv_local_hfence_gvma_all();
7599d05c1feSAnup Patel }
7609d05c1feSAnup Patel 
kvm_riscv_gstage_mode_detect(void)76145b66dc1SSean Christopherson void __init kvm_riscv_gstage_mode_detect(void)
7629d05c1feSAnup Patel {
7639d05c1feSAnup Patel #ifdef CONFIG_64BIT
764b4bbb95eSAnup Patel 	/* Try Sv57x4 G-stage mode */
765b4bbb95eSAnup Patel 	csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
766b4bbb95eSAnup Patel 	if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV57X4) {
767b4bbb95eSAnup Patel 		gstage_mode = (HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
768b4bbb95eSAnup Patel 		gstage_pgd_levels = 5;
769b4bbb95eSAnup Patel 		goto skip_sv48x4_test;
770b4bbb95eSAnup Patel 	}
771b4bbb95eSAnup Patel 
77226708234SAnup Patel 	/* Try Sv48x4 G-stage mode */
7739d05c1feSAnup Patel 	csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
7749d05c1feSAnup Patel 	if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV48X4) {
77526708234SAnup Patel 		gstage_mode = (HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
77626708234SAnup Patel 		gstage_pgd_levels = 4;
7779d05c1feSAnup Patel 	}
778b4bbb95eSAnup Patel skip_sv48x4_test:
7799d05c1feSAnup Patel 
780b4bbb95eSAnup Patel 	csr_write(CSR_HGATP, 0);
7812415e46eSAnup Patel 	kvm_riscv_local_hfence_gvma_all();
7829d05c1feSAnup Patel #endif
7839d05c1feSAnup Patel }
7849d05c1feSAnup Patel 
kvm_riscv_gstage_mode(void)78545b66dc1SSean Christopherson unsigned long __init kvm_riscv_gstage_mode(void)
7869d05c1feSAnup Patel {
78726708234SAnup Patel 	return gstage_mode >> HGATP_MODE_SHIFT;
78899cdc6c1SAnup Patel }
789a457fd56SAnup Patel 
kvm_riscv_gstage_gpa_bits(void)79026708234SAnup Patel int kvm_riscv_gstage_gpa_bits(void)
791a457fd56SAnup Patel {
79226708234SAnup Patel 	return gstage_gpa_bits;
793a457fd56SAnup Patel }
794