xref: /openbmc/linux/arch/riscv/kernel/sbi-ipi.c (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1832f15f4SAnup Patel // SPDX-License-Identifier: GPL-2.0-only
2832f15f4SAnup Patel /*
3832f15f4SAnup Patel  * Multiplex several IPIs over a single HW IPI.
4832f15f4SAnup Patel  *
5832f15f4SAnup Patel  * Copyright (c) 2022 Ventana Micro Systems Inc.
6832f15f4SAnup Patel  */
7832f15f4SAnup Patel 
8832f15f4SAnup Patel #define pr_fmt(fmt) "riscv: " fmt
9832f15f4SAnup Patel #include <linux/cpu.h>
10832f15f4SAnup Patel #include <linux/init.h>
11832f15f4SAnup Patel #include <linux/irq.h>
12832f15f4SAnup Patel #include <linux/irqchip/chained_irq.h>
13832f15f4SAnup Patel #include <linux/irqdomain.h>
14832f15f4SAnup Patel #include <asm/sbi.h>
15832f15f4SAnup Patel 
16832f15f4SAnup Patel static int sbi_ipi_virq;
17832f15f4SAnup Patel 
sbi_ipi_handle(struct irq_desc * desc)18832f15f4SAnup Patel static void sbi_ipi_handle(struct irq_desc *desc)
19832f15f4SAnup Patel {
20832f15f4SAnup Patel 	struct irq_chip *chip = irq_desc_get_chip(desc);
21832f15f4SAnup Patel 
22832f15f4SAnup Patel 	chained_irq_enter(chip, desc);
23832f15f4SAnup Patel 
24832f15f4SAnup Patel 	csr_clear(CSR_IP, IE_SIE);
25832f15f4SAnup Patel 	ipi_mux_process();
26832f15f4SAnup Patel 
27832f15f4SAnup Patel 	chained_irq_exit(chip, desc);
28832f15f4SAnup Patel }
29832f15f4SAnup Patel 
sbi_ipi_starting_cpu(unsigned int cpu)30832f15f4SAnup Patel static int sbi_ipi_starting_cpu(unsigned int cpu)
31832f15f4SAnup Patel {
32832f15f4SAnup Patel 	enable_percpu_irq(sbi_ipi_virq, irq_get_trigger_type(sbi_ipi_virq));
33832f15f4SAnup Patel 	return 0;
34832f15f4SAnup Patel }
35832f15f4SAnup Patel 
sbi_ipi_init(void)36832f15f4SAnup Patel void __init sbi_ipi_init(void)
37832f15f4SAnup Patel {
38832f15f4SAnup Patel 	int virq;
39832f15f4SAnup Patel 	struct irq_domain *domain;
40832f15f4SAnup Patel 
41832f15f4SAnup Patel 	if (riscv_ipi_have_virq_range())
42832f15f4SAnup Patel 		return;
43832f15f4SAnup Patel 
44832f15f4SAnup Patel 	domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(),
45832f15f4SAnup Patel 					  DOMAIN_BUS_ANY);
46832f15f4SAnup Patel 	if (!domain) {
47832f15f4SAnup Patel 		pr_err("unable to find INTC IRQ domain\n");
48832f15f4SAnup Patel 		return;
49832f15f4SAnup Patel 	}
50832f15f4SAnup Patel 
51832f15f4SAnup Patel 	sbi_ipi_virq = irq_create_mapping(domain, RV_IRQ_SOFT);
52832f15f4SAnup Patel 	if (!sbi_ipi_virq) {
53832f15f4SAnup Patel 		pr_err("unable to create INTC IRQ mapping\n");
54832f15f4SAnup Patel 		return;
55832f15f4SAnup Patel 	}
56832f15f4SAnup Patel 
57832f15f4SAnup Patel 	virq = ipi_mux_create(BITS_PER_BYTE, sbi_send_ipi);
58832f15f4SAnup Patel 	if (virq <= 0) {
59832f15f4SAnup Patel 		pr_err("unable to create muxed IPIs\n");
60832f15f4SAnup Patel 		irq_dispose_mapping(sbi_ipi_virq);
61832f15f4SAnup Patel 		return;
62832f15f4SAnup Patel 	}
63832f15f4SAnup Patel 
64832f15f4SAnup Patel 	irq_set_chained_handler(sbi_ipi_virq, sbi_ipi_handle);
65832f15f4SAnup Patel 
66832f15f4SAnup Patel 	/*
67832f15f4SAnup Patel 	 * Don't disable IPI when CPU goes offline because
68832f15f4SAnup Patel 	 * the masking/unmasking of virtual IPIs is done
69832f15f4SAnup Patel 	 * via generic IPI-Mux
70832f15f4SAnup Patel 	 */
71832f15f4SAnup Patel 	cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
72832f15f4SAnup Patel 			  "irqchip/sbi-ipi:starting",
73832f15f4SAnup Patel 			  sbi_ipi_starting_cpu, NULL);
74832f15f4SAnup Patel 
75*fb0f3d28SAnup Patel 	riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, false);
76832f15f4SAnup Patel 	pr_info("providing IPIs using SBI IPI extension\n");
77832f15f4SAnup Patel }
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