11f059dfdSIngo Molnar #ifndef _ASM_RISCV_VMALLOC_H 21f059dfdSIngo Molnar #define _ASM_RISCV_VMALLOC_H 31f059dfdSIngo Molnar 4310f541aSLiu Shixin #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 5310f541aSLiu Shixin 6d566bea4SAlexandre Ghiti extern bool pgtable_l4_enabled, pgtable_l5_enabled; 7d566bea4SAlexandre Ghiti 8310f541aSLiu Shixin #define IOREMAP_MAX_ORDER (PUD_SHIFT) 9310f541aSLiu Shixin 10310f541aSLiu Shixin #define arch_vmap_pud_supported arch_vmap_pud_supported arch_vmap_pud_supported(pgprot_t prot)11310f541aSLiu Shixinstatic inline bool arch_vmap_pud_supported(pgprot_t prot) 12310f541aSLiu Shixin { 13d566bea4SAlexandre Ghiti return pgtable_l4_enabled || pgtable_l5_enabled; 14310f541aSLiu Shixin } 15310f541aSLiu Shixin 16310f541aSLiu Shixin #define arch_vmap_pmd_supported arch_vmap_pmd_supported arch_vmap_pmd_supported(pgprot_t prot)17310f541aSLiu Shixinstatic inline bool arch_vmap_pmd_supported(pgprot_t prot) 18310f541aSLiu Shixin { 19310f541aSLiu Shixin return true; 20310f541aSLiu Shixin } 21310f541aSLiu Shixin 22*2b7ce74eSAlexandre Ghiti #endif 23310f541aSLiu Shixin 241f059dfdSIngo Molnar #endif /* _ASM_RISCV_VMALLOC_H */ 25