1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 11 #include <asm/pgtable-bits.h> 12 13 #ifndef __ASSEMBLY__ 14 15 /* Page Upper Directory not used in RISC-V */ 16 #include <asm-generic/pgtable-nopud.h> 17 #include <asm/page.h> 18 #include <asm/tlbflush.h> 19 #include <linux/mm_types.h> 20 21 #ifdef CONFIG_64BIT 22 #include <asm/pgtable-64.h> 23 #else 24 #include <asm/pgtable-32.h> 25 #endif /* CONFIG_64BIT */ 26 27 /* Number of entries in the page global directory */ 28 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 29 /* Number of entries in the page table */ 30 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 31 32 /* Number of PGD entries that a user-mode program can use */ 33 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 34 #define FIRST_USER_ADDRESS 0 35 36 /* Page protection bits */ 37 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 38 39 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE) 40 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 41 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 42 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 43 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 44 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 45 _PAGE_EXEC | _PAGE_WRITE) 46 47 #define PAGE_COPY PAGE_READ 48 #define PAGE_COPY_EXEC PAGE_EXEC 49 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 50 #define PAGE_SHARED PAGE_WRITE 51 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 52 53 #define _PAGE_KERNEL (_PAGE_READ \ 54 | _PAGE_WRITE \ 55 | _PAGE_PRESENT \ 56 | _PAGE_ACCESSED \ 57 | _PAGE_DIRTY) 58 59 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 60 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 61 62 extern pgd_t swapper_pg_dir[]; 63 64 /* MAP_PRIVATE permissions: xwr (copy-on-write) */ 65 #define __P000 PAGE_NONE 66 #define __P001 PAGE_READ 67 #define __P010 PAGE_COPY 68 #define __P011 PAGE_COPY 69 #define __P100 PAGE_EXEC 70 #define __P101 PAGE_READ_EXEC 71 #define __P110 PAGE_COPY_EXEC 72 #define __P111 PAGE_COPY_READ_EXEC 73 74 /* MAP_SHARED permissions: xwr */ 75 #define __S000 PAGE_NONE 76 #define __S001 PAGE_READ 77 #define __S010 PAGE_SHARED 78 #define __S011 PAGE_SHARED 79 #define __S100 PAGE_EXEC 80 #define __S101 PAGE_READ_EXEC 81 #define __S110 PAGE_SHARED_EXEC 82 #define __S111 PAGE_SHARED_EXEC 83 84 /* 85 * ZERO_PAGE is a global shared page that is always zero, 86 * used for zero-mapped memory areas, etc. 87 */ 88 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 89 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 90 91 static inline int pmd_present(pmd_t pmd) 92 { 93 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 94 } 95 96 static inline int pmd_none(pmd_t pmd) 97 { 98 return (pmd_val(pmd) == 0); 99 } 100 101 static inline int pmd_bad(pmd_t pmd) 102 { 103 return !pmd_present(pmd); 104 } 105 106 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 107 { 108 *pmdp = pmd; 109 } 110 111 static inline void pmd_clear(pmd_t *pmdp) 112 { 113 set_pmd(pmdp, __pmd(0)); 114 } 115 116 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 117 { 118 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 119 } 120 121 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 122 123 /* Locate an entry in the page global directory */ 124 static inline pgd_t *pgd_offset(const struct mm_struct *mm, unsigned long addr) 125 { 126 return mm->pgd + pgd_index(addr); 127 } 128 /* Locate an entry in the kernel page global directory */ 129 #define pgd_offset_k(addr) pgd_offset(&init_mm, (addr)) 130 131 static inline struct page *pmd_page(pmd_t pmd) 132 { 133 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 134 } 135 136 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 137 { 138 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 139 } 140 141 /* Yields the page frame number (PFN) of a page table entry */ 142 static inline unsigned long pte_pfn(pte_t pte) 143 { 144 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 145 } 146 147 #define pte_page(x) pfn_to_page(pte_pfn(x)) 148 149 /* Constructs a page table entry */ 150 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 151 { 152 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 153 } 154 155 static inline pte_t mk_pte(struct page *page, pgprot_t prot) 156 { 157 return pfn_pte(page_to_pfn(page), prot); 158 } 159 160 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 161 162 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long addr) 163 { 164 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(addr); 165 } 166 167 #define pte_offset_map(dir, addr) pte_offset_kernel((dir), (addr)) 168 #define pte_unmap(pte) ((void)(pte)) 169 170 static inline int pte_present(pte_t pte) 171 { 172 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 173 } 174 175 static inline int pte_none(pte_t pte) 176 { 177 return (pte_val(pte) == 0); 178 } 179 180 static inline int pte_write(pte_t pte) 181 { 182 return pte_val(pte) & _PAGE_WRITE; 183 } 184 185 static inline int pte_exec(pte_t pte) 186 { 187 return pte_val(pte) & _PAGE_EXEC; 188 } 189 190 static inline int pte_huge(pte_t pte) 191 { 192 return pte_present(pte) 193 && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 194 } 195 196 static inline int pte_dirty(pte_t pte) 197 { 198 return pte_val(pte) & _PAGE_DIRTY; 199 } 200 201 static inline int pte_young(pte_t pte) 202 { 203 return pte_val(pte) & _PAGE_ACCESSED; 204 } 205 206 static inline int pte_special(pte_t pte) 207 { 208 return pte_val(pte) & _PAGE_SPECIAL; 209 } 210 211 /* static inline pte_t pte_rdprotect(pte_t pte) */ 212 213 static inline pte_t pte_wrprotect(pte_t pte) 214 { 215 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 216 } 217 218 /* static inline pte_t pte_mkread(pte_t pte) */ 219 220 static inline pte_t pte_mkwrite(pte_t pte) 221 { 222 return __pte(pte_val(pte) | _PAGE_WRITE); 223 } 224 225 /* static inline pte_t pte_mkexec(pte_t pte) */ 226 227 static inline pte_t pte_mkdirty(pte_t pte) 228 { 229 return __pte(pte_val(pte) | _PAGE_DIRTY); 230 } 231 232 static inline pte_t pte_mkclean(pte_t pte) 233 { 234 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 235 } 236 237 static inline pte_t pte_mkyoung(pte_t pte) 238 { 239 return __pte(pte_val(pte) | _PAGE_ACCESSED); 240 } 241 242 static inline pte_t pte_mkold(pte_t pte) 243 { 244 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 245 } 246 247 static inline pte_t pte_mkspecial(pte_t pte) 248 { 249 return __pte(pte_val(pte) | _PAGE_SPECIAL); 250 } 251 252 static inline pte_t pte_mkhuge(pte_t pte) 253 { 254 return pte; 255 } 256 257 /* Modify page protection bits */ 258 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 259 { 260 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 261 } 262 263 #define pgd_ERROR(e) \ 264 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 265 266 267 /* Commit new configuration to MMU hardware */ 268 static inline void update_mmu_cache(struct vm_area_struct *vma, 269 unsigned long address, pte_t *ptep) 270 { 271 /* 272 * The kernel assumes that TLBs don't cache invalid entries, but 273 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 274 * cache flush; it is necessary even after writing invalid entries. 275 * Relying on flush_tlb_fix_spurious_fault would suffice, but 276 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 277 */ 278 local_flush_tlb_page(address); 279 } 280 281 #define __HAVE_ARCH_PTE_SAME 282 static inline int pte_same(pte_t pte_a, pte_t pte_b) 283 { 284 return pte_val(pte_a) == pte_val(pte_b); 285 } 286 287 /* 288 * Certain architectures need to do special things when PTEs within 289 * a page table are directly modified. Thus, the following hook is 290 * made available. 291 */ 292 static inline void set_pte(pte_t *ptep, pte_t pteval) 293 { 294 *ptep = pteval; 295 } 296 297 void flush_icache_pte(pte_t pte); 298 299 static inline void set_pte_at(struct mm_struct *mm, 300 unsigned long addr, pte_t *ptep, pte_t pteval) 301 { 302 if (pte_present(pteval) && pte_exec(pteval)) 303 flush_icache_pte(pteval); 304 305 set_pte(ptep, pteval); 306 } 307 308 static inline void pte_clear(struct mm_struct *mm, 309 unsigned long addr, pte_t *ptep) 310 { 311 set_pte_at(mm, addr, ptep, __pte(0)); 312 } 313 314 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 315 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 316 unsigned long address, pte_t *ptep, 317 pte_t entry, int dirty) 318 { 319 if (!pte_same(*ptep, entry)) 320 set_pte_at(vma->vm_mm, address, ptep, entry); 321 /* 322 * update_mmu_cache will unconditionally execute, handling both 323 * the case that the PTE changed and the spurious fault case. 324 */ 325 return true; 326 } 327 328 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 329 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 330 unsigned long address, pte_t *ptep) 331 { 332 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 333 } 334 335 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 336 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 337 unsigned long address, 338 pte_t *ptep) 339 { 340 if (!pte_young(*ptep)) 341 return 0; 342 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 343 } 344 345 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 346 static inline void ptep_set_wrprotect(struct mm_struct *mm, 347 unsigned long address, pte_t *ptep) 348 { 349 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 350 } 351 352 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 353 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 354 unsigned long address, pte_t *ptep) 355 { 356 /* 357 * This comment is borrowed from x86, but applies equally to RISC-V: 358 * 359 * Clearing the accessed bit without a TLB flush 360 * doesn't cause data corruption. [ It could cause incorrect 361 * page aging and the (mistaken) reclaim of hot pages, but the 362 * chance of that should be relatively low. ] 363 * 364 * So as a performance optimization don't flush the TLB when 365 * clearing the accessed bit, it will eventually be flushed by 366 * a context switch or a VM operation anyway. [ In the rare 367 * event of it not getting flushed for a long time the delay 368 * shouldn't really matter because there's no real memory 369 * pressure for swapout to react to. ] 370 */ 371 return ptep_test_and_clear_young(vma, address, ptep); 372 } 373 374 /* 375 * Encode and decode a swap entry 376 * 377 * Format of swap PTE: 378 * bit 0: _PAGE_PRESENT (zero) 379 * bit 1: _PAGE_PROT_NONE (zero) 380 * bits 2 to 6: swap type 381 * bits 7 to XLEN-1: swap offset 382 */ 383 #define __SWP_TYPE_SHIFT 2 384 #define __SWP_TYPE_BITS 5 385 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 386 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 387 388 #define MAX_SWAPFILES_CHECK() \ 389 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 390 391 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 392 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 393 #define __swp_entry(type, offset) ((swp_entry_t) \ 394 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 395 396 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 397 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 398 399 #ifdef CONFIG_FLATMEM 400 #define kern_addr_valid(addr) (1) /* FIXME */ 401 #endif 402 403 extern void setup_bootmem(void); 404 extern void paging_init(void); 405 406 static inline void pgtable_cache_init(void) 407 { 408 /* No page table caches to initialize */ 409 } 410 411 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 412 #define VMALLOC_END (PAGE_OFFSET - 1) 413 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 414 415 /* 416 * Task size is 0x4000000000 for RV64 or 0xb800000 for RV32. 417 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 418 */ 419 #ifdef CONFIG_64BIT 420 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 421 #else 422 #define TASK_SIZE VMALLOC_START 423 #endif 424 425 #include <asm-generic/pgtable.h> 426 427 #endif /* !__ASSEMBLY__ */ 428 429 #endif /* _ASM_RISCV_PGTABLE_H */ 430