1*f7fec5ecSAnup Patel /* SPDX-License-Identifier: GPL-2.0-only */ 2*f7fec5ecSAnup Patel /* 3*f7fec5ecSAnup Patel * Copyright (C) 2021 Western Digital Corporation or its affiliates. 4*f7fec5ecSAnup Patel * Copyright (C) 2022 Ventana Micro Systems Inc. 5*f7fec5ecSAnup Patel */ 6*f7fec5ecSAnup Patel #ifndef __KVM_RISCV_AIA_IMSIC_H 7*f7fec5ecSAnup Patel #define __KVM_RISCV_AIA_IMSIC_H 8*f7fec5ecSAnup Patel 9*f7fec5ecSAnup Patel #include <linux/types.h> 10*f7fec5ecSAnup Patel #include <asm/csr.h> 11*f7fec5ecSAnup Patel 12*f7fec5ecSAnup Patel #define IMSIC_MMIO_PAGE_SHIFT 12 13*f7fec5ecSAnup Patel #define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) 14*f7fec5ecSAnup Patel #define IMSIC_MMIO_PAGE_LE 0x00 15*f7fec5ecSAnup Patel #define IMSIC_MMIO_PAGE_BE 0x04 16*f7fec5ecSAnup Patel 17*f7fec5ecSAnup Patel #define IMSIC_MIN_ID 63 18*f7fec5ecSAnup Patel #define IMSIC_MAX_ID 2048 19*f7fec5ecSAnup Patel 20*f7fec5ecSAnup Patel #define IMSIC_EIDELIVERY 0x70 21*f7fec5ecSAnup Patel 22*f7fec5ecSAnup Patel #define IMSIC_EITHRESHOLD 0x72 23*f7fec5ecSAnup Patel 24*f7fec5ecSAnup Patel #define IMSIC_EIP0 0x80 25*f7fec5ecSAnup Patel #define IMSIC_EIP63 0xbf 26*f7fec5ecSAnup Patel #define IMSIC_EIPx_BITS 32 27*f7fec5ecSAnup Patel 28*f7fec5ecSAnup Patel #define IMSIC_EIE0 0xc0 29*f7fec5ecSAnup Patel #define IMSIC_EIE63 0xff 30*f7fec5ecSAnup Patel #define IMSIC_EIEx_BITS 32 31*f7fec5ecSAnup Patel 32*f7fec5ecSAnup Patel #define IMSIC_FIRST IMSIC_EIDELIVERY 33*f7fec5ecSAnup Patel #define IMSIC_LAST IMSIC_EIE63 34*f7fec5ecSAnup Patel 35*f7fec5ecSAnup Patel #define IMSIC_MMIO_SETIPNUM_LE 0x00 36*f7fec5ecSAnup Patel #define IMSIC_MMIO_SETIPNUM_BE 0x04 37*f7fec5ecSAnup Patel 38*f7fec5ecSAnup Patel #endif 39