1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2021 Sifive. 4 */ 5 #ifndef ASM_ERRATA_LIST_H 6 #define ASM_ERRATA_LIST_H 7 8 #include <asm/alternative.h> 9 #include <asm/csr.h> 10 #include <asm/hwcap.h> 11 #include <asm/vendorid_list.h> 12 13 #ifdef CONFIG_ERRATA_SIFIVE 14 #define ERRATA_SIFIVE_CIP_453 0 15 #define ERRATA_SIFIVE_CIP_1200 1 16 #define ERRATA_SIFIVE_NUMBER 2 17 #endif 18 19 #ifdef CONFIG_ERRATA_THEAD 20 #define ERRATA_THEAD_PBMT 0 21 #define ERRATA_THEAD_CMO 1 22 #define ERRATA_THEAD_PMU 2 23 #define ERRATA_THEAD_NUMBER 3 24 #endif 25 26 #define CPUFEATURE_SVPBMT 0 27 #define CPUFEATURE_ZICBOM 1 28 #define CPUFEATURE_ZBB 2 29 #define CPUFEATURE_NUMBER 3 30 31 #ifdef __ASSEMBLY__ 32 33 #define ALT_INSN_FAULT(x) \ 34 ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ 35 __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ 36 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 37 CONFIG_ERRATA_SIFIVE_CIP_453) 38 39 #define ALT_PAGE_FAULT(x) \ 40 ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ 41 __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ 42 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 43 CONFIG_ERRATA_SIFIVE_CIP_453) 44 #else /* !__ASSEMBLY__ */ 45 46 #define ALT_FLUSH_TLB_PAGE(x) \ 47 asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ 48 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ 49 : : "r" (addr) : "memory") 50 51 /* 52 * _val is marked as "will be overwritten", so need to set it to 0 53 * in the default case. 54 */ 55 #define ALT_SVPBMT_SHIFT 61 56 #define ALT_THEAD_PBMT_SHIFT 59 57 #define ALT_SVPBMT(_val, prot) \ 58 asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ 59 "li %0, %1\t\nslli %0,%0,%3", 0, \ 60 RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ 61 "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ 62 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 63 : "=r"(_val) \ 64 : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ 65 "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 66 "I"(ALT_SVPBMT_SHIFT), \ 67 "I"(ALT_THEAD_PBMT_SHIFT)) 68 69 #ifdef CONFIG_ERRATA_THEAD_PBMT 70 /* 71 * IO/NOCACHE memory types are handled together with svpbmt, 72 * so on T-Head chips, check if no other memory type is set, 73 * and set the non-0 PMA type if applicable. 74 */ 75 #define ALT_THEAD_PMA(_val) \ 76 asm volatile(ALTERNATIVE( \ 77 __nops(7), \ 78 "li t3, %1\n\t" \ 79 "slli t3, t3, %3\n\t" \ 80 "and t3, %0, t3\n\t" \ 81 "bne t3, zero, 2f\n\t" \ 82 "li t3, %2\n\t" \ 83 "slli t3, t3, %3\n\t" \ 84 "or %0, %0, t3\n\t" \ 85 "2:", THEAD_VENDOR_ID, \ 86 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 87 : "+r"(_val) \ 88 : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 89 "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 90 "I"(ALT_THEAD_PBMT_SHIFT) \ 91 : "t3") 92 #else 93 #define ALT_THEAD_PMA(_val) 94 #endif 95 96 /* 97 * dcache.ipa rs1 (invalidate, physical address) 98 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 99 * 0000001 01010 rs1 000 00000 0001011 100 * dache.iva rs1 (invalida, virtual address) 101 * 0000001 00110 rs1 000 00000 0001011 102 * 103 * dcache.cpa rs1 (clean, physical address) 104 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 105 * 0000001 01001 rs1 000 00000 0001011 106 * dcache.cva rs1 (clean, virtual address) 107 * 0000001 00100 rs1 000 00000 0001011 108 * 109 * dcache.cipa rs1 (clean then invalidate, physical address) 110 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 111 * 0000001 01011 rs1 000 00000 0001011 112 * dcache.civa rs1 (... virtual address) 113 * 0000001 00111 rs1 000 00000 0001011 114 * 115 * sync.s (make sure all cache operations finished) 116 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 117 * 0000000 11001 00000 000 00000 0001011 118 */ 119 #define THEAD_inval_A0 ".long 0x0265000b" 120 #define THEAD_clean_A0 ".long 0x0245000b" 121 #define THEAD_flush_A0 ".long 0x0275000b" 122 #define THEAD_SYNC_S ".long 0x0190000b" 123 124 #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ 125 asm volatile(ALTERNATIVE_2( \ 126 __nops(6), \ 127 "mv a0, %1\n\t" \ 128 "j 2f\n\t" \ 129 "3:\n\t" \ 130 "cbo." __stringify(_op) " (a0)\n\t" \ 131 "add a0, a0, %0\n\t" \ 132 "2:\n\t" \ 133 "bltu a0, %2, 3b\n\t" \ 134 "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ 135 "mv a0, %1\n\t" \ 136 "j 2f\n\t" \ 137 "3:\n\t" \ 138 THEAD_##_op##_A0 "\n\t" \ 139 "add a0, a0, %0\n\t" \ 140 "2:\n\t" \ 141 "bltu a0, %2, 3b\n\t" \ 142 THEAD_SYNC_S, THEAD_VENDOR_ID, \ 143 ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ 144 : : "r"(_cachesize), \ 145 "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ 146 "r"((unsigned long)(_start) + (_size)) \ 147 : "a0") 148 149 #define THEAD_C9XX_RV_IRQ_PMU 17 150 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 151 152 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ 153 asm volatile(ALTERNATIVE( \ 154 "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ 155 "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ 156 THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ 157 CONFIG_ERRATA_THEAD_PMU) \ 158 : "=r" (__ovl) : \ 159 : "memory") 160 161 #endif /* __ASSEMBLY__ */ 162 163 #endif 164