1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2021 Sifive. 4 */ 5 #ifndef ASM_ERRATA_LIST_H 6 #define ASM_ERRATA_LIST_H 7 8 #include <asm/alternative.h> 9 #include <asm/csr.h> 10 #include <asm/hwcap.h> 11 #include <asm/vendorid_list.h> 12 13 #ifdef CONFIG_ERRATA_SIFIVE 14 #define ERRATA_SIFIVE_CIP_453 0 15 #define ERRATA_SIFIVE_CIP_1200 1 16 #define ERRATA_SIFIVE_NUMBER 2 17 #endif 18 19 #ifdef CONFIG_ERRATA_THEAD 20 #define ERRATA_THEAD_PBMT 0 21 #define ERRATA_THEAD_CMO 1 22 #define ERRATA_THEAD_PMU 2 23 #define ERRATA_THEAD_NUMBER 3 24 #endif 25 26 #ifdef __ASSEMBLY__ 27 28 #define ALT_INSN_FAULT(x) \ 29 ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ 30 __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ 31 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 32 CONFIG_ERRATA_SIFIVE_CIP_453) 33 34 #define ALT_PAGE_FAULT(x) \ 35 ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ 36 __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ 37 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 38 CONFIG_ERRATA_SIFIVE_CIP_453) 39 #else /* !__ASSEMBLY__ */ 40 41 #define ALT_FLUSH_TLB_PAGE(x) \ 42 asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ 43 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ 44 : : "r" (addr) : "memory") 45 46 /* 47 * _val is marked as "will be overwritten", so need to set it to 0 48 * in the default case. 49 */ 50 #define ALT_SVPBMT_SHIFT 61 51 #define ALT_THEAD_PBMT_SHIFT 59 52 #define ALT_SVPBMT(_val, prot) \ 53 asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ 54 "li %0, %1\t\nslli %0,%0,%3", 0, \ 55 RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ 56 "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ 57 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 58 : "=r"(_val) \ 59 : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ 60 "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 61 "I"(ALT_SVPBMT_SHIFT), \ 62 "I"(ALT_THEAD_PBMT_SHIFT)) 63 64 #ifdef CONFIG_ERRATA_THEAD_PBMT 65 /* 66 * IO/NOCACHE memory types are handled together with svpbmt, 67 * so on T-Head chips, check if no other memory type is set, 68 * and set the non-0 PMA type if applicable. 69 */ 70 #define ALT_THEAD_PMA(_val) \ 71 asm volatile(ALTERNATIVE( \ 72 __nops(7), \ 73 "li t3, %1\n\t" \ 74 "slli t3, t3, %3\n\t" \ 75 "and t3, %0, t3\n\t" \ 76 "bne t3, zero, 2f\n\t" \ 77 "li t3, %2\n\t" \ 78 "slli t3, t3, %3\n\t" \ 79 "or %0, %0, t3\n\t" \ 80 "2:", THEAD_VENDOR_ID, \ 81 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 82 : "+r"(_val) \ 83 : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 84 "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 85 "I"(ALT_THEAD_PBMT_SHIFT) \ 86 : "t3") 87 #else 88 #define ALT_THEAD_PMA(_val) 89 #endif 90 91 /* 92 * dcache.ipa rs1 (invalidate, physical address) 93 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 94 * 0000001 01010 rs1 000 00000 0001011 95 * dache.iva rs1 (invalida, virtual address) 96 * 0000001 00110 rs1 000 00000 0001011 97 * 98 * dcache.cpa rs1 (clean, physical address) 99 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 100 * 0000001 01001 rs1 000 00000 0001011 101 * dcache.cva rs1 (clean, virtual address) 102 * 0000001 00100 rs1 000 00000 0001011 103 * 104 * dcache.cipa rs1 (clean then invalidate, physical address) 105 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 106 * 0000001 01011 rs1 000 00000 0001011 107 * dcache.civa rs1 (... virtual address) 108 * 0000001 00111 rs1 000 00000 0001011 109 * 110 * sync.s (make sure all cache operations finished) 111 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 112 * 0000000 11001 00000 000 00000 0001011 113 */ 114 #define THEAD_inval_A0 ".long 0x0265000b" 115 #define THEAD_clean_A0 ".long 0x0245000b" 116 #define THEAD_flush_A0 ".long 0x0275000b" 117 #define THEAD_SYNC_S ".long 0x0190000b" 118 119 #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ 120 asm volatile(ALTERNATIVE_2( \ 121 __nops(6), \ 122 "mv a0, %1\n\t" \ 123 "j 2f\n\t" \ 124 "3:\n\t" \ 125 "cbo." __stringify(_op) " (a0)\n\t" \ 126 "add a0, a0, %0\n\t" \ 127 "2:\n\t" \ 128 "bltu a0, %2, 3b\n\t" \ 129 "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ 130 "mv a0, %1\n\t" \ 131 "j 2f\n\t" \ 132 "3:\n\t" \ 133 THEAD_##_op##_A0 "\n\t" \ 134 "add a0, a0, %0\n\t" \ 135 "2:\n\t" \ 136 "bltu a0, %2, 3b\n\t" \ 137 THEAD_SYNC_S, THEAD_VENDOR_ID, \ 138 ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ 139 : : "r"(_cachesize), \ 140 "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ 141 "r"((unsigned long)(_start) + (_size)) \ 142 : "a0") 143 144 #define THEAD_C9XX_RV_IRQ_PMU 17 145 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 146 147 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ 148 asm volatile(ALTERNATIVE( \ 149 "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ 150 "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ 151 THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ 152 CONFIG_ERRATA_THEAD_PMU) \ 153 : "=r" (__ovl) : \ 154 : "memory") 155 156 #endif /* __ASSEMBLY__ */ 157 158 #endif 159