xref: /openbmc/linux/arch/riscv/include/asm/cache.h (revision 50acfb2b76e19f73270fef9a32726c7e18d08ec3)
1*50acfb2bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
276d2a049SPalmer Dabbelt /*
376d2a049SPalmer Dabbelt  * Copyright (C) 2017 Chen Liqin <liqin.chen@sunplusct.com>
476d2a049SPalmer Dabbelt  * Copyright (C) 2012 Regents of the University of California
576d2a049SPalmer Dabbelt  */
676d2a049SPalmer Dabbelt 
776d2a049SPalmer Dabbelt #ifndef _ASM_RISCV_CACHE_H
876d2a049SPalmer Dabbelt #define _ASM_RISCV_CACHE_H
976d2a049SPalmer Dabbelt 
1076d2a049SPalmer Dabbelt #define L1_CACHE_SHIFT		6
1176d2a049SPalmer Dabbelt 
1276d2a049SPalmer Dabbelt #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
1376d2a049SPalmer Dabbelt 
1476d2a049SPalmer Dabbelt #endif /* _ASM_RISCV_CACHE_H */
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