1*bc47b221SConor Dooley// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*bc47b221SConor Dooley/* Copyright (c) 2020-2022 Microchip Technology Inc */ 3*bc47b221SConor Dooley 4*bc47b221SConor Dooley/dts-v1/; 5*bc47b221SConor Dooley 6*bc47b221SConor Dooley#include "mpfs.dtsi" 7*bc47b221SConor Dooley#include "mpfs-polarberry-fabric.dtsi" 8*bc47b221SConor Dooley 9*bc47b221SConor Dooley/* Clock frequency (in Hz) of the rtcclk */ 10*bc47b221SConor Dooley#define MTIMER_FREQ 1000000 11*bc47b221SConor Dooley 12*bc47b221SConor Dooley/ { 13*bc47b221SConor Dooley model = "Sundance PolarBerry"; 14*bc47b221SConor Dooley compatible = "sundance,polarberry", "microchip,mpfs"; 15*bc47b221SConor Dooley 16*bc47b221SConor Dooley aliases { 17*bc47b221SConor Dooley ethernet0 = &mac1; 18*bc47b221SConor Dooley serial0 = &mmuart0; 19*bc47b221SConor Dooley }; 20*bc47b221SConor Dooley 21*bc47b221SConor Dooley chosen { 22*bc47b221SConor Dooley stdout-path = "serial0:115200n8"; 23*bc47b221SConor Dooley }; 24*bc47b221SConor Dooley 25*bc47b221SConor Dooley cpus { 26*bc47b221SConor Dooley timebase-frequency = <MTIMER_FREQ>; 27*bc47b221SConor Dooley }; 28*bc47b221SConor Dooley 29*bc47b221SConor Dooley ddrc_cache_lo: memory@80000000 { 30*bc47b221SConor Dooley device_type = "memory"; 31*bc47b221SConor Dooley reg = <0x0 0x80000000 0x0 0x2e000000>; 32*bc47b221SConor Dooley }; 33*bc47b221SConor Dooley 34*bc47b221SConor Dooley ddrc_cache_hi: memory@1000000000 { 35*bc47b221SConor Dooley device_type = "memory"; 36*bc47b221SConor Dooley reg = <0x10 0x00000000 0x0 0xC0000000>; 37*bc47b221SConor Dooley }; 38*bc47b221SConor Dooley}; 39*bc47b221SConor Dooley 40*bc47b221SConor Dooley/* 41*bc47b221SConor Dooley * phy0 is connected to mac0, but the port itself is on the (optional) carrier 42*bc47b221SConor Dooley * board. 43*bc47b221SConor Dooley */ 44*bc47b221SConor Dooley&mac0 { 45*bc47b221SConor Dooley phy-mode = "sgmii"; 46*bc47b221SConor Dooley phy-handle = <&phy0>; 47*bc47b221SConor Dooley status = "disabled"; 48*bc47b221SConor Dooley}; 49*bc47b221SConor Dooley 50*bc47b221SConor Dooley&mac1 { 51*bc47b221SConor Dooley phy-mode = "sgmii"; 52*bc47b221SConor Dooley phy-handle = <&phy1>; 53*bc47b221SConor Dooley status = "okay"; 54*bc47b221SConor Dooley 55*bc47b221SConor Dooley phy1: ethernet-phy@5 { 56*bc47b221SConor Dooley reg = <5>; 57*bc47b221SConor Dooley }; 58*bc47b221SConor Dooley 59*bc47b221SConor Dooley phy0: ethernet-phy@4 { 60*bc47b221SConor Dooley reg = <4>; 61*bc47b221SConor Dooley }; 62*bc47b221SConor Dooley}; 63*bc47b221SConor Dooley 64*bc47b221SConor Dooley&mbox { 65*bc47b221SConor Dooley status = "okay"; 66*bc47b221SConor Dooley}; 67*bc47b221SConor Dooley 68*bc47b221SConor Dooley&mmc { 69*bc47b221SConor Dooley bus-width = <4>; 70*bc47b221SConor Dooley disable-wp; 71*bc47b221SConor Dooley cap-sd-highspeed; 72*bc47b221SConor Dooley cap-mmc-highspeed; 73*bc47b221SConor Dooley mmc-ddr-1_8v; 74*bc47b221SConor Dooley mmc-hs200-1_8v; 75*bc47b221SConor Dooley sd-uhs-sdr12; 76*bc47b221SConor Dooley sd-uhs-sdr25; 77*bc47b221SConor Dooley sd-uhs-sdr50; 78*bc47b221SConor Dooley sd-uhs-sdr104; 79*bc47b221SConor Dooley status = "okay"; 80*bc47b221SConor Dooley}; 81*bc47b221SConor Dooley 82*bc47b221SConor Dooley&mmuart0 { 83*bc47b221SConor Dooley status = "okay"; 84*bc47b221SConor Dooley}; 85*bc47b221SConor Dooley 86*bc47b221SConor Dooley&refclk { 87*bc47b221SConor Dooley clock-frequency = <125000000>; 88*bc47b221SConor Dooley}; 89*bc47b221SConor Dooley 90*bc47b221SConor Dooley&rtc { 91*bc47b221SConor Dooley status = "okay"; 92*bc47b221SConor Dooley}; 93*bc47b221SConor Dooley 94*bc47b221SConor Dooley&syscontroller { 95*bc47b221SConor Dooley status = "okay"; 96*bc47b221SConor Dooley}; 97