1 /* 2 * SMP support for PowerNV machines. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/sched.h> 15 #include <linux/sched/hotplug.h> 16 #include <linux/smp.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/cpu.h> 22 23 #include <asm/irq.h> 24 #include <asm/smp.h> 25 #include <asm/paca.h> 26 #include <asm/machdep.h> 27 #include <asm/cputable.h> 28 #include <asm/firmware.h> 29 #include <asm/vdso_datapage.h> 30 #include <asm/cputhreads.h> 31 #include <asm/xics.h> 32 #include <asm/xive.h> 33 #include <asm/opal.h> 34 #include <asm/runlatch.h> 35 #include <asm/code-patching.h> 36 #include <asm/dbell.h> 37 #include <asm/kvm_ppc.h> 38 #include <asm/ppc-opcode.h> 39 #include <asm/cpuidle.h> 40 41 #include "powernv.h" 42 43 #ifdef DEBUG 44 #include <asm/udbg.h> 45 #define DBG(fmt...) udbg_printf(fmt) 46 #else 47 #define DBG(fmt...) 48 #endif 49 50 static void pnv_smp_setup_cpu(int cpu) 51 { 52 if (xive_enabled()) 53 xive_smp_setup_cpu(); 54 else if (cpu != boot_cpuid) 55 xics_setup_cpu(); 56 57 #ifdef CONFIG_PPC_DOORBELL 58 if (cpu_has_feature(CPU_FTR_DBELL)) 59 doorbell_setup_this_cpu(); 60 #endif 61 } 62 63 static int pnv_smp_kick_cpu(int nr) 64 { 65 unsigned int pcpu = get_hard_smp_processor_id(nr); 66 unsigned long start_here = 67 __pa(ppc_function_entry(generic_secondary_smp_init)); 68 long rc; 69 uint8_t status; 70 71 BUG_ON(nr < 0 || nr >= NR_CPUS); 72 73 /* 74 * If we already started or OPAL is not supported, we just 75 * kick the CPU via the PACA 76 */ 77 if (paca[nr].cpu_start || !firmware_has_feature(FW_FEATURE_OPAL)) 78 goto kick; 79 80 /* 81 * At this point, the CPU can either be spinning on the way in 82 * from kexec or be inside OPAL waiting to be started for the 83 * first time. OPAL v3 allows us to query OPAL to know if it 84 * has the CPUs, so we do that 85 */ 86 rc = opal_query_cpu_status(pcpu, &status); 87 if (rc != OPAL_SUCCESS) { 88 pr_warn("OPAL Error %ld querying CPU %d state\n", rc, nr); 89 return -ENODEV; 90 } 91 92 /* 93 * Already started, just kick it, probably coming from 94 * kexec and spinning 95 */ 96 if (status == OPAL_THREAD_STARTED) 97 goto kick; 98 99 /* 100 * Available/inactive, let's kick it 101 */ 102 if (status == OPAL_THREAD_INACTIVE) { 103 pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu); 104 rc = opal_start_cpu(pcpu, start_here); 105 if (rc != OPAL_SUCCESS) { 106 pr_warn("OPAL Error %ld starting CPU %d\n", rc, nr); 107 return -ENODEV; 108 } 109 } else { 110 /* 111 * An unavailable CPU (or any other unknown status) 112 * shouldn't be started. It should also 113 * not be in the possible map but currently it can 114 * happen 115 */ 116 pr_devel("OPAL: CPU %d (HW 0x%x) is unavailable" 117 " (status %d)...\n", nr, pcpu, status); 118 return -ENODEV; 119 } 120 121 kick: 122 return smp_generic_kick_cpu(nr); 123 } 124 125 #ifdef CONFIG_HOTPLUG_CPU 126 127 static int pnv_smp_cpu_disable(void) 128 { 129 int cpu = smp_processor_id(); 130 131 /* This is identical to pSeries... might consolidate by 132 * moving migrate_irqs_away to a ppc_md with default to 133 * the generic fixup_irqs. --BenH. 134 */ 135 set_cpu_online(cpu, false); 136 vdso_data->processorCount--; 137 if (cpu == boot_cpuid) 138 boot_cpuid = cpumask_any(cpu_online_mask); 139 if (xive_enabled()) 140 xive_smp_disable_cpu(); 141 else 142 xics_migrate_irqs_away(); 143 return 0; 144 } 145 146 static void pnv_smp_cpu_kill_self(void) 147 { 148 unsigned int cpu; 149 unsigned long srr1, wmask; 150 151 /* Standard hot unplug procedure */ 152 local_irq_disable(); 153 idle_task_exit(); 154 current->active_mm = NULL; /* for sanity */ 155 cpu = smp_processor_id(); 156 DBG("CPU%d offline\n", cpu); 157 generic_set_cpu_dead(cpu); 158 smp_wmb(); 159 160 wmask = SRR1_WAKEMASK; 161 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 162 wmask = SRR1_WAKEMASK_P8; 163 164 /* We don't want to take decrementer interrupts while we are offline, 165 * so clear LPCR:PECE1. We keep PECE2 (and LPCR_PECE_HVEE on P9) 166 * enabled as to let IPIs in. 167 */ 168 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1); 169 170 /* 171 * Hard-disable interrupts, and then clear irq_happened flags 172 * that we can safely ignore while off-line, since they 173 * are for things for which we do no processing when off-line 174 * (or in the case of HMI, all the processing we need to do 175 * is done in lower-level real-mode code). 176 */ 177 hard_irq_disable(); 178 local_paca->irq_happened &= ~(PACA_IRQ_DEC | PACA_IRQ_HMI); 179 180 while (!generic_check_cpu_restart(cpu)) { 181 /* 182 * Clear IPI flag, since we don't handle IPIs while 183 * offline, except for those when changing micro-threading 184 * mode, which are handled explicitly below, and those 185 * for coming online, which are handled via 186 * generic_check_cpu_restart() calls. 187 */ 188 kvmppc_set_host_ipi(cpu, 0); 189 190 ppc64_runlatch_off(); 191 srr1 = pnv_cpu_offline(cpu); 192 ppc64_runlatch_on(); 193 194 /* 195 * If the SRR1 value indicates that we woke up due to 196 * an external interrupt, then clear the interrupt. 197 * We clear the interrupt before checking for the 198 * reason, so as to avoid a race where we wake up for 199 * some other reason, find nothing and clear the interrupt 200 * just as some other cpu is sending us an interrupt. 201 * If we returned from power7_nap as a result of 202 * having finished executing in a KVM guest, then srr1 203 * contains 0. 204 */ 205 if (((srr1 & wmask) == SRR1_WAKEEE) || 206 ((srr1 & wmask) == SRR1_WAKEHVI) || 207 (local_paca->irq_happened & PACA_IRQ_EE)) { 208 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 209 if (xive_enabled()) 210 xive_flush_interrupt(); 211 else 212 icp_opal_flush_interrupt(); 213 } else 214 icp_native_flush_interrupt(); 215 } else if ((srr1 & wmask) == SRR1_WAKEHDBELL) { 216 unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 217 asm volatile(PPC_MSGCLR(%0) : : "r" (msg)); 218 } 219 local_paca->irq_happened &= ~(PACA_IRQ_EE | PACA_IRQ_DBELL); 220 smp_mb(); 221 222 if (cpu_core_split_required()) 223 continue; 224 225 if (srr1 && !generic_check_cpu_restart(cpu)) 226 DBG("CPU%d Unexpected exit while offline !\n", cpu); 227 } 228 229 /* Re-enable decrementer interrupts */ 230 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_PECE1); 231 DBG("CPU%d coming online...\n", cpu); 232 } 233 234 #endif /* CONFIG_HOTPLUG_CPU */ 235 236 static int pnv_cpu_bootable(unsigned int nr) 237 { 238 /* 239 * Starting with POWER8, the subcore logic relies on all threads of a 240 * core being booted so that they can participate in split mode 241 * switches. So on those machines we ignore the smt_enabled_at_boot 242 * setting (smt-enabled on the kernel command line). 243 */ 244 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 245 return 1; 246 247 return smp_generic_cpu_bootable(nr); 248 } 249 250 static int pnv_smp_prepare_cpu(int cpu) 251 { 252 if (xive_enabled()) 253 return xive_smp_prepare_cpu(cpu); 254 return 0; 255 } 256 257 static void __init pnv_smp_probe(void) 258 { 259 if (xive_enabled()) 260 xive_smp_probe(); 261 else 262 xics_smp_probe(); 263 } 264 265 static struct smp_ops_t pnv_smp_ops = { 266 .message_pass = smp_muxed_ipi_message_pass, 267 .cause_ipi = NULL, /* Filled at runtime by xi{cs,ve}_smp_probe() */ 268 .probe = pnv_smp_probe, 269 .prepare_cpu = pnv_smp_prepare_cpu, 270 .kick_cpu = pnv_smp_kick_cpu, 271 .setup_cpu = pnv_smp_setup_cpu, 272 .cpu_bootable = pnv_cpu_bootable, 273 #ifdef CONFIG_HOTPLUG_CPU 274 .cpu_disable = pnv_smp_cpu_disable, 275 .cpu_die = generic_cpu_die, 276 #endif /* CONFIG_HOTPLUG_CPU */ 277 }; 278 279 /* This is called very early during platform setup_arch */ 280 void __init pnv_smp_init(void) 281 { 282 smp_ops = &pnv_smp_ops; 283 284 #ifdef CONFIG_HOTPLUG_CPU 285 ppc_md.cpu_die = pnv_smp_cpu_kill_self; 286 #endif 287 } 288