1 /* 2 * Copyright (C) 2006-2007 PA Semi, Inc 3 * 4 * Authors: Kip Walker, PA Semi 5 * Olof Johansson, PA Semi 6 * 7 * Maintained by: Olof Johansson <olof@lixom.net> 8 * 9 * Based on arch/powerpc/platforms/maple/setup.c 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24 25 #include <linux/errno.h> 26 #include <linux/kernel.h> 27 #include <linux/delay.h> 28 #include <linux/console.h> 29 #include <linux/pci.h> 30 31 #include <asm/prom.h> 32 #include <asm/system.h> 33 #include <asm/iommu.h> 34 #include <asm/machdep.h> 35 #include <asm/mpic.h> 36 #include <asm/smp.h> 37 #include <asm/time.h> 38 #include <asm/of_platform.h> 39 40 #include <pcmcia/ss.h> 41 #include <pcmcia/cistpl.h> 42 #include <pcmcia/ds.h> 43 44 #include "pasemi.h" 45 46 /* SDC reset register, must be pre-mapped at reset time */ 47 static void __iomem *reset_reg; 48 49 /* Various error status registers, must be pre-mapped at MCE time */ 50 51 #define MAX_MCE_REGS 32 52 struct mce_regs { 53 char *name; 54 void __iomem *addr; 55 }; 56 57 static struct mce_regs mce_regs[MAX_MCE_REGS]; 58 static int num_mce_regs; 59 60 61 static void pas_restart(char *cmd) 62 { 63 printk("Restarting...\n"); 64 while (1) 65 out_le32(reset_reg, 0x6000000); 66 } 67 68 #ifdef CONFIG_SMP 69 static DEFINE_SPINLOCK(timebase_lock); 70 static unsigned long timebase; 71 72 static void __devinit pas_give_timebase(void) 73 { 74 spin_lock(&timebase_lock); 75 mtspr(SPRN_TBCTL, TBCTL_FREEZE); 76 isync(); 77 timebase = get_tb(); 78 spin_unlock(&timebase_lock); 79 80 while (timebase) 81 barrier(); 82 mtspr(SPRN_TBCTL, TBCTL_RESTART); 83 } 84 85 static void __devinit pas_take_timebase(void) 86 { 87 while (!timebase) 88 smp_rmb(); 89 90 spin_lock(&timebase_lock); 91 set_tb(timebase >> 32, timebase & 0xffffffff); 92 timebase = 0; 93 spin_unlock(&timebase_lock); 94 } 95 96 struct smp_ops_t pas_smp_ops = { 97 .probe = smp_mpic_probe, 98 .message_pass = smp_mpic_message_pass, 99 .kick_cpu = smp_generic_kick_cpu, 100 .setup_cpu = smp_mpic_setup_cpu, 101 .give_timebase = pas_give_timebase, 102 .take_timebase = pas_take_timebase, 103 }; 104 #endif /* CONFIG_SMP */ 105 106 void __init pas_setup_arch(void) 107 { 108 #ifdef CONFIG_SMP 109 /* Setup SMP callback */ 110 smp_ops = &pas_smp_ops; 111 #endif 112 /* Lookup PCI hosts */ 113 pas_pci_init(); 114 115 #ifdef CONFIG_DUMMY_CONSOLE 116 conswitchp = &dummy_con; 117 #endif 118 119 /* Remap SDC register for doing reset */ 120 /* XXXOJN This should maybe come out of the device tree */ 121 reset_reg = ioremap(0xfc101100, 4); 122 } 123 124 static int __init pas_setup_mce_regs(void) 125 { 126 struct pci_dev *dev; 127 int reg; 128 129 if (!machine_is(pasemi)) 130 return -ENODEV; 131 132 /* Remap various SoC status registers for use by the MCE handler */ 133 134 reg = 0; 135 136 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL); 137 while (dev && reg < MAX_MCE_REGS) { 138 mce_regs[reg].name = kasprintf(GFP_KERNEL, 139 "mc%d_mcdebug_errsta", reg); 140 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); 141 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev); 142 reg++; 143 } 144 145 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 146 if (dev && reg+4 < MAX_MCE_REGS) { 147 mce_regs[reg].name = "iobdbg_IntStatus1"; 148 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); 149 reg++; 150 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; 151 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); 152 reg++; 153 mce_regs[reg].name = "iobiom_IntStatus"; 154 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); 155 reg++; 156 mce_regs[reg].name = "iobiom_IntDbgReg"; 157 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); 158 reg++; 159 } 160 161 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL); 162 if (dev && reg+2 < MAX_MCE_REGS) { 163 mce_regs[reg].name = "l2csts_IntStatus"; 164 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); 165 reg++; 166 mce_regs[reg].name = "l2csts_Cnt"; 167 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); 168 reg++; 169 } 170 171 num_mce_regs = reg; 172 173 return 0; 174 } 175 device_initcall(pas_setup_mce_regs); 176 177 static __init void pas_init_IRQ(void) 178 { 179 struct device_node *np; 180 struct device_node *root, *mpic_node; 181 unsigned long openpic_addr; 182 const unsigned int *opprop; 183 int naddr, opplen; 184 struct mpic *mpic; 185 186 mpic_node = NULL; 187 188 for_each_node_by_type(np, "interrupt-controller") 189 if (of_device_is_compatible(np, "open-pic")) { 190 mpic_node = np; 191 break; 192 } 193 if (!mpic_node) 194 for_each_node_by_type(np, "open-pic") { 195 mpic_node = np; 196 break; 197 } 198 if (!mpic_node) { 199 printk(KERN_ERR 200 "Failed to locate the MPIC interrupt controller\n"); 201 return; 202 } 203 204 /* Find address list in /platform-open-pic */ 205 root = of_find_node_by_path("/"); 206 naddr = of_n_addr_cells(root); 207 opprop = of_get_property(root, "platform-open-pic", &opplen); 208 if (!opprop) { 209 printk(KERN_ERR "No platform-open-pic property.\n"); 210 of_node_put(root); 211 return; 212 } 213 openpic_addr = of_read_number(opprop, naddr); 214 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr); 215 216 mpic = mpic_alloc(mpic_node, openpic_addr, 217 MPIC_PRIMARY|MPIC_LARGE_VECTORS|MPIC_WANTS_RESET, 218 0, 0, " PAS-OPIC "); 219 BUG_ON(!mpic); 220 221 mpic_assign_isu(mpic, 0, openpic_addr + 0x10000); 222 mpic_init(mpic); 223 of_node_put(mpic_node); 224 of_node_put(root); 225 } 226 227 static void __init pas_progress(char *s, unsigned short hex) 228 { 229 printk("[%04x] : %s\n", hex, s ? s : ""); 230 } 231 232 233 static int pas_machine_check_handler(struct pt_regs *regs) 234 { 235 int cpu = smp_processor_id(); 236 unsigned long srr0, srr1, dsisr; 237 int dump_slb = 0; 238 int i; 239 240 srr0 = regs->nip; 241 srr1 = regs->msr; 242 dsisr = mfspr(SPRN_DSISR); 243 printk(KERN_ERR "Machine Check on CPU %d\n", cpu); 244 printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); 245 printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); 246 printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER), 247 mfspr(SPRN_PA6T_MER)); 248 printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER), 249 mfspr(SPRN_PA6T_DER)); 250 printk(KERN_ERR "Cause:\n"); 251 252 if (srr1 & 0x200000) 253 printk(KERN_ERR "Signalled by SDC\n"); 254 255 if (srr1 & 0x100000) { 256 printk(KERN_ERR "Load/Store detected error:\n"); 257 if (dsisr & 0x8000) 258 printk(KERN_ERR "D-cache ECC double-bit error or bus error\n"); 259 if (dsisr & 0x4000) 260 printk(KERN_ERR "LSU snoop response error\n"); 261 if (dsisr & 0x2000) { 262 printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n"); 263 dump_slb = 1; 264 } 265 if (dsisr & 0x1000) 266 printk(KERN_ERR "Recoverable Duptags\n"); 267 if (dsisr & 0x800) 268 printk(KERN_ERR "Recoverable D-cache parity error count overflow\n"); 269 if (dsisr & 0x400) 270 printk(KERN_ERR "TLB parity error count overflow\n"); 271 } 272 273 if (srr1 & 0x80000) 274 printk(KERN_ERR "Bus Error\n"); 275 276 if (srr1 & 0x40000) { 277 printk(KERN_ERR "I-side SLB multiple hit\n"); 278 dump_slb = 1; 279 } 280 281 if (srr1 & 0x20000) 282 printk(KERN_ERR "I-cache parity error hit\n"); 283 284 if (num_mce_regs == 0) 285 printk(KERN_ERR "No MCE registers mapped yet, can't dump\n"); 286 else 287 printk(KERN_ERR "SoC debug registers:\n"); 288 289 for (i = 0; i < num_mce_regs; i++) 290 printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name, 291 in_le32(mce_regs[i].addr)); 292 293 if (dump_slb) { 294 unsigned long e, v; 295 int i; 296 297 printk(KERN_ERR "slb contents:\n"); 298 for (i = 0; i < SLB_NUM_ENTRIES; i++) { 299 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i)); 300 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i)); 301 printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v); 302 } 303 } 304 305 306 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */ 307 return !!(srr1 & 0x2); 308 } 309 310 static void __init pas_init_early(void) 311 { 312 iommu_init_early_pasemi(); 313 } 314 315 #ifdef CONFIG_PCMCIA 316 static int pcmcia_notify(struct notifier_block *nb, unsigned long action, 317 void *data) 318 { 319 struct device *dev = data; 320 struct device *parent; 321 struct pcmcia_device *pdev = to_pcmcia_dev(dev); 322 323 /* We are only intereted in device addition */ 324 if (action != BUS_NOTIFY_ADD_DEVICE) 325 return 0; 326 327 parent = pdev->socket->dev.parent; 328 329 /* We know electra_cf devices will always have of_node set, since 330 * electra_cf is an of_platform driver. 331 */ 332 if (!parent->archdata.of_node) 333 return 0; 334 335 if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf")) 336 return 0; 337 338 /* We use the direct ops for localbus */ 339 dev->archdata.dma_ops = &dma_direct_ops; 340 341 return 0; 342 } 343 344 static struct notifier_block pcmcia_notifier = { 345 .notifier_call = pcmcia_notify, 346 }; 347 348 static inline void pasemi_pcmcia_init(void) 349 { 350 extern struct bus_type pcmcia_bus_type; 351 352 bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier); 353 } 354 355 #else 356 357 static inline void pasemi_pcmcia_init(void) 358 { 359 } 360 361 #endif 362 363 364 static struct of_device_id pasemi_bus_ids[] = { 365 { .type = "localbus", }, 366 { .type = "sdc", }, 367 {}, 368 }; 369 370 static int __init pasemi_publish_devices(void) 371 { 372 if (!machine_is(pasemi)) 373 return 0; 374 375 pasemi_pcmcia_init(); 376 377 /* Publish OF platform devices for SDC and other non-PCI devices */ 378 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL); 379 380 return 0; 381 } 382 device_initcall(pasemi_publish_devices); 383 384 385 /* 386 * Called very early, MMU is off, device-tree isn't unflattened 387 */ 388 static int __init pas_probe(void) 389 { 390 unsigned long root = of_get_flat_dt_root(); 391 392 if (!of_flat_dt_is_compatible(root, "PA6T-1682M")) 393 return 0; 394 395 hpte_init_native(); 396 397 alloc_iobmap_l2(); 398 399 return 1; 400 } 401 402 define_machine(pasemi) { 403 .name = "PA Semi PA6T-1682M", 404 .probe = pas_probe, 405 .setup_arch = pas_setup_arch, 406 .init_early = pas_init_early, 407 .init_IRQ = pas_init_IRQ, 408 .get_irq = mpic_get_irq, 409 .restart = pas_restart, 410 .get_boot_time = pas_get_boot_time, 411 .calibrate_decr = generic_calibrate_decr, 412 .progress = pas_progress, 413 .machine_check_exception = pas_machine_check_handler, 414 }; 415