1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC85xx RDB Board Setup 4 * 5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/kdev_t.h> 12 #include <linux/delay.h> 13 #include <linux/seq_file.h> 14 #include <linux/interrupt.h> 15 #include <linux/of_platform.h> 16 #include <linux/fsl/guts.h> 17 18 #include <asm/time.h> 19 #include <asm/machdep.h> 20 #include <asm/pci-bridge.h> 21 #include <mm/mmu_decl.h> 22 #include <asm/udbg.h> 23 #include <asm/mpic.h> 24 #include <soc/fsl/qe/qe.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include "smp.h" 29 30 #include "mpc85xx.h" 31 32 void __init mpc85xx_rdb_pic_init(void) 33 { 34 struct mpic *mpic; 35 int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU; 36 37 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) 38 flags |= MPIC_NO_RESET; 39 40 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC "); 41 42 if (WARN_ON(!mpic)) 43 return; 44 45 mpic_init(mpic); 46 } 47 48 /* 49 * Setup the architecture 50 */ 51 static void __init mpc85xx_rdb_setup_arch(void) 52 { 53 if (ppc_md.progress) 54 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 55 56 mpc85xx_smp_init(); 57 58 fsl_pci_assign_primary(); 59 60 mpc85xx_qe_par_io_init(); 61 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 62 if (machine_is(p1025_rdb)) { 63 struct device_node *np; 64 65 struct ccsr_guts __iomem *guts; 66 67 np = of_find_node_by_name(NULL, "global-utilities"); 68 if (np) { 69 guts = of_iomap(np, 0); 70 if (!guts) { 71 72 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 73 74 } else { 75 /* P1025 has pins muxed for QE and other functions. To 76 * enable QE UEC mode, we need to set bit QE0 for UCC1 77 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 78 * and QE12 for QE MII management singals in PMUXCR 79 * register. 80 */ 81 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 82 MPC85xx_PMUXCR_QE(3) | 83 MPC85xx_PMUXCR_QE(9) | 84 MPC85xx_PMUXCR_QE(12)); 85 iounmap(guts); 86 } 87 of_node_put(np); 88 } 89 90 } 91 #endif 92 93 pr_info("MPC85xx RDB board from Freescale Semiconductor\n"); 94 } 95 96 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 97 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 98 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 99 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 100 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 101 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 102 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 103 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 104 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 105 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 106 107 define_machine(p2020_rdb) { 108 .name = "P2020 RDB", 109 .compatible = "fsl,P2020RDB", 110 .setup_arch = mpc85xx_rdb_setup_arch, 111 .init_IRQ = mpc85xx_rdb_pic_init, 112 #ifdef CONFIG_PCI 113 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 114 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 115 #endif 116 .get_irq = mpic_get_irq, 117 .progress = udbg_progress, 118 }; 119 120 define_machine(p1020_rdb) { 121 .name = "P1020 RDB", 122 .compatible = "fsl,P1020RDB", 123 .setup_arch = mpc85xx_rdb_setup_arch, 124 .init_IRQ = mpc85xx_rdb_pic_init, 125 #ifdef CONFIG_PCI 126 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 127 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 128 #endif 129 .get_irq = mpic_get_irq, 130 .progress = udbg_progress, 131 }; 132 133 define_machine(p1021_rdb_pc) { 134 .name = "P1021 RDB-PC", 135 .compatible = "fsl,P1021RDB-PC", 136 .setup_arch = mpc85xx_rdb_setup_arch, 137 .init_IRQ = mpc85xx_rdb_pic_init, 138 #ifdef CONFIG_PCI 139 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 140 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 141 #endif 142 .get_irq = mpic_get_irq, 143 .progress = udbg_progress, 144 }; 145 146 define_machine(p2020_rdb_pc) { 147 .name = "P2020RDB-PC", 148 .compatible = "fsl,P2020RDB-PC", 149 .setup_arch = mpc85xx_rdb_setup_arch, 150 .init_IRQ = mpc85xx_rdb_pic_init, 151 #ifdef CONFIG_PCI 152 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 153 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 154 #endif 155 .get_irq = mpic_get_irq, 156 .progress = udbg_progress, 157 }; 158 159 define_machine(p1025_rdb) { 160 .name = "P1025 RDB", 161 .compatible = "fsl,P1025RDB", 162 .setup_arch = mpc85xx_rdb_setup_arch, 163 .init_IRQ = mpc85xx_rdb_pic_init, 164 #ifdef CONFIG_PCI 165 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 166 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 167 #endif 168 .get_irq = mpic_get_irq, 169 .progress = udbg_progress, 170 }; 171 172 define_machine(p1020_mbg_pc) { 173 .name = "P1020 MBG-PC", 174 .compatible = "fsl,P1020MBG-PC", 175 .setup_arch = mpc85xx_rdb_setup_arch, 176 .init_IRQ = mpc85xx_rdb_pic_init, 177 #ifdef CONFIG_PCI 178 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 179 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 180 #endif 181 .get_irq = mpic_get_irq, 182 .progress = udbg_progress, 183 }; 184 185 define_machine(p1020_utm_pc) { 186 .name = "P1020 UTM-PC", 187 .compatible = "fsl,P1020UTM-PC", 188 .setup_arch = mpc85xx_rdb_setup_arch, 189 .init_IRQ = mpc85xx_rdb_pic_init, 190 #ifdef CONFIG_PCI 191 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 192 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 193 #endif 194 .get_irq = mpic_get_irq, 195 .progress = udbg_progress, 196 }; 197 198 define_machine(p1020_rdb_pc) { 199 .name = "P1020RDB-PC", 200 .compatible = "fsl,P1020RDB-PC", 201 .setup_arch = mpc85xx_rdb_setup_arch, 202 .init_IRQ = mpc85xx_rdb_pic_init, 203 #ifdef CONFIG_PCI 204 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 205 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 206 #endif 207 .get_irq = mpic_get_irq, 208 .progress = udbg_progress, 209 }; 210 211 define_machine(p1020_rdb_pd) { 212 .name = "P1020RDB-PD", 213 .compatible = "fsl,P1020RDB-PD", 214 .setup_arch = mpc85xx_rdb_setup_arch, 215 .init_IRQ = mpc85xx_rdb_pic_init, 216 #ifdef CONFIG_PCI 217 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 218 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 219 #endif 220 .get_irq = mpic_get_irq, 221 .progress = udbg_progress, 222 }; 223 224 define_machine(p1024_rdb) { 225 .name = "P1024 RDB", 226 .compatible = "fsl,P1024RDB", 227 .setup_arch = mpc85xx_rdb_setup_arch, 228 .init_IRQ = mpc85xx_rdb_pic_init, 229 #ifdef CONFIG_PCI 230 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 231 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 232 #endif 233 .get_irq = mpic_get_irq, 234 .progress = udbg_progress, 235 }; 236