1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC85xx RDB Board Setup 4 * 5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/kdev_t.h> 12 #include <linux/delay.h> 13 #include <linux/seq_file.h> 14 #include <linux/interrupt.h> 15 #include <linux/of_platform.h> 16 #include <linux/fsl/guts.h> 17 18 #include <asm/time.h> 19 #include <asm/machdep.h> 20 #include <asm/pci-bridge.h> 21 #include <mm/mmu_decl.h> 22 #include <asm/udbg.h> 23 #include <asm/mpic.h> 24 #include <soc/fsl/qe/qe.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include "smp.h" 29 30 #include "mpc85xx.h" 31 32 void __init mpc85xx_rdb_pic_init(void) 33 { 34 struct mpic *mpic; 35 36 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) { 37 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | 38 MPIC_BIG_ENDIAN | 39 MPIC_SINGLE_DEST_CPU, 40 0, 256, " OpenPIC "); 41 } else { 42 mpic = mpic_alloc(NULL, 0, 43 MPIC_BIG_ENDIAN | 44 MPIC_SINGLE_DEST_CPU, 45 0, 256, " OpenPIC "); 46 } 47 48 BUG_ON(mpic == NULL); 49 mpic_init(mpic); 50 } 51 52 /* 53 * Setup the architecture 54 */ 55 static void __init mpc85xx_rdb_setup_arch(void) 56 { 57 if (ppc_md.progress) 58 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 59 60 mpc85xx_smp_init(); 61 62 fsl_pci_assign_primary(); 63 64 #ifdef CONFIG_QUICC_ENGINE 65 mpc85xx_qe_par_io_init(); 66 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 67 if (machine_is(p1025_rdb)) { 68 struct device_node *np; 69 70 struct ccsr_guts __iomem *guts; 71 72 np = of_find_node_by_name(NULL, "global-utilities"); 73 if (np) { 74 guts = of_iomap(np, 0); 75 if (!guts) { 76 77 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 78 79 } else { 80 /* P1025 has pins muxed for QE and other functions. To 81 * enable QE UEC mode, we need to set bit QE0 for UCC1 82 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 83 * and QE12 for QE MII management singals in PMUXCR 84 * register. 85 */ 86 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 87 MPC85xx_PMUXCR_QE(3) | 88 MPC85xx_PMUXCR_QE(9) | 89 MPC85xx_PMUXCR_QE(12)); 90 iounmap(guts); 91 } 92 of_node_put(np); 93 } 94 95 } 96 #endif 97 #endif /* CONFIG_QUICC_ENGINE */ 98 99 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 100 } 101 102 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 103 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 104 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 105 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 106 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 107 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 108 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 109 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 110 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 111 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 112 113 define_machine(p2020_rdb) { 114 .name = "P2020 RDB", 115 .compatible = "fsl,P2020RDB", 116 .setup_arch = mpc85xx_rdb_setup_arch, 117 .init_IRQ = mpc85xx_rdb_pic_init, 118 #ifdef CONFIG_PCI 119 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 120 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 121 #endif 122 .get_irq = mpic_get_irq, 123 .progress = udbg_progress, 124 }; 125 126 define_machine(p1020_rdb) { 127 .name = "P1020 RDB", 128 .compatible = "fsl,P1020RDB", 129 .setup_arch = mpc85xx_rdb_setup_arch, 130 .init_IRQ = mpc85xx_rdb_pic_init, 131 #ifdef CONFIG_PCI 132 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 133 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 134 #endif 135 .get_irq = mpic_get_irq, 136 .progress = udbg_progress, 137 }; 138 139 define_machine(p1021_rdb_pc) { 140 .name = "P1021 RDB-PC", 141 .compatible = "fsl,P1021RDB-PC", 142 .setup_arch = mpc85xx_rdb_setup_arch, 143 .init_IRQ = mpc85xx_rdb_pic_init, 144 #ifdef CONFIG_PCI 145 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 146 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 147 #endif 148 .get_irq = mpic_get_irq, 149 .progress = udbg_progress, 150 }; 151 152 define_machine(p2020_rdb_pc) { 153 .name = "P2020RDB-PC", 154 .compatible = "fsl,P2020RDB-PC", 155 .setup_arch = mpc85xx_rdb_setup_arch, 156 .init_IRQ = mpc85xx_rdb_pic_init, 157 #ifdef CONFIG_PCI 158 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 159 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 160 #endif 161 .get_irq = mpic_get_irq, 162 .progress = udbg_progress, 163 }; 164 165 define_machine(p1025_rdb) { 166 .name = "P1025 RDB", 167 .compatible = "fsl,P1025RDB", 168 .setup_arch = mpc85xx_rdb_setup_arch, 169 .init_IRQ = mpc85xx_rdb_pic_init, 170 #ifdef CONFIG_PCI 171 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 172 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 173 #endif 174 .get_irq = mpic_get_irq, 175 .progress = udbg_progress, 176 }; 177 178 define_machine(p1020_mbg_pc) { 179 .name = "P1020 MBG-PC", 180 .compatible = "fsl,P1020MBG-PC", 181 .setup_arch = mpc85xx_rdb_setup_arch, 182 .init_IRQ = mpc85xx_rdb_pic_init, 183 #ifdef CONFIG_PCI 184 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 185 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 186 #endif 187 .get_irq = mpic_get_irq, 188 .progress = udbg_progress, 189 }; 190 191 define_machine(p1020_utm_pc) { 192 .name = "P1020 UTM-PC", 193 .compatible = "fsl,P1020UTM-PC", 194 .setup_arch = mpc85xx_rdb_setup_arch, 195 .init_IRQ = mpc85xx_rdb_pic_init, 196 #ifdef CONFIG_PCI 197 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 198 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 199 #endif 200 .get_irq = mpic_get_irq, 201 .progress = udbg_progress, 202 }; 203 204 define_machine(p1020_rdb_pc) { 205 .name = "P1020RDB-PC", 206 .compatible = "fsl,P1020RDB-PC", 207 .setup_arch = mpc85xx_rdb_setup_arch, 208 .init_IRQ = mpc85xx_rdb_pic_init, 209 #ifdef CONFIG_PCI 210 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 211 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 212 #endif 213 .get_irq = mpic_get_irq, 214 .progress = udbg_progress, 215 }; 216 217 define_machine(p1020_rdb_pd) { 218 .name = "P1020RDB-PD", 219 .compatible = "fsl,P1020RDB-PD", 220 .setup_arch = mpc85xx_rdb_setup_arch, 221 .init_IRQ = mpc85xx_rdb_pic_init, 222 #ifdef CONFIG_PCI 223 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 224 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 225 #endif 226 .get_irq = mpic_get_irq, 227 .progress = udbg_progress, 228 }; 229 230 define_machine(p1024_rdb) { 231 .name = "P1024 RDB", 232 .compatible = "fsl,P1024RDB", 233 .setup_arch = mpc85xx_rdb_setup_arch, 234 .init_IRQ = mpc85xx_rdb_pic_init, 235 #ifdef CONFIG_PCI 236 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 237 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 238 #endif 239 .get_irq = mpic_get_irq, 240 .progress = udbg_progress, 241 }; 242