1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC85xx RDB Board Setup 4 * 5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/kdev_t.h> 12 #include <linux/delay.h> 13 #include <linux/seq_file.h> 14 #include <linux/interrupt.h> 15 #include <linux/of_platform.h> 16 #include <linux/fsl/guts.h> 17 18 #include <asm/time.h> 19 #include <asm/machdep.h> 20 #include <asm/pci-bridge.h> 21 #include <mm/mmu_decl.h> 22 #include <asm/udbg.h> 23 #include <asm/mpic.h> 24 #include <soc/fsl/qe/qe.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include "smp.h" 29 30 #include "mpc85xx.h" 31 32 #undef DEBUG 33 34 #ifdef DEBUG 35 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 36 #else 37 #define DBG(fmt, args...) 38 #endif 39 40 41 void __init mpc85xx_rdb_pic_init(void) 42 { 43 struct mpic *mpic; 44 45 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) { 46 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | 47 MPIC_BIG_ENDIAN | 48 MPIC_SINGLE_DEST_CPU, 49 0, 256, " OpenPIC "); 50 } else { 51 mpic = mpic_alloc(NULL, 0, 52 MPIC_BIG_ENDIAN | 53 MPIC_SINGLE_DEST_CPU, 54 0, 256, " OpenPIC "); 55 } 56 57 BUG_ON(mpic == NULL); 58 mpic_init(mpic); 59 } 60 61 /* 62 * Setup the architecture 63 */ 64 static void __init mpc85xx_rdb_setup_arch(void) 65 { 66 if (ppc_md.progress) 67 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 68 69 mpc85xx_smp_init(); 70 71 fsl_pci_assign_primary(); 72 73 #ifdef CONFIG_QUICC_ENGINE 74 mpc85xx_qe_par_io_init(); 75 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 76 if (machine_is(p1025_rdb)) { 77 struct device_node *np; 78 79 struct ccsr_guts __iomem *guts; 80 81 np = of_find_node_by_name(NULL, "global-utilities"); 82 if (np) { 83 guts = of_iomap(np, 0); 84 if (!guts) { 85 86 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 87 88 } else { 89 /* P1025 has pins muxed for QE and other functions. To 90 * enable QE UEC mode, we need to set bit QE0 for UCC1 91 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 92 * and QE12 for QE MII management singals in PMUXCR 93 * register. 94 */ 95 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 96 MPC85xx_PMUXCR_QE(3) | 97 MPC85xx_PMUXCR_QE(9) | 98 MPC85xx_PMUXCR_QE(12)); 99 iounmap(guts); 100 } 101 of_node_put(np); 102 } 103 104 } 105 #endif 106 #endif /* CONFIG_QUICC_ENGINE */ 107 108 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 109 } 110 111 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 112 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 113 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 114 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 115 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 116 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 117 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 118 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 119 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 120 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 121 122 define_machine(p2020_rdb) { 123 .name = "P2020 RDB", 124 .compatible = "fsl,P2020RDB", 125 .setup_arch = mpc85xx_rdb_setup_arch, 126 .init_IRQ = mpc85xx_rdb_pic_init, 127 #ifdef CONFIG_PCI 128 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 129 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 130 #endif 131 .get_irq = mpic_get_irq, 132 .calibrate_decr = generic_calibrate_decr, 133 .progress = udbg_progress, 134 }; 135 136 define_machine(p1020_rdb) { 137 .name = "P1020 RDB", 138 .compatible = "fsl,P1020RDB", 139 .setup_arch = mpc85xx_rdb_setup_arch, 140 .init_IRQ = mpc85xx_rdb_pic_init, 141 #ifdef CONFIG_PCI 142 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 143 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 144 #endif 145 .get_irq = mpic_get_irq, 146 .calibrate_decr = generic_calibrate_decr, 147 .progress = udbg_progress, 148 }; 149 150 define_machine(p1021_rdb_pc) { 151 .name = "P1021 RDB-PC", 152 .compatible = "fsl,P1021RDB-PC", 153 .setup_arch = mpc85xx_rdb_setup_arch, 154 .init_IRQ = mpc85xx_rdb_pic_init, 155 #ifdef CONFIG_PCI 156 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 157 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 158 #endif 159 .get_irq = mpic_get_irq, 160 .calibrate_decr = generic_calibrate_decr, 161 .progress = udbg_progress, 162 }; 163 164 define_machine(p2020_rdb_pc) { 165 .name = "P2020RDB-PC", 166 .compatible = "fsl,P2020RDB-PC", 167 .setup_arch = mpc85xx_rdb_setup_arch, 168 .init_IRQ = mpc85xx_rdb_pic_init, 169 #ifdef CONFIG_PCI 170 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 171 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 172 #endif 173 .get_irq = mpic_get_irq, 174 .calibrate_decr = generic_calibrate_decr, 175 .progress = udbg_progress, 176 }; 177 178 define_machine(p1025_rdb) { 179 .name = "P1025 RDB", 180 .compatible = "fsl,P1025RDB", 181 .setup_arch = mpc85xx_rdb_setup_arch, 182 .init_IRQ = mpc85xx_rdb_pic_init, 183 #ifdef CONFIG_PCI 184 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 185 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 186 #endif 187 .get_irq = mpic_get_irq, 188 .calibrate_decr = generic_calibrate_decr, 189 .progress = udbg_progress, 190 }; 191 192 define_machine(p1020_mbg_pc) { 193 .name = "P1020 MBG-PC", 194 .compatible = "fsl,P1020MBG-PC", 195 .setup_arch = mpc85xx_rdb_setup_arch, 196 .init_IRQ = mpc85xx_rdb_pic_init, 197 #ifdef CONFIG_PCI 198 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 199 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 200 #endif 201 .get_irq = mpic_get_irq, 202 .calibrate_decr = generic_calibrate_decr, 203 .progress = udbg_progress, 204 }; 205 206 define_machine(p1020_utm_pc) { 207 .name = "P1020 UTM-PC", 208 .compatible = "fsl,P1020UTM-PC", 209 .setup_arch = mpc85xx_rdb_setup_arch, 210 .init_IRQ = mpc85xx_rdb_pic_init, 211 #ifdef CONFIG_PCI 212 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 213 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 214 #endif 215 .get_irq = mpic_get_irq, 216 .calibrate_decr = generic_calibrate_decr, 217 .progress = udbg_progress, 218 }; 219 220 define_machine(p1020_rdb_pc) { 221 .name = "P1020RDB-PC", 222 .compatible = "fsl,P1020RDB-PC", 223 .setup_arch = mpc85xx_rdb_setup_arch, 224 .init_IRQ = mpc85xx_rdb_pic_init, 225 #ifdef CONFIG_PCI 226 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 227 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 228 #endif 229 .get_irq = mpic_get_irq, 230 .calibrate_decr = generic_calibrate_decr, 231 .progress = udbg_progress, 232 }; 233 234 define_machine(p1020_rdb_pd) { 235 .name = "P1020RDB-PD", 236 .compatible = "fsl,P1020RDB-PD", 237 .setup_arch = mpc85xx_rdb_setup_arch, 238 .init_IRQ = mpc85xx_rdb_pic_init, 239 #ifdef CONFIG_PCI 240 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 241 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 242 #endif 243 .get_irq = mpic_get_irq, 244 .calibrate_decr = generic_calibrate_decr, 245 .progress = udbg_progress, 246 }; 247 248 define_machine(p1024_rdb) { 249 .name = "P1024 RDB", 250 .compatible = "fsl,P1024RDB", 251 .setup_arch = mpc85xx_rdb_setup_arch, 252 .init_IRQ = mpc85xx_rdb_pic_init, 253 #ifdef CONFIG_PCI 254 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 255 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 256 #endif 257 .get_irq = mpic_get_irq, 258 .calibrate_decr = generic_calibrate_decr, 259 .progress = udbg_progress, 260 }; 261