1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC85xx RDB Board Setup 4 * 5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/kdev_t.h> 12 #include <linux/delay.h> 13 #include <linux/seq_file.h> 14 #include <linux/interrupt.h> 15 #include <linux/of_platform.h> 16 #include <linux/fsl/guts.h> 17 18 #include <asm/time.h> 19 #include <asm/machdep.h> 20 #include <asm/pci-bridge.h> 21 #include <mm/mmu_decl.h> 22 #include <asm/udbg.h> 23 #include <asm/mpic.h> 24 #include <soc/fsl/qe/qe.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include "smp.h" 29 30 #include "mpc85xx.h" 31 32 void __init mpc85xx_rdb_pic_init(void) 33 { 34 struct mpic *mpic; 35 int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU; 36 37 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) 38 flags |= MPIC_NO_RESET; 39 40 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC "); 41 42 if (WARN_ON(!mpic)) 43 return; 44 45 mpic_init(mpic); 46 } 47 48 /* 49 * Setup the architecture 50 */ 51 static void __init mpc85xx_rdb_setup_arch(void) 52 { 53 if (ppc_md.progress) 54 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 55 56 mpc85xx_smp_init(); 57 58 fsl_pci_assign_primary(); 59 60 #ifdef CONFIG_QUICC_ENGINE 61 mpc85xx_qe_par_io_init(); 62 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 63 if (machine_is(p1025_rdb)) { 64 struct device_node *np; 65 66 struct ccsr_guts __iomem *guts; 67 68 np = of_find_node_by_name(NULL, "global-utilities"); 69 if (np) { 70 guts = of_iomap(np, 0); 71 if (!guts) { 72 73 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 74 75 } else { 76 /* P1025 has pins muxed for QE and other functions. To 77 * enable QE UEC mode, we need to set bit QE0 for UCC1 78 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 79 * and QE12 for QE MII management singals in PMUXCR 80 * register. 81 */ 82 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 83 MPC85xx_PMUXCR_QE(3) | 84 MPC85xx_PMUXCR_QE(9) | 85 MPC85xx_PMUXCR_QE(12)); 86 iounmap(guts); 87 } 88 of_node_put(np); 89 } 90 91 } 92 #endif 93 #endif /* CONFIG_QUICC_ENGINE */ 94 95 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 96 } 97 98 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 99 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 100 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 101 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 102 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 103 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 104 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 105 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 106 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 107 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 108 109 define_machine(p2020_rdb) { 110 .name = "P2020 RDB", 111 .compatible = "fsl,P2020RDB", 112 .setup_arch = mpc85xx_rdb_setup_arch, 113 .init_IRQ = mpc85xx_rdb_pic_init, 114 #ifdef CONFIG_PCI 115 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 116 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 117 #endif 118 .get_irq = mpic_get_irq, 119 .progress = udbg_progress, 120 }; 121 122 define_machine(p1020_rdb) { 123 .name = "P1020 RDB", 124 .compatible = "fsl,P1020RDB", 125 .setup_arch = mpc85xx_rdb_setup_arch, 126 .init_IRQ = mpc85xx_rdb_pic_init, 127 #ifdef CONFIG_PCI 128 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 129 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 130 #endif 131 .get_irq = mpic_get_irq, 132 .progress = udbg_progress, 133 }; 134 135 define_machine(p1021_rdb_pc) { 136 .name = "P1021 RDB-PC", 137 .compatible = "fsl,P1021RDB-PC", 138 .setup_arch = mpc85xx_rdb_setup_arch, 139 .init_IRQ = mpc85xx_rdb_pic_init, 140 #ifdef CONFIG_PCI 141 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 142 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 143 #endif 144 .get_irq = mpic_get_irq, 145 .progress = udbg_progress, 146 }; 147 148 define_machine(p2020_rdb_pc) { 149 .name = "P2020RDB-PC", 150 .compatible = "fsl,P2020RDB-PC", 151 .setup_arch = mpc85xx_rdb_setup_arch, 152 .init_IRQ = mpc85xx_rdb_pic_init, 153 #ifdef CONFIG_PCI 154 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 155 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 156 #endif 157 .get_irq = mpic_get_irq, 158 .progress = udbg_progress, 159 }; 160 161 define_machine(p1025_rdb) { 162 .name = "P1025 RDB", 163 .compatible = "fsl,P1025RDB", 164 .setup_arch = mpc85xx_rdb_setup_arch, 165 .init_IRQ = mpc85xx_rdb_pic_init, 166 #ifdef CONFIG_PCI 167 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 168 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 169 #endif 170 .get_irq = mpic_get_irq, 171 .progress = udbg_progress, 172 }; 173 174 define_machine(p1020_mbg_pc) { 175 .name = "P1020 MBG-PC", 176 .compatible = "fsl,P1020MBG-PC", 177 .setup_arch = mpc85xx_rdb_setup_arch, 178 .init_IRQ = mpc85xx_rdb_pic_init, 179 #ifdef CONFIG_PCI 180 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 181 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 182 #endif 183 .get_irq = mpic_get_irq, 184 .progress = udbg_progress, 185 }; 186 187 define_machine(p1020_utm_pc) { 188 .name = "P1020 UTM-PC", 189 .compatible = "fsl,P1020UTM-PC", 190 .setup_arch = mpc85xx_rdb_setup_arch, 191 .init_IRQ = mpc85xx_rdb_pic_init, 192 #ifdef CONFIG_PCI 193 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 194 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 195 #endif 196 .get_irq = mpic_get_irq, 197 .progress = udbg_progress, 198 }; 199 200 define_machine(p1020_rdb_pc) { 201 .name = "P1020RDB-PC", 202 .compatible = "fsl,P1020RDB-PC", 203 .setup_arch = mpc85xx_rdb_setup_arch, 204 .init_IRQ = mpc85xx_rdb_pic_init, 205 #ifdef CONFIG_PCI 206 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 207 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 208 #endif 209 .get_irq = mpic_get_irq, 210 .progress = udbg_progress, 211 }; 212 213 define_machine(p1020_rdb_pd) { 214 .name = "P1020RDB-PD", 215 .compatible = "fsl,P1020RDB-PD", 216 .setup_arch = mpc85xx_rdb_setup_arch, 217 .init_IRQ = mpc85xx_rdb_pic_init, 218 #ifdef CONFIG_PCI 219 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 220 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 221 #endif 222 .get_irq = mpic_get_irq, 223 .progress = udbg_progress, 224 }; 225 226 define_machine(p1024_rdb) { 227 .name = "P1024 RDB", 228 .compatible = "fsl,P1024RDB", 229 .setup_arch = mpc85xx_rdb_setup_arch, 230 .init_IRQ = mpc85xx_rdb_pic_init, 231 #ifdef CONFIG_PCI 232 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 233 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 234 #endif 235 .get_irq = mpic_get_irq, 236 .progress = udbg_progress, 237 }; 238