1 /* 2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved. 3 * 4 * Author: Andy Fleming <afleming@freescale.com> 5 * 6 * Based on 83xx/mpc8360e_pb.c by: 7 * Li Yang <LeoLi@freescale.com> 8 * Yin Olivia <Hong-hua.Yin@freescale.com> 9 * 10 * Description: 11 * MPC85xx MDS board specific routines. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 19 #include <linux/stddef.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/reboot.h> 24 #include <linux/pci.h> 25 #include <linux/kdev_t.h> 26 #include <linux/major.h> 27 #include <linux/console.h> 28 #include <linux/delay.h> 29 #include <linux/seq_file.h> 30 #include <linux/initrd.h> 31 #include <linux/module.h> 32 #include <linux/fsl_devices.h> 33 34 #include <asm/of_device.h> 35 #include <asm/of_platform.h> 36 #include <asm/system.h> 37 #include <asm/atomic.h> 38 #include <asm/time.h> 39 #include <asm/io.h> 40 #include <asm/machdep.h> 41 #include <asm/pci-bridge.h> 42 #include <asm/irq.h> 43 #include <mm/mmu_decl.h> 44 #include <asm/prom.h> 45 #include <asm/udbg.h> 46 #include <sysdev/fsl_soc.h> 47 #include <sysdev/fsl_pci.h> 48 #include <asm/qe.h> 49 #include <asm/qe_ic.h> 50 #include <asm/mpic.h> 51 52 #undef DEBUG 53 #ifdef DEBUG 54 #define DBG(fmt...) udbg_printf(fmt) 55 #else 56 #define DBG(fmt...) 57 #endif 58 59 /* ************************************************************************ 60 * 61 * Setup the architecture 62 * 63 */ 64 static void __init mpc85xx_mds_setup_arch(void) 65 { 66 struct device_node *np; 67 static u8 *bcsr_regs = NULL; 68 69 if (ppc_md.progress) 70 ppc_md.progress("mpc85xx_mds_setup_arch()", 0); 71 72 /* Map BCSR area */ 73 np = of_find_node_by_name(NULL, "bcsr"); 74 if (np != NULL) { 75 struct resource res; 76 77 of_address_to_resource(np, 0, &res); 78 bcsr_regs = ioremap(res.start, res.end - res.start +1); 79 of_node_put(np); 80 } 81 82 #ifdef CONFIG_PCI 83 for_each_node_by_type(np, "pci") { 84 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 85 of_device_is_compatible(np, "fsl,mpc8548-pcie")) { 86 struct resource rsrc; 87 of_address_to_resource(np, 0, &rsrc); 88 if ((rsrc.start & 0xfffff) == 0x8000) 89 fsl_add_bridge(np, 1); 90 else 91 fsl_add_bridge(np, 0); 92 } 93 } 94 #endif 95 96 #ifdef CONFIG_QUICC_ENGINE 97 if ((np = of_find_node_by_name(NULL, "qe")) != NULL) { 98 qe_reset(); 99 of_node_put(np); 100 } 101 102 if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { 103 struct device_node *ucc = NULL; 104 105 par_io_init(np); 106 of_node_put(np); 107 108 for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;) 109 par_io_of_config(ucc); 110 111 of_node_put(ucc); 112 } 113 114 if (bcsr_regs) { 115 #define BCSR_UCC1_GETH_EN (0x1 << 7) 116 #define BCSR_UCC2_GETH_EN (0x1 << 7) 117 #define BCSR_UCC1_MODE_MSK (0x3 << 4) 118 #define BCSR_UCC2_MODE_MSK (0x3 << 0) 119 120 /* Turn off UCC1 & UCC2 */ 121 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 122 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 123 124 /* Mode is RGMII, all bits clear */ 125 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | 126 BCSR_UCC2_MODE_MSK); 127 128 /* Turn UCC1 & UCC2 on */ 129 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 130 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 131 132 iounmap(bcsr_regs); 133 } 134 135 #endif /* CONFIG_QUICC_ENGINE */ 136 } 137 138 static struct of_device_id mpc85xx_ids[] = { 139 { .type = "soc", }, 140 { .compatible = "soc", }, 141 { .type = "qe", }, 142 {}, 143 }; 144 145 static int __init mpc85xx_publish_devices(void) 146 { 147 if (!machine_is(mpc85xx_mds)) 148 return 0; 149 150 /* Publish the QE devices */ 151 of_platform_bus_probe(NULL,mpc85xx_ids,NULL); 152 153 return 0; 154 } 155 device_initcall(mpc85xx_publish_devices); 156 157 static void __init mpc85xx_mds_pic_init(void) 158 { 159 struct mpic *mpic; 160 struct resource r; 161 struct device_node *np = NULL; 162 163 np = of_find_node_by_type(NULL, "open-pic"); 164 if (!np) 165 return; 166 167 if (of_address_to_resource(np, 0, &r)) { 168 printk(KERN_ERR "Failed to map mpic register space\n"); 169 of_node_put(np); 170 return; 171 } 172 173 mpic = mpic_alloc(np, r.start, 174 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 175 0, 256, " OpenPIC "); 176 BUG_ON(mpic == NULL); 177 of_node_put(np); 178 179 mpic_init(mpic); 180 181 #ifdef CONFIG_QUICC_ENGINE 182 np = of_find_node_by_type(NULL, "qeic"); 183 if (!np) 184 return; 185 186 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); 187 of_node_put(np); 188 #endif /* CONFIG_QUICC_ENGINE */ 189 } 190 191 static int __init mpc85xx_mds_probe(void) 192 { 193 unsigned long root = of_get_flat_dt_root(); 194 195 return of_flat_dt_is_compatible(root, "MPC85xxMDS"); 196 } 197 198 define_machine(mpc85xx_mds) { 199 .name = "MPC85xx MDS", 200 .probe = mpc85xx_mds_probe, 201 .setup_arch = mpc85xx_mds_setup_arch, 202 .init_IRQ = mpc85xx_mds_pic_init, 203 .get_irq = mpic_get_irq, 204 .restart = fsl_rstcr_restart, 205 .calibrate_decr = generic_calibrate_decr, 206 .progress = udbg_progress, 207 #ifdef CONFIG_PCI 208 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 209 #endif 210 }; 211