12874c5fdSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-or-later */ 217312f25SChristophe Leroy/* 317312f25SChristophe Leroy * PowerPC version 417312f25SChristophe Leroy * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 517312f25SChristophe Leroy * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 617312f25SChristophe Leroy * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 717312f25SChristophe Leroy * Adapted for Power Macintosh by Paul Mackerras. 817312f25SChristophe Leroy * Low-level exception handlers and MMU support 917312f25SChristophe Leroy * rewritten by Paul Mackerras. 1017312f25SChristophe Leroy * Copyright (C) 1996 Paul Mackerras. 1117312f25SChristophe Leroy * 1217312f25SChristophe Leroy * This file contains low-level assembler routines for managing 1317312f25SChristophe Leroy * the PowerPC MMU hash table. (PPC 8xx processors don't use a 1417312f25SChristophe Leroy * hash table, so this file is not used on them.) 1517312f25SChristophe Leroy */ 1617312f25SChristophe Leroy 1717312f25SChristophe Leroy#include <asm/reg.h> 1817312f25SChristophe Leroy#include <asm/page.h> 1917312f25SChristophe Leroy#include <asm/pgtable.h> 2017312f25SChristophe Leroy#include <asm/cputable.h> 2117312f25SChristophe Leroy#include <asm/ppc_asm.h> 2217312f25SChristophe Leroy#include <asm/thread_info.h> 2317312f25SChristophe Leroy#include <asm/asm-offsets.h> 2417312f25SChristophe Leroy#include <asm/export.h> 2517312f25SChristophe Leroy#include <asm/feature-fixups.h> 2617312f25SChristophe Leroy#include <asm/code-patching-asm.h> 2717312f25SChristophe Leroy 28cd08f109SChristophe Leroy#ifdef CONFIG_VMAP_STACK 29cd08f109SChristophe Leroy#define ADDR_OFFSET 0 30cd08f109SChristophe Leroy#else 31cd08f109SChristophe Leroy#define ADDR_OFFSET PAGE_OFFSET 32cd08f109SChristophe Leroy#endif 33cd08f109SChristophe Leroy 3417312f25SChristophe Leroy#ifdef CONFIG_SMP 3517312f25SChristophe Leroy .section .bss 3617312f25SChristophe Leroy .align 2 3717312f25SChristophe Leroymmu_hash_lock: 3817312f25SChristophe Leroy .space 4 3917312f25SChristophe Leroy#endif /* CONFIG_SMP */ 4017312f25SChristophe Leroy 4117312f25SChristophe Leroy/* 4217312f25SChristophe Leroy * Load a PTE into the hash table, if possible. 4317312f25SChristophe Leroy * The address is in r4, and r3 contains an access flag: 4417312f25SChristophe Leroy * _PAGE_RW (0x400) if a write. 4517312f25SChristophe Leroy * r9 contains the SRR1 value, from which we use the MSR_PR bit. 4617312f25SChristophe Leroy * SPRG_THREAD contains the physical address of the current task's thread. 4717312f25SChristophe Leroy * 4817312f25SChristophe Leroy * Returns to the caller if the access is illegal or there is no 4917312f25SChristophe Leroy * mapping for the address. Otherwise it places an appropriate PTE 5017312f25SChristophe Leroy * in the hash table and returns from the exception. 5117312f25SChristophe Leroy * Uses r0, r3 - r6, r8, r10, ctr, lr. 5217312f25SChristophe Leroy */ 5317312f25SChristophe Leroy .text 5417312f25SChristophe Leroy_GLOBAL(hash_page) 5517312f25SChristophe Leroy#ifdef CONFIG_SMP 56cd08f109SChristophe Leroy lis r8, (mmu_hash_lock - ADDR_OFFSET)@h 57cd08f109SChristophe Leroy ori r8, r8, (mmu_hash_lock - ADDR_OFFSET)@l 5817312f25SChristophe Leroy lis r0,0x0fff 5917312f25SChristophe Leroy b 10f 6017312f25SChristophe Leroy11: lwz r6,0(r8) 6117312f25SChristophe Leroy cmpwi 0,r6,0 6217312f25SChristophe Leroy bne 11b 6317312f25SChristophe Leroy10: lwarx r6,0,r8 6417312f25SChristophe Leroy cmpwi 0,r6,0 6517312f25SChristophe Leroy bne- 11b 6617312f25SChristophe Leroy stwcx. r0,0,r8 6717312f25SChristophe Leroy bne- 10b 6817312f25SChristophe Leroy isync 6917312f25SChristophe Leroy#endif 7017312f25SChristophe Leroy /* Get PTE (linux-style) and check access */ 7117312f25SChristophe Leroy lis r0,KERNELBASE@h /* check if kernel address */ 7217312f25SChristophe Leroy cmplw 0,r4,r0 7317312f25SChristophe Leroy ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ 7417312f25SChristophe Leroy mfspr r5, SPRN_SPRG_PGDIR /* phys page-table root */ 75cd08f109SChristophe Leroy#ifdef CONFIG_VMAP_STACK 76cd08f109SChristophe Leroy tovirt(r5, r5) 77cd08f109SChristophe Leroy#endif 7817312f25SChristophe Leroy blt+ 112f /* assume user more likely */ 79cd08f109SChristophe Leroy lis r5, (swapper_pg_dir - ADDR_OFFSET)@ha /* if kernel address, use */ 80cd08f109SChristophe Leroy addi r5 ,r5 ,(swapper_pg_dir - ADDR_OFFSET)@l /* kernel page table */ 8117312f25SChristophe Leroy rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ 8217312f25SChristophe Leroy112: 8317312f25SChristophe Leroy#ifndef CONFIG_PTE_64BIT 8417312f25SChristophe Leroy rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ 8517312f25SChristophe Leroy lwz r8,0(r5) /* get pmd entry */ 8617312f25SChristophe Leroy rlwinm. r8,r8,0,0,19 /* extract address of pte page */ 8717312f25SChristophe Leroy#else 8817312f25SChristophe Leroy rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */ 8917312f25SChristophe Leroy lwzx r8,r8,r5 /* Get L1 entry */ 9017312f25SChristophe Leroy rlwinm. r8,r8,0,0,20 /* extract pt base address */ 9117312f25SChristophe Leroy#endif 92cd08f109SChristophe Leroy#ifdef CONFIG_VMAP_STACK 93cd08f109SChristophe Leroy tovirt(r8, r8) 94cd08f109SChristophe Leroy#endif 9517312f25SChristophe Leroy#ifdef CONFIG_SMP 9617312f25SChristophe Leroy beq- hash_page_out /* return if no mapping */ 9717312f25SChristophe Leroy#else 9817312f25SChristophe Leroy /* XXX it seems like the 601 will give a machine fault on the 9917312f25SChristophe Leroy rfi if its alignment is wrong (bottom 4 bits of address are 10017312f25SChristophe Leroy 8 or 0xc) and we have had a not-taken conditional branch 10117312f25SChristophe Leroy to the address following the rfi. */ 10217312f25SChristophe Leroy beqlr- 10317312f25SChristophe Leroy#endif 10417312f25SChristophe Leroy#ifndef CONFIG_PTE_64BIT 10517312f25SChristophe Leroy rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ 10617312f25SChristophe Leroy#else 10717312f25SChristophe Leroy rlwimi r8,r4,23,20,28 /* compute pte address */ 10817312f25SChristophe Leroy#endif 10917312f25SChristophe Leroy rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 11017312f25SChristophe Leroy ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE 11117312f25SChristophe Leroy 11217312f25SChristophe Leroy /* 11317312f25SChristophe Leroy * Update the linux PTE atomically. We do the lwarx up-front 11417312f25SChristophe Leroy * because almost always, there won't be a permission violation 11517312f25SChristophe Leroy * and there won't already be an HPTE, and thus we will have 11617312f25SChristophe Leroy * to update the PTE to set _PAGE_HASHPTE. -- paulus. 11717312f25SChristophe Leroy * 11817312f25SChristophe Leroy * If PTE_64BIT is set, the low word is the flags word; use that 11917312f25SChristophe Leroy * word for locking since it contains all the interesting bits. 12017312f25SChristophe Leroy */ 12117312f25SChristophe Leroy#if (PTE_FLAGS_OFFSET != 0) 12217312f25SChristophe Leroy addi r8,r8,PTE_FLAGS_OFFSET 12317312f25SChristophe Leroy#endif 12417312f25SChristophe Leroyretry: 12517312f25SChristophe Leroy lwarx r6,0,r8 /* get linux-style pte, flag word */ 12617312f25SChristophe Leroy andc. r5,r3,r6 /* check access & ~permission */ 12717312f25SChristophe Leroy#ifdef CONFIG_SMP 12817312f25SChristophe Leroy bne- hash_page_out /* return if access not permitted */ 12917312f25SChristophe Leroy#else 13017312f25SChristophe Leroy bnelr- 13117312f25SChristophe Leroy#endif 13217312f25SChristophe Leroy or r5,r0,r6 /* set accessed/dirty bits */ 13317312f25SChristophe Leroy#ifdef CONFIG_PTE_64BIT 13417312f25SChristophe Leroy#ifdef CONFIG_SMP 13517312f25SChristophe Leroy subf r10,r6,r8 /* create false data dependency */ 13617312f25SChristophe Leroy subi r10,r10,PTE_FLAGS_OFFSET 13717312f25SChristophe Leroy lwzx r10,r6,r10 /* Get upper PTE word */ 13817312f25SChristophe Leroy#else 13917312f25SChristophe Leroy lwz r10,-PTE_FLAGS_OFFSET(r8) 14017312f25SChristophe Leroy#endif /* CONFIG_SMP */ 14117312f25SChristophe Leroy#endif /* CONFIG_PTE_64BIT */ 14217312f25SChristophe Leroy stwcx. r5,0,r8 /* attempt to update PTE */ 14317312f25SChristophe Leroy bne- retry /* retry if someone got there first */ 14417312f25SChristophe Leroy 14517312f25SChristophe Leroy mfsrin r3,r4 /* get segment reg for segment */ 14617312f25SChristophe Leroy mfctr r0 14717312f25SChristophe Leroy stw r0,_CTR(r11) 14817312f25SChristophe Leroy bl create_hpte /* add the hash table entry */ 14917312f25SChristophe Leroy 15017312f25SChristophe Leroy#ifdef CONFIG_SMP 15117312f25SChristophe Leroy eieio 152cd08f109SChristophe Leroy lis r8, (mmu_hash_lock - ADDR_OFFSET)@ha 15317312f25SChristophe Leroy li r0,0 154cd08f109SChristophe Leroy stw r0, (mmu_hash_lock - ADDR_OFFSET)@l(r8) 15517312f25SChristophe Leroy#endif 15617312f25SChristophe Leroy 15717312f25SChristophe Leroy /* Return from the exception */ 15817312f25SChristophe Leroy lwz r5,_CTR(r11) 15917312f25SChristophe Leroy mtctr r5 16017312f25SChristophe Leroy lwz r0,GPR0(r11) 16117312f25SChristophe Leroy lwz r8,GPR8(r11) 16217312f25SChristophe Leroy b fast_exception_return 16317312f25SChristophe Leroy 16417312f25SChristophe Leroy#ifdef CONFIG_SMP 16517312f25SChristophe Leroyhash_page_out: 16617312f25SChristophe Leroy eieio 167cd08f109SChristophe Leroy lis r8, (mmu_hash_lock - ADDR_OFFSET)@ha 16817312f25SChristophe Leroy li r0,0 169cd08f109SChristophe Leroy stw r0, (mmu_hash_lock - ADDR_OFFSET)@l(r8) 17017312f25SChristophe Leroy blr 17117312f25SChristophe Leroy#endif /* CONFIG_SMP */ 17217312f25SChristophe Leroy 17317312f25SChristophe Leroy/* 17417312f25SChristophe Leroy * Add an entry for a particular page to the hash table. 17517312f25SChristophe Leroy * 17617312f25SChristophe Leroy * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) 17717312f25SChristophe Leroy * 17817312f25SChristophe Leroy * We assume any necessary modifications to the pte (e.g. setting 17917312f25SChristophe Leroy * the accessed bit) have already been done and that there is actually 18017312f25SChristophe Leroy * a hash table in use (i.e. we're not on a 603). 18117312f25SChristophe Leroy */ 18217312f25SChristophe Leroy_GLOBAL(add_hash_page) 18317312f25SChristophe Leroy mflr r0 18417312f25SChristophe Leroy stw r0,4(r1) 18517312f25SChristophe Leroy 18617312f25SChristophe Leroy /* Convert context and va to VSID */ 18717312f25SChristophe Leroy mulli r3,r3,897*16 /* multiply context by context skew */ 18817312f25SChristophe Leroy rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 18917312f25SChristophe Leroy mulli r0,r0,0x111 /* multiply by ESID skew */ 19017312f25SChristophe Leroy add r3,r3,r0 /* note create_hpte trims to 24 bits */ 19117312f25SChristophe Leroy 19217312f25SChristophe Leroy#ifdef CONFIG_SMP 19317312f25SChristophe Leroy lwz r8,TASK_CPU(r2) /* to go in mmu_hash_lock */ 19417312f25SChristophe Leroy oris r8,r8,12 19517312f25SChristophe Leroy#endif /* CONFIG_SMP */ 19617312f25SChristophe Leroy 19717312f25SChristophe Leroy /* 19817312f25SChristophe Leroy * We disable interrupts here, even on UP, because we don't 19917312f25SChristophe Leroy * want to race with hash_page, and because we want the 20017312f25SChristophe Leroy * _PAGE_HASHPTE bit to be a reliable indication of whether 20117312f25SChristophe Leroy * the HPTE exists (or at least whether one did once). 20217312f25SChristophe Leroy * We also turn off the MMU for data accesses so that we 20317312f25SChristophe Leroy * we can't take a hash table miss (assuming the code is 20417312f25SChristophe Leroy * covered by a BAT). -- paulus 20517312f25SChristophe Leroy */ 20617312f25SChristophe Leroy mfmsr r9 20717312f25SChristophe Leroy SYNC 20817312f25SChristophe Leroy rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */ 20917312f25SChristophe Leroy rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 21017312f25SChristophe Leroy mtmsr r0 21117312f25SChristophe Leroy SYNC_601 21217312f25SChristophe Leroy isync 21317312f25SChristophe Leroy 21417312f25SChristophe Leroy#ifdef CONFIG_SMP 21517312f25SChristophe Leroy lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha 21617312f25SChristophe Leroy addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l 21717312f25SChristophe Leroy10: lwarx r0,0,r6 /* take the mmu_hash_lock */ 21817312f25SChristophe Leroy cmpi 0,r0,0 21917312f25SChristophe Leroy bne- 11f 22017312f25SChristophe Leroy stwcx. r8,0,r6 22117312f25SChristophe Leroy beq+ 12f 22217312f25SChristophe Leroy11: lwz r0,0(r6) 22317312f25SChristophe Leroy cmpi 0,r0,0 22417312f25SChristophe Leroy beq 10b 22517312f25SChristophe Leroy b 11b 22617312f25SChristophe Leroy12: isync 22717312f25SChristophe Leroy#endif 22817312f25SChristophe Leroy 22917312f25SChristophe Leroy /* 23017312f25SChristophe Leroy * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. 23117312f25SChristophe Leroy * If _PAGE_HASHPTE was already set, we don't replace the existing 23217312f25SChristophe Leroy * HPTE, so we just unlock and return. 23317312f25SChristophe Leroy */ 23417312f25SChristophe Leroy mr r8,r5 23517312f25SChristophe Leroy#ifndef CONFIG_PTE_64BIT 23617312f25SChristophe Leroy rlwimi r8,r4,22,20,29 23717312f25SChristophe Leroy#else 23817312f25SChristophe Leroy rlwimi r8,r4,23,20,28 23917312f25SChristophe Leroy addi r8,r8,PTE_FLAGS_OFFSET 24017312f25SChristophe Leroy#endif 24117312f25SChristophe Leroy1: lwarx r6,0,r8 24217312f25SChristophe Leroy andi. r0,r6,_PAGE_HASHPTE 24317312f25SChristophe Leroy bne 9f /* if HASHPTE already set, done */ 24417312f25SChristophe Leroy#ifdef CONFIG_PTE_64BIT 24517312f25SChristophe Leroy#ifdef CONFIG_SMP 24617312f25SChristophe Leroy subf r10,r6,r8 /* create false data dependency */ 24717312f25SChristophe Leroy subi r10,r10,PTE_FLAGS_OFFSET 24817312f25SChristophe Leroy lwzx r10,r6,r10 /* Get upper PTE word */ 24917312f25SChristophe Leroy#else 25017312f25SChristophe Leroy lwz r10,-PTE_FLAGS_OFFSET(r8) 25117312f25SChristophe Leroy#endif /* CONFIG_SMP */ 25217312f25SChristophe Leroy#endif /* CONFIG_PTE_64BIT */ 25317312f25SChristophe Leroy ori r5,r6,_PAGE_HASHPTE 25417312f25SChristophe Leroy stwcx. r5,0,r8 25517312f25SChristophe Leroy bne- 1b 25617312f25SChristophe Leroy 25717312f25SChristophe Leroy bl create_hpte 25817312f25SChristophe Leroy 25917312f25SChristophe Leroy9: 26017312f25SChristophe Leroy#ifdef CONFIG_SMP 26117312f25SChristophe Leroy lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha 26217312f25SChristophe Leroy addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l 26317312f25SChristophe Leroy eieio 26417312f25SChristophe Leroy li r0,0 26517312f25SChristophe Leroy stw r0,0(r6) /* clear mmu_hash_lock */ 26617312f25SChristophe Leroy#endif 26717312f25SChristophe Leroy 26817312f25SChristophe Leroy /* reenable interrupts and DR */ 26917312f25SChristophe Leroy mtmsr r9 27017312f25SChristophe Leroy SYNC_601 27117312f25SChristophe Leroy isync 27217312f25SChristophe Leroy 27317312f25SChristophe Leroy lwz r0,4(r1) 27417312f25SChristophe Leroy mtlr r0 27517312f25SChristophe Leroy blr 27617312f25SChristophe Leroy 27717312f25SChristophe Leroy/* 27817312f25SChristophe Leroy * This routine adds a hardware PTE to the hash table. 27917312f25SChristophe Leroy * It is designed to be called with the MMU either on or off. 28017312f25SChristophe Leroy * r3 contains the VSID, r4 contains the virtual address, 28117312f25SChristophe Leroy * r5 contains the linux PTE, r6 contains the old value of the 28217312f25SChristophe Leroy * linux PTE (before setting _PAGE_HASHPTE). r10 contains the 28317312f25SChristophe Leroy * upper half of the PTE if CONFIG_PTE_64BIT. 28417312f25SChristophe Leroy * On SMP, the caller should have the mmu_hash_lock held. 28517312f25SChristophe Leroy * We assume that the caller has (or will) set the _PAGE_HASHPTE 28617312f25SChristophe Leroy * bit in the linux PTE in memory. The value passed in r6 should 28717312f25SChristophe Leroy * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set 28817312f25SChristophe Leroy * this routine will skip the search for an existing HPTE. 28917312f25SChristophe Leroy * This procedure modifies r0, r3 - r6, r8, cr0. 29017312f25SChristophe Leroy * -- paulus. 29117312f25SChristophe Leroy * 29217312f25SChristophe Leroy * For speed, 4 of the instructions get patched once the size and 29317312f25SChristophe Leroy * physical address of the hash table are known. These definitions 29417312f25SChristophe Leroy * of Hash_base and Hash_bits below are just an example. 29517312f25SChristophe Leroy */ 29617312f25SChristophe LeroyHash_base = 0xc0180000 29717312f25SChristophe LeroyHash_bits = 12 /* e.g. 256kB hash table */ 29817312f25SChristophe LeroyHash_msk = (((1 << Hash_bits) - 1) * 64) 29917312f25SChristophe Leroy 30017312f25SChristophe Leroy/* defines for the PTE format for 32-bit PPCs */ 30117312f25SChristophe Leroy#define HPTE_SIZE 8 30217312f25SChristophe Leroy#define PTEG_SIZE 64 30317312f25SChristophe Leroy#define LG_PTEG_SIZE 6 30417312f25SChristophe Leroy#define LDPTEu lwzu 30517312f25SChristophe Leroy#define LDPTE lwz 30617312f25SChristophe Leroy#define STPTE stw 30717312f25SChristophe Leroy#define CMPPTE cmpw 30817312f25SChristophe Leroy#define PTE_H 0x40 30917312f25SChristophe Leroy#define PTE_V 0x80000000 31017312f25SChristophe Leroy#define TST_V(r) rlwinm. r,r,0,0,0 31117312f25SChristophe Leroy#define SET_V(r) oris r,r,PTE_V@h 31217312f25SChristophe Leroy#define CLR_V(r,t) rlwinm r,r,0,1,31 31317312f25SChristophe Leroy 31417312f25SChristophe Leroy#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) 31517312f25SChristophe Leroy#define HASH_RIGHT 31-LG_PTEG_SIZE 31617312f25SChristophe Leroy 31717312f25SChristophe Leroy_GLOBAL(create_hpte) 31817312f25SChristophe Leroy /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ 31917312f25SChristophe Leroy rlwinm r8,r5,32-9,30,30 /* _PAGE_RW -> PP msb */ 32017312f25SChristophe Leroy rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */ 32117312f25SChristophe Leroy and r8,r8,r0 /* writable if _RW & _DIRTY */ 32217312f25SChristophe Leroy rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 32317312f25SChristophe Leroy rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 32417312f25SChristophe Leroy ori r8,r8,0xe04 /* clear out reserved bits */ 32517312f25SChristophe Leroy andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */ 32617312f25SChristophe LeroyBEGIN_FTR_SECTION 32717312f25SChristophe Leroy rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 32817312f25SChristophe LeroyEND_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 32917312f25SChristophe Leroy#ifdef CONFIG_PTE_64BIT 33017312f25SChristophe Leroy /* Put the XPN bits into the PTE */ 33117312f25SChristophe Leroy rlwimi r8,r10,8,20,22 33217312f25SChristophe Leroy rlwimi r8,r10,2,29,29 33317312f25SChristophe Leroy#endif 33417312f25SChristophe Leroy 33517312f25SChristophe Leroy /* Construct the high word of the PPC-style PTE (r5) */ 33617312f25SChristophe Leroy rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 33717312f25SChristophe Leroy rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ 33817312f25SChristophe Leroy SET_V(r5) /* set V (valid) bit */ 33917312f25SChristophe Leroy 34017312f25SChristophe Leroy patch_site 0f, patch__hash_page_A0 34117312f25SChristophe Leroy patch_site 1f, patch__hash_page_A1 34217312f25SChristophe Leroy patch_site 2f, patch__hash_page_A2 34317312f25SChristophe Leroy /* Get the address of the primary PTE group in the hash table (r3) */ 344cd08f109SChristophe Leroy0: lis r0, (Hash_base - ADDR_OFFSET)@h /* base address of hash table */ 34517312f25SChristophe Leroy1: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 34617312f25SChristophe Leroy2: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 34717312f25SChristophe Leroy xor r3,r3,r0 /* make primary hash */ 34817312f25SChristophe Leroy li r0,8 /* PTEs/group */ 34917312f25SChristophe Leroy 35017312f25SChristophe Leroy /* 35117312f25SChristophe Leroy * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search 35217312f25SChristophe Leroy * if it is clear, meaning that the HPTE isn't there already... 35317312f25SChristophe Leroy */ 35417312f25SChristophe Leroy andi. r6,r6,_PAGE_HASHPTE 35517312f25SChristophe Leroy beq+ 10f /* no PTE: go look for an empty slot */ 35617312f25SChristophe Leroy tlbie r4 35717312f25SChristophe Leroy 358cd08f109SChristophe Leroy lis r4, (htab_hash_searches - ADDR_OFFSET)@ha 359cd08f109SChristophe Leroy lwz r6, (htab_hash_searches - ADDR_OFFSET)@l(r4) 36017312f25SChristophe Leroy addi r6,r6,1 /* count how many searches we do */ 361cd08f109SChristophe Leroy stw r6, (htab_hash_searches - ADDR_OFFSET)@l(r4) 36217312f25SChristophe Leroy 36317312f25SChristophe Leroy /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 36417312f25SChristophe Leroy mtctr r0 36517312f25SChristophe Leroy addi r4,r3,-HPTE_SIZE 36617312f25SChristophe Leroy1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 36717312f25SChristophe Leroy CMPPTE 0,r6,r5 36817312f25SChristophe Leroy bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 36917312f25SChristophe Leroy beq+ found_slot 37017312f25SChristophe Leroy 37117312f25SChristophe Leroy patch_site 0f, patch__hash_page_B 37217312f25SChristophe Leroy /* Search the secondary PTEG for a matching PTE */ 37317312f25SChristophe Leroy ori r5,r5,PTE_H /* set H (secondary hash) bit */ 37417312f25SChristophe Leroy0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 37517312f25SChristophe Leroy xori r4,r4,(-PTEG_SIZE & 0xffff) 37617312f25SChristophe Leroy addi r4,r4,-HPTE_SIZE 37717312f25SChristophe Leroy mtctr r0 37817312f25SChristophe Leroy2: LDPTEu r6,HPTE_SIZE(r4) 37917312f25SChristophe Leroy CMPPTE 0,r6,r5 38017312f25SChristophe Leroy bdnzf 2,2b 38117312f25SChristophe Leroy beq+ found_slot 38217312f25SChristophe Leroy xori r5,r5,PTE_H /* clear H bit again */ 38317312f25SChristophe Leroy 38417312f25SChristophe Leroy /* Search the primary PTEG for an empty slot */ 38517312f25SChristophe Leroy10: mtctr r0 38617312f25SChristophe Leroy addi r4,r3,-HPTE_SIZE /* search primary PTEG */ 38717312f25SChristophe Leroy1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 38817312f25SChristophe Leroy TST_V(r6) /* test valid bit */ 38917312f25SChristophe Leroy bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 39017312f25SChristophe Leroy beq+ found_empty 39117312f25SChristophe Leroy 39217312f25SChristophe Leroy /* update counter of times that the primary PTEG is full */ 393cd08f109SChristophe Leroy lis r4, (primary_pteg_full - ADDR_OFFSET)@ha 394cd08f109SChristophe Leroy lwz r6, (primary_pteg_full - ADDR_OFFSET)@l(r4) 39517312f25SChristophe Leroy addi r6,r6,1 396cd08f109SChristophe Leroy stw r6, (primary_pteg_full - ADDR_OFFSET)@l(r4) 39717312f25SChristophe Leroy 39817312f25SChristophe Leroy patch_site 0f, patch__hash_page_C 39917312f25SChristophe Leroy /* Search the secondary PTEG for an empty slot */ 40017312f25SChristophe Leroy ori r5,r5,PTE_H /* set H (secondary hash) bit */ 40117312f25SChristophe Leroy0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 40217312f25SChristophe Leroy xori r4,r4,(-PTEG_SIZE & 0xffff) 40317312f25SChristophe Leroy addi r4,r4,-HPTE_SIZE 40417312f25SChristophe Leroy mtctr r0 40517312f25SChristophe Leroy2: LDPTEu r6,HPTE_SIZE(r4) 40617312f25SChristophe Leroy TST_V(r6) 40717312f25SChristophe Leroy bdnzf 2,2b 40817312f25SChristophe Leroy beq+ found_empty 40917312f25SChristophe Leroy xori r5,r5,PTE_H /* clear H bit again */ 41017312f25SChristophe Leroy 41117312f25SChristophe Leroy /* 41217312f25SChristophe Leroy * Choose an arbitrary slot in the primary PTEG to overwrite. 41317312f25SChristophe Leroy * Since both the primary and secondary PTEGs are full, and we 41417312f25SChristophe Leroy * have no information that the PTEs in the primary PTEG are 41517312f25SChristophe Leroy * more important or useful than those in the secondary PTEG, 41617312f25SChristophe Leroy * and we know there is a definite (although small) speed 41717312f25SChristophe Leroy * advantage to putting the PTE in the primary PTEG, we always 41817312f25SChristophe Leroy * put the PTE in the primary PTEG. 41917312f25SChristophe Leroy * 42017312f25SChristophe Leroy * In addition, we skip any slot that is mapping kernel text in 42117312f25SChristophe Leroy * order to avoid a deadlock when not using BAT mappings if 42217312f25SChristophe Leroy * trying to hash in the kernel hash code itself after it has 42317312f25SChristophe Leroy * already taken the hash table lock. This works in conjunction 42417312f25SChristophe Leroy * with pre-faulting of the kernel text. 42517312f25SChristophe Leroy * 42617312f25SChristophe Leroy * If the hash table bucket is full of kernel text entries, we'll 42717312f25SChristophe Leroy * lockup here but that shouldn't happen 42817312f25SChristophe Leroy */ 42917312f25SChristophe Leroy 430cd08f109SChristophe Leroy1: lis r4, (next_slot - ADDR_OFFSET)@ha /* get next evict slot */ 431cd08f109SChristophe Leroy lwz r6, (next_slot - ADDR_OFFSET)@l(r4) 43217312f25SChristophe Leroy addi r6,r6,HPTE_SIZE /* search for candidate */ 43317312f25SChristophe Leroy andi. r6,r6,7*HPTE_SIZE 43417312f25SChristophe Leroy stw r6,next_slot@l(r4) 43517312f25SChristophe Leroy add r4,r3,r6 43617312f25SChristophe Leroy LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */ 43717312f25SChristophe Leroy clrrwi r0,r0,12 43817312f25SChristophe Leroy lis r6,etext@h 43917312f25SChristophe Leroy ori r6,r6,etext@l /* get etext */ 44017312f25SChristophe Leroy tophys(r6,r6) 44117312f25SChristophe Leroy cmpl cr0,r0,r6 /* compare and try again */ 44217312f25SChristophe Leroy blt 1b 44317312f25SChristophe Leroy 44417312f25SChristophe Leroy#ifndef CONFIG_SMP 44517312f25SChristophe Leroy /* Store PTE in PTEG */ 44617312f25SChristophe Leroyfound_empty: 44717312f25SChristophe Leroy STPTE r5,0(r4) 44817312f25SChristophe Leroyfound_slot: 44917312f25SChristophe Leroy STPTE r8,HPTE_SIZE/2(r4) 45017312f25SChristophe Leroy 45117312f25SChristophe Leroy#else /* CONFIG_SMP */ 45217312f25SChristophe Leroy/* 45317312f25SChristophe Leroy * Between the tlbie above and updating the hash table entry below, 45417312f25SChristophe Leroy * another CPU could read the hash table entry and put it in its TLB. 45517312f25SChristophe Leroy * There are 3 cases: 45617312f25SChristophe Leroy * 1. using an empty slot 45717312f25SChristophe Leroy * 2. updating an earlier entry to change permissions (i.e. enable write) 45817312f25SChristophe Leroy * 3. taking over the PTE for an unrelated address 45917312f25SChristophe Leroy * 46017312f25SChristophe Leroy * In each case it doesn't really matter if the other CPUs have the old 46117312f25SChristophe Leroy * PTE in their TLB. So we don't need to bother with another tlbie here, 46217312f25SChristophe Leroy * which is convenient as we've overwritten the register that had the 46317312f25SChristophe Leroy * address. :-) The tlbie above is mainly to make sure that this CPU comes 46417312f25SChristophe Leroy * and gets the new PTE from the hash table. 46517312f25SChristophe Leroy * 46617312f25SChristophe Leroy * We do however have to make sure that the PTE is never in an invalid 46717312f25SChristophe Leroy * state with the V bit set. 46817312f25SChristophe Leroy */ 46917312f25SChristophe Leroyfound_empty: 47017312f25SChristophe Leroyfound_slot: 47117312f25SChristophe Leroy CLR_V(r5,r0) /* clear V (valid) bit in PTE */ 47217312f25SChristophe Leroy STPTE r5,0(r4) 47317312f25SChristophe Leroy sync 47417312f25SChristophe Leroy TLBSYNC 47517312f25SChristophe Leroy STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ 47617312f25SChristophe Leroy sync 47717312f25SChristophe Leroy SET_V(r5) 47817312f25SChristophe Leroy STPTE r5,0(r4) /* finally set V bit in PTE */ 47917312f25SChristophe Leroy#endif /* CONFIG_SMP */ 48017312f25SChristophe Leroy 48117312f25SChristophe Leroy sync /* make sure pte updates get to memory */ 48217312f25SChristophe Leroy blr 48317312f25SChristophe Leroy 48417312f25SChristophe Leroy .section .bss 48517312f25SChristophe Leroy .align 2 48617312f25SChristophe Leroynext_slot: 48717312f25SChristophe Leroy .space 4 48817312f25SChristophe Leroyprimary_pteg_full: 48917312f25SChristophe Leroy .space 4 49017312f25SChristophe Leroyhtab_hash_searches: 49117312f25SChristophe Leroy .space 4 49217312f25SChristophe Leroy .previous 49317312f25SChristophe Leroy 49417312f25SChristophe Leroy/* 49517312f25SChristophe Leroy * Flush the entry for a particular page from the hash table. 49617312f25SChristophe Leroy * 49717312f25SChristophe Leroy * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, 49817312f25SChristophe Leroy * int count) 49917312f25SChristophe Leroy * 50017312f25SChristophe Leroy * We assume that there is a hash table in use (Hash != 0). 50117312f25SChristophe Leroy */ 50217312f25SChristophe Leroy_GLOBAL(flush_hash_pages) 50317312f25SChristophe Leroy /* 50417312f25SChristophe Leroy * We disable interrupts here, even on UP, because we want 50517312f25SChristophe Leroy * the _PAGE_HASHPTE bit to be a reliable indication of 50617312f25SChristophe Leroy * whether the HPTE exists (or at least whether one did once). 50717312f25SChristophe Leroy * We also turn off the MMU for data accesses so that we 50817312f25SChristophe Leroy * we can't take a hash table miss (assuming the code is 50917312f25SChristophe Leroy * covered by a BAT). -- paulus 51017312f25SChristophe Leroy */ 51117312f25SChristophe Leroy mfmsr r10 51217312f25SChristophe Leroy SYNC 51317312f25SChristophe Leroy rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 51417312f25SChristophe Leroy rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 51517312f25SChristophe Leroy mtmsr r0 51617312f25SChristophe Leroy SYNC_601 51717312f25SChristophe Leroy isync 51817312f25SChristophe Leroy 51917312f25SChristophe Leroy /* First find a PTE in the range that has _PAGE_HASHPTE set */ 52017312f25SChristophe Leroy#ifndef CONFIG_PTE_64BIT 52117312f25SChristophe Leroy rlwimi r5,r4,22,20,29 52217312f25SChristophe Leroy#else 52317312f25SChristophe Leroy rlwimi r5,r4,23,20,28 52417312f25SChristophe Leroy#endif 52517312f25SChristophe Leroy1: lwz r0,PTE_FLAGS_OFFSET(r5) 52617312f25SChristophe Leroy cmpwi cr1,r6,1 52717312f25SChristophe Leroy andi. r0,r0,_PAGE_HASHPTE 52817312f25SChristophe Leroy bne 2f 52917312f25SChristophe Leroy ble cr1,19f 53017312f25SChristophe Leroy addi r4,r4,0x1000 53117312f25SChristophe Leroy addi r5,r5,PTE_SIZE 53217312f25SChristophe Leroy addi r6,r6,-1 53317312f25SChristophe Leroy b 1b 53417312f25SChristophe Leroy 53517312f25SChristophe Leroy /* Convert context and va to VSID */ 53617312f25SChristophe Leroy2: mulli r3,r3,897*16 /* multiply context by context skew */ 53717312f25SChristophe Leroy rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 53817312f25SChristophe Leroy mulli r0,r0,0x111 /* multiply by ESID skew */ 53917312f25SChristophe Leroy add r3,r3,r0 /* note code below trims to 24 bits */ 54017312f25SChristophe Leroy 54117312f25SChristophe Leroy /* Construct the high word of the PPC-style PTE (r11) */ 54217312f25SChristophe Leroy rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 54317312f25SChristophe Leroy rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ 54417312f25SChristophe Leroy SET_V(r11) /* set V (valid) bit */ 54517312f25SChristophe Leroy 54617312f25SChristophe Leroy#ifdef CONFIG_SMP 54717312f25SChristophe Leroy lis r9, (mmu_hash_lock - PAGE_OFFSET)@ha 54817312f25SChristophe Leroy addi r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l 549397d2300SChristophe Leroy tophys (r8, r2) 550397d2300SChristophe Leroy lwz r8, TASK_CPU(r8) 55117312f25SChristophe Leroy oris r8,r8,9 55217312f25SChristophe Leroy10: lwarx r0,0,r9 55317312f25SChristophe Leroy cmpi 0,r0,0 55417312f25SChristophe Leroy bne- 11f 55517312f25SChristophe Leroy stwcx. r8,0,r9 55617312f25SChristophe Leroy beq+ 12f 55717312f25SChristophe Leroy11: lwz r0,0(r9) 55817312f25SChristophe Leroy cmpi 0,r0,0 55917312f25SChristophe Leroy beq 10b 56017312f25SChristophe Leroy b 11b 56117312f25SChristophe Leroy12: isync 56217312f25SChristophe Leroy#endif 56317312f25SChristophe Leroy 56417312f25SChristophe Leroy /* 56517312f25SChristophe Leroy * Check the _PAGE_HASHPTE bit in the linux PTE. If it is 56617312f25SChristophe Leroy * already clear, we're done (for this pte). If not, 56717312f25SChristophe Leroy * clear it (atomically) and proceed. -- paulus. 56817312f25SChristophe Leroy */ 56917312f25SChristophe Leroy#if (PTE_FLAGS_OFFSET != 0) 57017312f25SChristophe Leroy addi r5,r5,PTE_FLAGS_OFFSET 57117312f25SChristophe Leroy#endif 57217312f25SChristophe Leroy33: lwarx r8,0,r5 /* fetch the pte flags word */ 57317312f25SChristophe Leroy andi. r0,r8,_PAGE_HASHPTE 57417312f25SChristophe Leroy beq 8f /* done if HASHPTE is already clear */ 57517312f25SChristophe Leroy rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ 57617312f25SChristophe Leroy stwcx. r8,0,r5 /* update the pte */ 57717312f25SChristophe Leroy bne- 33b 57817312f25SChristophe Leroy 57917312f25SChristophe Leroy patch_site 0f, patch__flush_hash_A0 58017312f25SChristophe Leroy patch_site 1f, patch__flush_hash_A1 58117312f25SChristophe Leroy patch_site 2f, patch__flush_hash_A2 58217312f25SChristophe Leroy /* Get the address of the primary PTE group in the hash table (r3) */ 58317312f25SChristophe Leroy0: lis r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */ 58417312f25SChristophe Leroy1: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 58517312f25SChristophe Leroy2: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 58617312f25SChristophe Leroy xor r8,r0,r8 /* make primary hash */ 58717312f25SChristophe Leroy 58817312f25SChristophe Leroy /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 58917312f25SChristophe Leroy li r0,8 /* PTEs/group */ 59017312f25SChristophe Leroy mtctr r0 59117312f25SChristophe Leroy addi r12,r8,-HPTE_SIZE 59217312f25SChristophe Leroy1: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */ 59317312f25SChristophe Leroy CMPPTE 0,r0,r11 59417312f25SChristophe Leroy bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 59517312f25SChristophe Leroy beq+ 3f 59617312f25SChristophe Leroy 59717312f25SChristophe Leroy patch_site 0f, patch__flush_hash_B 59817312f25SChristophe Leroy /* Search the secondary PTEG for a matching PTE */ 59917312f25SChristophe Leroy ori r11,r11,PTE_H /* set H (secondary hash) bit */ 60017312f25SChristophe Leroy li r0,8 /* PTEs/group */ 60117312f25SChristophe Leroy0: xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ 60217312f25SChristophe Leroy xori r12,r12,(-PTEG_SIZE & 0xffff) 60317312f25SChristophe Leroy addi r12,r12,-HPTE_SIZE 60417312f25SChristophe Leroy mtctr r0 60517312f25SChristophe Leroy2: LDPTEu r0,HPTE_SIZE(r12) 60617312f25SChristophe Leroy CMPPTE 0,r0,r11 60717312f25SChristophe Leroy bdnzf 2,2b 60817312f25SChristophe Leroy xori r11,r11,PTE_H /* clear H again */ 60917312f25SChristophe Leroy bne- 4f /* should rarely fail to find it */ 61017312f25SChristophe Leroy 61117312f25SChristophe Leroy3: li r0,0 61217312f25SChristophe Leroy STPTE r0,0(r12) /* invalidate entry */ 61317312f25SChristophe Leroy4: sync 61417312f25SChristophe Leroy tlbie r4 /* in hw tlb too */ 61517312f25SChristophe Leroy sync 61617312f25SChristophe Leroy 61717312f25SChristophe Leroy8: ble cr1,9f /* if all ptes checked */ 61817312f25SChristophe Leroy81: addi r6,r6,-1 61917312f25SChristophe Leroy addi r5,r5,PTE_SIZE 62017312f25SChristophe Leroy addi r4,r4,0x1000 62117312f25SChristophe Leroy lwz r0,0(r5) /* check next pte */ 62217312f25SChristophe Leroy cmpwi cr1,r6,1 62317312f25SChristophe Leroy andi. r0,r0,_PAGE_HASHPTE 62417312f25SChristophe Leroy bne 33b 62517312f25SChristophe Leroy bgt cr1,81b 62617312f25SChristophe Leroy 62717312f25SChristophe Leroy9: 62817312f25SChristophe Leroy#ifdef CONFIG_SMP 62917312f25SChristophe Leroy TLBSYNC 63017312f25SChristophe Leroy li r0,0 63117312f25SChristophe Leroy stw r0,0(r9) /* clear mmu_hash_lock */ 63217312f25SChristophe Leroy#endif 63317312f25SChristophe Leroy 63417312f25SChristophe Leroy19: mtmsr r10 63517312f25SChristophe Leroy SYNC_601 63617312f25SChristophe Leroy isync 63717312f25SChristophe Leroy blr 63817312f25SChristophe LeroyEXPORT_SYMBOL(flush_hash_pages) 63917312f25SChristophe Leroy 64017312f25SChristophe Leroy/* 64117312f25SChristophe Leroy * Flush an entry from the TLB 64217312f25SChristophe Leroy */ 64317312f25SChristophe Leroy_GLOBAL(_tlbie) 64417312f25SChristophe Leroy#ifdef CONFIG_SMP 64517312f25SChristophe Leroy lwz r8,TASK_CPU(r2) 64617312f25SChristophe Leroy oris r8,r8,11 64717312f25SChristophe Leroy mfmsr r10 64817312f25SChristophe Leroy SYNC 64917312f25SChristophe Leroy rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 65017312f25SChristophe Leroy rlwinm r0,r0,0,28,26 /* clear DR */ 65117312f25SChristophe Leroy mtmsr r0 65217312f25SChristophe Leroy SYNC_601 65317312f25SChristophe Leroy isync 65417312f25SChristophe Leroy lis r9,mmu_hash_lock@h 65517312f25SChristophe Leroy ori r9,r9,mmu_hash_lock@l 65617312f25SChristophe Leroy tophys(r9,r9) 65717312f25SChristophe Leroy10: lwarx r7,0,r9 65817312f25SChristophe Leroy cmpwi 0,r7,0 65917312f25SChristophe Leroy bne- 10b 66017312f25SChristophe Leroy stwcx. r8,0,r9 66117312f25SChristophe Leroy bne- 10b 66217312f25SChristophe Leroy eieio 66317312f25SChristophe Leroy tlbie r3 66417312f25SChristophe Leroy sync 66517312f25SChristophe Leroy TLBSYNC 66617312f25SChristophe Leroy li r0,0 66717312f25SChristophe Leroy stw r0,0(r9) /* clear mmu_hash_lock */ 66817312f25SChristophe Leroy mtmsr r10 66917312f25SChristophe Leroy SYNC_601 67017312f25SChristophe Leroy isync 67117312f25SChristophe Leroy#else /* CONFIG_SMP */ 67217312f25SChristophe Leroy tlbie r3 67317312f25SChristophe Leroy sync 67417312f25SChristophe Leroy#endif /* CONFIG_SMP */ 67517312f25SChristophe Leroy blr 67617312f25SChristophe Leroy 67717312f25SChristophe Leroy/* 67817312f25SChristophe Leroy * Flush the entire TLB. 603/603e only 67917312f25SChristophe Leroy */ 68017312f25SChristophe Leroy_GLOBAL(_tlbia) 68117312f25SChristophe Leroy#if defined(CONFIG_SMP) 68217312f25SChristophe Leroy lwz r8,TASK_CPU(r2) 68317312f25SChristophe Leroy oris r8,r8,10 68417312f25SChristophe Leroy mfmsr r10 68517312f25SChristophe Leroy SYNC 68617312f25SChristophe Leroy rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 68717312f25SChristophe Leroy rlwinm r0,r0,0,28,26 /* clear DR */ 68817312f25SChristophe Leroy mtmsr r0 68917312f25SChristophe Leroy SYNC_601 69017312f25SChristophe Leroy isync 69117312f25SChristophe Leroy lis r9,mmu_hash_lock@h 69217312f25SChristophe Leroy ori r9,r9,mmu_hash_lock@l 69317312f25SChristophe Leroy tophys(r9,r9) 69417312f25SChristophe Leroy10: lwarx r7,0,r9 69517312f25SChristophe Leroy cmpwi 0,r7,0 69617312f25SChristophe Leroy bne- 10b 69717312f25SChristophe Leroy stwcx. r8,0,r9 69817312f25SChristophe Leroy bne- 10b 699*e1347a02SChristophe Leroy#endif /* CONFIG_SMP */ 700*e1347a02SChristophe Leroy li r5, 32 701*e1347a02SChristophe Leroy lis r4, KERNELBASE@h 702*e1347a02SChristophe Leroy mtctr r5 70317312f25SChristophe Leroy sync 704*e1347a02SChristophe Leroy0: tlbie r4 705*e1347a02SChristophe Leroy addi r4, r4, 0x1000 706*e1347a02SChristophe Leroy bdnz 0b 70717312f25SChristophe Leroy sync 708*e1347a02SChristophe Leroy#ifdef CONFIG_SMP 70917312f25SChristophe Leroy TLBSYNC 71017312f25SChristophe Leroy li r0,0 71117312f25SChristophe Leroy stw r0,0(r9) /* clear mmu_hash_lock */ 71217312f25SChristophe Leroy mtmsr r10 71317312f25SChristophe Leroy SYNC_601 71417312f25SChristophe Leroy isync 71517312f25SChristophe Leroy#endif /* CONFIG_SMP */ 71617312f25SChristophe Leroy blr 717