1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/user.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/prctl.h> 30 #include <linux/delay.h> 31 #include <linux/kprobes.h> 32 #include <linux/kexec.h> 33 #include <linux/backlight.h> 34 #include <linux/bug.h> 35 #include <linux/kdebug.h> 36 #include <linux/debugfs.h> 37 38 #include <asm/emulated_ops.h> 39 #include <asm/pgtable.h> 40 #include <asm/uaccess.h> 41 #include <asm/system.h> 42 #include <asm/io.h> 43 #include <asm/machdep.h> 44 #include <asm/rtas.h> 45 #include <asm/pmc.h> 46 #ifdef CONFIG_PPC32 47 #include <asm/reg.h> 48 #endif 49 #ifdef CONFIG_PMAC_BACKLIGHT 50 #include <asm/backlight.h> 51 #endif 52 #ifdef CONFIG_PPC64 53 #include <asm/firmware.h> 54 #include <asm/processor.h> 55 #endif 56 #include <asm/kexec.h> 57 #include <asm/ppc-opcode.h> 58 #include <asm/rio.h> 59 60 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 61 int (*__debugger)(struct pt_regs *regs) __read_mostly; 62 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 63 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 64 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 65 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 66 int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; 67 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 68 69 EXPORT_SYMBOL(__debugger); 70 EXPORT_SYMBOL(__debugger_ipi); 71 EXPORT_SYMBOL(__debugger_bpt); 72 EXPORT_SYMBOL(__debugger_sstep); 73 EXPORT_SYMBOL(__debugger_iabr_match); 74 EXPORT_SYMBOL(__debugger_dabr_match); 75 EXPORT_SYMBOL(__debugger_fault_handler); 76 #endif 77 78 /* 79 * Trap & Exception support 80 */ 81 82 #ifdef CONFIG_PMAC_BACKLIGHT 83 static void pmac_backlight_unblank(void) 84 { 85 mutex_lock(&pmac_backlight_mutex); 86 if (pmac_backlight) { 87 struct backlight_properties *props; 88 89 props = &pmac_backlight->props; 90 props->brightness = props->max_brightness; 91 props->power = FB_BLANK_UNBLANK; 92 backlight_update_status(pmac_backlight); 93 } 94 mutex_unlock(&pmac_backlight_mutex); 95 } 96 #else 97 static inline void pmac_backlight_unblank(void) { } 98 #endif 99 100 int die(const char *str, struct pt_regs *regs, long err) 101 { 102 static struct { 103 raw_spinlock_t lock; 104 u32 lock_owner; 105 int lock_owner_depth; 106 } die = { 107 .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock), 108 .lock_owner = -1, 109 .lock_owner_depth = 0 110 }; 111 static int die_counter; 112 unsigned long flags; 113 114 if (debugger(regs)) 115 return 1; 116 117 oops_enter(); 118 119 if (die.lock_owner != raw_smp_processor_id()) { 120 console_verbose(); 121 raw_spin_lock_irqsave(&die.lock, flags); 122 die.lock_owner = smp_processor_id(); 123 die.lock_owner_depth = 0; 124 bust_spinlocks(1); 125 if (machine_is(powermac)) 126 pmac_backlight_unblank(); 127 } else { 128 local_save_flags(flags); 129 } 130 131 if (++die.lock_owner_depth < 3) { 132 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 133 #ifdef CONFIG_PREEMPT 134 printk("PREEMPT "); 135 #endif 136 #ifdef CONFIG_SMP 137 printk("SMP NR_CPUS=%d ", NR_CPUS); 138 #endif 139 #ifdef CONFIG_DEBUG_PAGEALLOC 140 printk("DEBUG_PAGEALLOC "); 141 #endif 142 #ifdef CONFIG_NUMA 143 printk("NUMA "); 144 #endif 145 printk("%s\n", ppc_md.name ? ppc_md.name : ""); 146 147 if (notify_die(DIE_OOPS, str, regs, err, 255, 148 SIGSEGV) == NOTIFY_STOP) 149 return 1; 150 151 print_modules(); 152 show_regs(regs); 153 } else { 154 printk("Recursive die() failure, output suppressed\n"); 155 } 156 157 bust_spinlocks(0); 158 die.lock_owner = -1; 159 add_taint(TAINT_DIE); 160 raw_spin_unlock_irqrestore(&die.lock, flags); 161 162 if (kexec_should_crash(current) || 163 kexec_sr_activated(smp_processor_id())) 164 crash_kexec(regs); 165 crash_kexec_secondary(regs); 166 167 if (in_interrupt()) 168 panic("Fatal exception in interrupt"); 169 170 if (panic_on_oops) 171 panic("Fatal exception"); 172 173 oops_exit(); 174 do_exit(err); 175 176 return 0; 177 } 178 179 void user_single_step_siginfo(struct task_struct *tsk, 180 struct pt_regs *regs, siginfo_t *info) 181 { 182 memset(info, 0, sizeof(*info)); 183 info->si_signo = SIGTRAP; 184 info->si_code = TRAP_TRACE; 185 info->si_addr = (void __user *)regs->nip; 186 } 187 188 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 189 { 190 siginfo_t info; 191 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 192 "at %08lx nip %08lx lr %08lx code %x\n"; 193 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 194 "at %016lx nip %016lx lr %016lx code %x\n"; 195 196 if (!user_mode(regs)) { 197 if (die("Exception in kernel mode", regs, signr)) 198 return; 199 } else if (show_unhandled_signals && 200 unhandled_signal(current, signr) && 201 printk_ratelimit()) { 202 printk(regs->msr & MSR_64BIT ? fmt64 : fmt32, 203 current->comm, current->pid, signr, 204 addr, regs->nip, regs->link, code); 205 } 206 207 memset(&info, 0, sizeof(info)); 208 info.si_signo = signr; 209 info.si_code = code; 210 info.si_addr = (void __user *) addr; 211 force_sig_info(signr, &info, current); 212 } 213 214 #ifdef CONFIG_PPC64 215 void system_reset_exception(struct pt_regs *regs) 216 { 217 /* See if any machine dependent calls */ 218 if (ppc_md.system_reset_exception) { 219 if (ppc_md.system_reset_exception(regs)) 220 return; 221 } 222 223 #ifdef CONFIG_KEXEC 224 cpumask_set_cpu(smp_processor_id(), &cpus_in_sr); 225 #endif 226 227 die("System Reset", regs, SIGABRT); 228 229 /* 230 * Some CPUs when released from the debugger will execute this path. 231 * These CPUs entered the debugger via a soft-reset. If the CPU was 232 * hung before entering the debugger it will return to the hung 233 * state when exiting this function. This causes a problem in 234 * kdump since the hung CPU(s) will not respond to the IPI sent 235 * from kdump. To prevent the problem we call crash_kexec_secondary() 236 * here. If a kdump had not been initiated or we exit the debugger 237 * with the "exit and recover" command (x) crash_kexec_secondary() 238 * will return after 5ms and the CPU returns to its previous state. 239 */ 240 crash_kexec_secondary(regs); 241 242 /* Must die if the interrupt is not recoverable */ 243 if (!(regs->msr & MSR_RI)) 244 panic("Unrecoverable System Reset"); 245 246 /* What should we do here? We could issue a shutdown or hard reset. */ 247 } 248 #endif 249 250 /* 251 * I/O accesses can cause machine checks on powermacs. 252 * Check if the NIP corresponds to the address of a sync 253 * instruction for which there is an entry in the exception 254 * table. 255 * Note that the 601 only takes a machine check on TEA 256 * (transfer error ack) signal assertion, and does not 257 * set any of the top 16 bits of SRR1. 258 * -- paulus. 259 */ 260 static inline int check_io_access(struct pt_regs *regs) 261 { 262 #ifdef CONFIG_PPC32 263 unsigned long msr = regs->msr; 264 const struct exception_table_entry *entry; 265 unsigned int *nip = (unsigned int *)regs->nip; 266 267 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 268 && (entry = search_exception_tables(regs->nip)) != NULL) { 269 /* 270 * Check that it's a sync instruction, or somewhere 271 * in the twi; isync; nop sequence that inb/inw/inl uses. 272 * As the address is in the exception table 273 * we should be able to read the instr there. 274 * For the debug message, we look at the preceding 275 * load or store. 276 */ 277 if (*nip == 0x60000000) /* nop */ 278 nip -= 2; 279 else if (*nip == 0x4c00012c) /* isync */ 280 --nip; 281 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 282 /* sync or twi */ 283 unsigned int rb; 284 285 --nip; 286 rb = (*nip >> 11) & 0x1f; 287 printk(KERN_DEBUG "%s bad port %lx at %p\n", 288 (*nip & 0x100)? "OUT to": "IN from", 289 regs->gpr[rb] - _IO_BASE, nip); 290 regs->msr |= MSR_RI; 291 regs->nip = entry->fixup; 292 return 1; 293 } 294 } 295 #endif /* CONFIG_PPC32 */ 296 return 0; 297 } 298 299 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 300 /* On 4xx, the reason for the machine check or program exception 301 is in the ESR. */ 302 #define get_reason(regs) ((regs)->dsisr) 303 #ifndef CONFIG_FSL_BOOKE 304 #define get_mc_reason(regs) ((regs)->dsisr) 305 #else 306 #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 307 #endif 308 #define REASON_FP ESR_FP 309 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 310 #define REASON_PRIVILEGED ESR_PPR 311 #define REASON_TRAP ESR_PTR 312 313 /* single-step stuff */ 314 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 315 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 316 317 #else 318 /* On non-4xx, the reason for the machine check or program 319 exception is in the MSR. */ 320 #define get_reason(regs) ((regs)->msr) 321 #define get_mc_reason(regs) ((regs)->msr) 322 #define REASON_FP 0x100000 323 #define REASON_ILLEGAL 0x80000 324 #define REASON_PRIVILEGED 0x40000 325 #define REASON_TRAP 0x20000 326 327 #define single_stepping(regs) ((regs)->msr & MSR_SE) 328 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 329 #endif 330 331 #if defined(CONFIG_4xx) 332 int machine_check_4xx(struct pt_regs *regs) 333 { 334 unsigned long reason = get_mc_reason(regs); 335 336 if (reason & ESR_IMCP) { 337 printk("Instruction"); 338 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 339 } else 340 printk("Data"); 341 printk(" machine check in kernel mode.\n"); 342 343 return 0; 344 } 345 346 int machine_check_440A(struct pt_regs *regs) 347 { 348 unsigned long reason = get_mc_reason(regs); 349 350 printk("Machine check in kernel mode.\n"); 351 if (reason & ESR_IMCP){ 352 printk("Instruction Synchronous Machine Check exception\n"); 353 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 354 } 355 else { 356 u32 mcsr = mfspr(SPRN_MCSR); 357 if (mcsr & MCSR_IB) 358 printk("Instruction Read PLB Error\n"); 359 if (mcsr & MCSR_DRB) 360 printk("Data Read PLB Error\n"); 361 if (mcsr & MCSR_DWB) 362 printk("Data Write PLB Error\n"); 363 if (mcsr & MCSR_TLBP) 364 printk("TLB Parity Error\n"); 365 if (mcsr & MCSR_ICP){ 366 flush_instruction_cache(); 367 printk("I-Cache Parity Error\n"); 368 } 369 if (mcsr & MCSR_DCSP) 370 printk("D-Cache Search Parity Error\n"); 371 if (mcsr & MCSR_DCFP) 372 printk("D-Cache Flush Parity Error\n"); 373 if (mcsr & MCSR_IMPE) 374 printk("Machine Check exception is imprecise\n"); 375 376 /* Clear MCSR */ 377 mtspr(SPRN_MCSR, mcsr); 378 } 379 return 0; 380 } 381 382 int machine_check_47x(struct pt_regs *regs) 383 { 384 unsigned long reason = get_mc_reason(regs); 385 u32 mcsr; 386 387 printk(KERN_ERR "Machine check in kernel mode.\n"); 388 if (reason & ESR_IMCP) { 389 printk(KERN_ERR 390 "Instruction Synchronous Machine Check exception\n"); 391 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 392 return 0; 393 } 394 mcsr = mfspr(SPRN_MCSR); 395 if (mcsr & MCSR_IB) 396 printk(KERN_ERR "Instruction Read PLB Error\n"); 397 if (mcsr & MCSR_DRB) 398 printk(KERN_ERR "Data Read PLB Error\n"); 399 if (mcsr & MCSR_DWB) 400 printk(KERN_ERR "Data Write PLB Error\n"); 401 if (mcsr & MCSR_TLBP) 402 printk(KERN_ERR "TLB Parity Error\n"); 403 if (mcsr & MCSR_ICP) { 404 flush_instruction_cache(); 405 printk(KERN_ERR "I-Cache Parity Error\n"); 406 } 407 if (mcsr & MCSR_DCSP) 408 printk(KERN_ERR "D-Cache Search Parity Error\n"); 409 if (mcsr & PPC47x_MCSR_GPR) 410 printk(KERN_ERR "GPR Parity Error\n"); 411 if (mcsr & PPC47x_MCSR_FPR) 412 printk(KERN_ERR "FPR Parity Error\n"); 413 if (mcsr & PPC47x_MCSR_IPR) 414 printk(KERN_ERR "Machine Check exception is imprecise\n"); 415 416 /* Clear MCSR */ 417 mtspr(SPRN_MCSR, mcsr); 418 419 return 0; 420 } 421 #elif defined(CONFIG_E500) 422 int machine_check_e500mc(struct pt_regs *regs) 423 { 424 unsigned long mcsr = mfspr(SPRN_MCSR); 425 unsigned long reason = mcsr; 426 int recoverable = 1; 427 428 if (reason & MCSR_BUS_RBERR) { 429 recoverable = fsl_rio_mcheck_exception(regs); 430 if (recoverable == 1) 431 goto silent_out; 432 } 433 434 printk("Machine check in kernel mode.\n"); 435 printk("Caused by (from MCSR=%lx): ", reason); 436 437 if (reason & MCSR_MCP) 438 printk("Machine Check Signal\n"); 439 440 if (reason & MCSR_ICPERR) { 441 printk("Instruction Cache Parity Error\n"); 442 443 /* 444 * This is recoverable by invalidating the i-cache. 445 */ 446 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 447 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 448 ; 449 450 /* 451 * This will generally be accompanied by an instruction 452 * fetch error report -- only treat MCSR_IF as fatal 453 * if it wasn't due to an L1 parity error. 454 */ 455 reason &= ~MCSR_IF; 456 } 457 458 if (reason & MCSR_DCPERR_MC) { 459 printk("Data Cache Parity Error\n"); 460 recoverable = 0; 461 } 462 463 if (reason & MCSR_L2MMU_MHIT) { 464 printk("Hit on multiple TLB entries\n"); 465 recoverable = 0; 466 } 467 468 if (reason & MCSR_NMI) 469 printk("Non-maskable interrupt\n"); 470 471 if (reason & MCSR_IF) { 472 printk("Instruction Fetch Error Report\n"); 473 recoverable = 0; 474 } 475 476 if (reason & MCSR_LD) { 477 printk("Load Error Report\n"); 478 recoverable = 0; 479 } 480 481 if (reason & MCSR_ST) { 482 printk("Store Error Report\n"); 483 recoverable = 0; 484 } 485 486 if (reason & MCSR_LDG) { 487 printk("Guarded Load Error Report\n"); 488 recoverable = 0; 489 } 490 491 if (reason & MCSR_TLBSYNC) 492 printk("Simultaneous tlbsync operations\n"); 493 494 if (reason & MCSR_BSL2_ERR) { 495 printk("Level 2 Cache Error\n"); 496 recoverable = 0; 497 } 498 499 if (reason & MCSR_MAV) { 500 u64 addr; 501 502 addr = mfspr(SPRN_MCAR); 503 addr |= (u64)mfspr(SPRN_MCARU) << 32; 504 505 printk("Machine Check %s Address: %#llx\n", 506 reason & MCSR_MEA ? "Effective" : "Physical", addr); 507 } 508 509 silent_out: 510 mtspr(SPRN_MCSR, mcsr); 511 return mfspr(SPRN_MCSR) == 0 && recoverable; 512 } 513 514 int machine_check_e500(struct pt_regs *regs) 515 { 516 unsigned long reason = get_mc_reason(regs); 517 518 if (reason & MCSR_BUS_RBERR) { 519 if (fsl_rio_mcheck_exception(regs)) 520 return 1; 521 } 522 523 printk("Machine check in kernel mode.\n"); 524 printk("Caused by (from MCSR=%lx): ", reason); 525 526 if (reason & MCSR_MCP) 527 printk("Machine Check Signal\n"); 528 if (reason & MCSR_ICPERR) 529 printk("Instruction Cache Parity Error\n"); 530 if (reason & MCSR_DCP_PERR) 531 printk("Data Cache Push Parity Error\n"); 532 if (reason & MCSR_DCPERR) 533 printk("Data Cache Parity Error\n"); 534 if (reason & MCSR_BUS_IAERR) 535 printk("Bus - Instruction Address Error\n"); 536 if (reason & MCSR_BUS_RAERR) 537 printk("Bus - Read Address Error\n"); 538 if (reason & MCSR_BUS_WAERR) 539 printk("Bus - Write Address Error\n"); 540 if (reason & MCSR_BUS_IBERR) 541 printk("Bus - Instruction Data Error\n"); 542 if (reason & MCSR_BUS_RBERR) 543 printk("Bus - Read Data Bus Error\n"); 544 if (reason & MCSR_BUS_WBERR) 545 printk("Bus - Read Data Bus Error\n"); 546 if (reason & MCSR_BUS_IPERR) 547 printk("Bus - Instruction Parity Error\n"); 548 if (reason & MCSR_BUS_RPERR) 549 printk("Bus - Read Parity Error\n"); 550 551 return 0; 552 } 553 554 int machine_check_generic(struct pt_regs *regs) 555 { 556 return 0; 557 } 558 #elif defined(CONFIG_E200) 559 int machine_check_e200(struct pt_regs *regs) 560 { 561 unsigned long reason = get_mc_reason(regs); 562 563 printk("Machine check in kernel mode.\n"); 564 printk("Caused by (from MCSR=%lx): ", reason); 565 566 if (reason & MCSR_MCP) 567 printk("Machine Check Signal\n"); 568 if (reason & MCSR_CP_PERR) 569 printk("Cache Push Parity Error\n"); 570 if (reason & MCSR_CPERR) 571 printk("Cache Parity Error\n"); 572 if (reason & MCSR_EXCP_ERR) 573 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 574 if (reason & MCSR_BUS_IRERR) 575 printk("Bus - Read Bus Error on instruction fetch\n"); 576 if (reason & MCSR_BUS_DRERR) 577 printk("Bus - Read Bus Error on data load\n"); 578 if (reason & MCSR_BUS_WRERR) 579 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 580 581 return 0; 582 } 583 #else 584 int machine_check_generic(struct pt_regs *regs) 585 { 586 unsigned long reason = get_mc_reason(regs); 587 588 printk("Machine check in kernel mode.\n"); 589 printk("Caused by (from SRR1=%lx): ", reason); 590 switch (reason & 0x601F0000) { 591 case 0x80000: 592 printk("Machine check signal\n"); 593 break; 594 case 0: /* for 601 */ 595 case 0x40000: 596 case 0x140000: /* 7450 MSS error and TEA */ 597 printk("Transfer error ack signal\n"); 598 break; 599 case 0x20000: 600 printk("Data parity error signal\n"); 601 break; 602 case 0x10000: 603 printk("Address parity error signal\n"); 604 break; 605 case 0x20000000: 606 printk("L1 Data Cache error\n"); 607 break; 608 case 0x40000000: 609 printk("L1 Instruction Cache error\n"); 610 break; 611 case 0x00100000: 612 printk("L2 data cache parity error\n"); 613 break; 614 default: 615 printk("Unknown values in msr\n"); 616 } 617 return 0; 618 } 619 #endif /* everything else */ 620 621 void machine_check_exception(struct pt_regs *regs) 622 { 623 int recover = 0; 624 625 __get_cpu_var(irq_stat).mce_exceptions++; 626 627 /* See if any machine dependent calls. In theory, we would want 628 * to call the CPU first, and call the ppc_md. one if the CPU 629 * one returns a positive number. However there is existing code 630 * that assumes the board gets a first chance, so let's keep it 631 * that way for now and fix things later. --BenH. 632 */ 633 if (ppc_md.machine_check_exception) 634 recover = ppc_md.machine_check_exception(regs); 635 else if (cur_cpu_spec->machine_check) 636 recover = cur_cpu_spec->machine_check(regs); 637 638 if (recover > 0) 639 return; 640 641 #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 642 /* the qspan pci read routines can cause machine checks -- Cort 643 * 644 * yuck !!! that totally needs to go away ! There are better ways 645 * to deal with that than having a wart in the mcheck handler. 646 * -- BenH 647 */ 648 bad_page_fault(regs, regs->dar, SIGBUS); 649 return; 650 #endif 651 652 if (debugger_fault_handler(regs)) 653 return; 654 655 if (check_io_access(regs)) 656 return; 657 658 die("Machine check", regs, SIGBUS); 659 660 /* Must die if the interrupt is not recoverable */ 661 if (!(regs->msr & MSR_RI)) 662 panic("Unrecoverable Machine check"); 663 } 664 665 void SMIException(struct pt_regs *regs) 666 { 667 die("System Management Interrupt", regs, SIGABRT); 668 } 669 670 void unknown_exception(struct pt_regs *regs) 671 { 672 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 673 regs->nip, regs->msr, regs->trap); 674 675 _exception(SIGTRAP, regs, 0, 0); 676 } 677 678 void instruction_breakpoint_exception(struct pt_regs *regs) 679 { 680 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 681 5, SIGTRAP) == NOTIFY_STOP) 682 return; 683 if (debugger_iabr_match(regs)) 684 return; 685 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 686 } 687 688 void RunModeException(struct pt_regs *regs) 689 { 690 _exception(SIGTRAP, regs, 0, 0); 691 } 692 693 void __kprobes single_step_exception(struct pt_regs *regs) 694 { 695 clear_single_step(regs); 696 697 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 698 5, SIGTRAP) == NOTIFY_STOP) 699 return; 700 if (debugger_sstep(regs)) 701 return; 702 703 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 704 } 705 706 /* 707 * After we have successfully emulated an instruction, we have to 708 * check if the instruction was being single-stepped, and if so, 709 * pretend we got a single-step exception. This was pointed out 710 * by Kumar Gala. -- paulus 711 */ 712 static void emulate_single_step(struct pt_regs *regs) 713 { 714 if (single_stepping(regs)) 715 single_step_exception(regs); 716 } 717 718 static inline int __parse_fpscr(unsigned long fpscr) 719 { 720 int ret = 0; 721 722 /* Invalid operation */ 723 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 724 ret = FPE_FLTINV; 725 726 /* Overflow */ 727 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 728 ret = FPE_FLTOVF; 729 730 /* Underflow */ 731 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 732 ret = FPE_FLTUND; 733 734 /* Divide by zero */ 735 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 736 ret = FPE_FLTDIV; 737 738 /* Inexact result */ 739 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 740 ret = FPE_FLTRES; 741 742 return ret; 743 } 744 745 static void parse_fpe(struct pt_regs *regs) 746 { 747 int code = 0; 748 749 flush_fp_to_thread(current); 750 751 code = __parse_fpscr(current->thread.fpscr.val); 752 753 _exception(SIGFPE, regs, code, regs->nip); 754 } 755 756 /* 757 * Illegal instruction emulation support. Originally written to 758 * provide the PVR to user applications using the mfspr rd, PVR. 759 * Return non-zero if we can't emulate, or -EFAULT if the associated 760 * memory access caused an access fault. Return zero on success. 761 * 762 * There are a couple of ways to do this, either "decode" the instruction 763 * or directly match lots of bits. In this case, matching lots of 764 * bits is faster and easier. 765 * 766 */ 767 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 768 { 769 u8 rT = (instword >> 21) & 0x1f; 770 u8 rA = (instword >> 16) & 0x1f; 771 u8 NB_RB = (instword >> 11) & 0x1f; 772 u32 num_bytes; 773 unsigned long EA; 774 int pos = 0; 775 776 /* Early out if we are an invalid form of lswx */ 777 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 778 if ((rT == rA) || (rT == NB_RB)) 779 return -EINVAL; 780 781 EA = (rA == 0) ? 0 : regs->gpr[rA]; 782 783 switch (instword & PPC_INST_STRING_MASK) { 784 case PPC_INST_LSWX: 785 case PPC_INST_STSWX: 786 EA += NB_RB; 787 num_bytes = regs->xer & 0x7f; 788 break; 789 case PPC_INST_LSWI: 790 case PPC_INST_STSWI: 791 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 792 break; 793 default: 794 return -EINVAL; 795 } 796 797 while (num_bytes != 0) 798 { 799 u8 val; 800 u32 shift = 8 * (3 - (pos & 0x3)); 801 802 switch ((instword & PPC_INST_STRING_MASK)) { 803 case PPC_INST_LSWX: 804 case PPC_INST_LSWI: 805 if (get_user(val, (u8 __user *)EA)) 806 return -EFAULT; 807 /* first time updating this reg, 808 * zero it out */ 809 if (pos == 0) 810 regs->gpr[rT] = 0; 811 regs->gpr[rT] |= val << shift; 812 break; 813 case PPC_INST_STSWI: 814 case PPC_INST_STSWX: 815 val = regs->gpr[rT] >> shift; 816 if (put_user(val, (u8 __user *)EA)) 817 return -EFAULT; 818 break; 819 } 820 /* move EA to next address */ 821 EA += 1; 822 num_bytes--; 823 824 /* manage our position within the register */ 825 if (++pos == 4) { 826 pos = 0; 827 if (++rT == 32) 828 rT = 0; 829 } 830 } 831 832 return 0; 833 } 834 835 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 836 { 837 u32 ra,rs; 838 unsigned long tmp; 839 840 ra = (instword >> 16) & 0x1f; 841 rs = (instword >> 21) & 0x1f; 842 843 tmp = regs->gpr[rs]; 844 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 845 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 846 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 847 regs->gpr[ra] = tmp; 848 849 return 0; 850 } 851 852 static int emulate_isel(struct pt_regs *regs, u32 instword) 853 { 854 u8 rT = (instword >> 21) & 0x1f; 855 u8 rA = (instword >> 16) & 0x1f; 856 u8 rB = (instword >> 11) & 0x1f; 857 u8 BC = (instword >> 6) & 0x1f; 858 u8 bit; 859 unsigned long tmp; 860 861 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 862 bit = (regs->ccr >> (31 - BC)) & 0x1; 863 864 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 865 866 return 0; 867 } 868 869 static int emulate_instruction(struct pt_regs *regs) 870 { 871 u32 instword; 872 u32 rd; 873 874 if (!user_mode(regs) || (regs->msr & MSR_LE)) 875 return -EINVAL; 876 CHECK_FULL_REGS(regs); 877 878 if (get_user(instword, (u32 __user *)(regs->nip))) 879 return -EFAULT; 880 881 /* Emulate the mfspr rD, PVR. */ 882 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 883 PPC_WARN_EMULATED(mfpvr, regs); 884 rd = (instword >> 21) & 0x1f; 885 regs->gpr[rd] = mfspr(SPRN_PVR); 886 return 0; 887 } 888 889 /* Emulating the dcba insn is just a no-op. */ 890 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 891 PPC_WARN_EMULATED(dcba, regs); 892 return 0; 893 } 894 895 /* Emulate the mcrxr insn. */ 896 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 897 int shift = (instword >> 21) & 0x1c; 898 unsigned long msk = 0xf0000000UL >> shift; 899 900 PPC_WARN_EMULATED(mcrxr, regs); 901 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 902 regs->xer &= ~0xf0000000UL; 903 return 0; 904 } 905 906 /* Emulate load/store string insn. */ 907 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 908 PPC_WARN_EMULATED(string, regs); 909 return emulate_string_inst(regs, instword); 910 } 911 912 /* Emulate the popcntb (Population Count Bytes) instruction. */ 913 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 914 PPC_WARN_EMULATED(popcntb, regs); 915 return emulate_popcntb_inst(regs, instword); 916 } 917 918 /* Emulate isel (Integer Select) instruction */ 919 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 920 PPC_WARN_EMULATED(isel, regs); 921 return emulate_isel(regs, instword); 922 } 923 924 #ifdef CONFIG_PPC64 925 /* Emulate the mfspr rD, DSCR. */ 926 if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) && 927 cpu_has_feature(CPU_FTR_DSCR)) { 928 PPC_WARN_EMULATED(mfdscr, regs); 929 rd = (instword >> 21) & 0x1f; 930 regs->gpr[rd] = mfspr(SPRN_DSCR); 931 return 0; 932 } 933 /* Emulate the mtspr DSCR, rD. */ 934 if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) && 935 cpu_has_feature(CPU_FTR_DSCR)) { 936 PPC_WARN_EMULATED(mtdscr, regs); 937 rd = (instword >> 21) & 0x1f; 938 mtspr(SPRN_DSCR, regs->gpr[rd]); 939 current->thread.dscr_inherit = 1; 940 return 0; 941 } 942 #endif 943 944 return -EINVAL; 945 } 946 947 int is_valid_bugaddr(unsigned long addr) 948 { 949 return is_kernel_addr(addr); 950 } 951 952 void __kprobes program_check_exception(struct pt_regs *regs) 953 { 954 unsigned int reason = get_reason(regs); 955 extern int do_mathemu(struct pt_regs *regs); 956 957 /* We can now get here via a FP Unavailable exception if the core 958 * has no FPU, in that case the reason flags will be 0 */ 959 960 if (reason & REASON_FP) { 961 /* IEEE FP exception */ 962 parse_fpe(regs); 963 return; 964 } 965 if (reason & REASON_TRAP) { 966 /* Debugger is first in line to stop recursive faults in 967 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 968 if (debugger_bpt(regs)) 969 return; 970 971 /* trap exception */ 972 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 973 == NOTIFY_STOP) 974 return; 975 976 if (!(regs->msr & MSR_PR) && /* not user-mode */ 977 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 978 regs->nip += 4; 979 return; 980 } 981 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 982 return; 983 } 984 985 local_irq_enable(); 986 987 #ifdef CONFIG_MATH_EMULATION 988 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 989 * but there seems to be a hardware bug on the 405GP (RevD) 990 * that means ESR is sometimes set incorrectly - either to 991 * ESR_DST (!?) or 0. In the process of chasing this with the 992 * hardware people - not sure if it can happen on any illegal 993 * instruction or only on FP instructions, whether there is a 994 * pattern to occurrences etc. -dgibson 31/Mar/2003 */ 995 switch (do_mathemu(regs)) { 996 case 0: 997 emulate_single_step(regs); 998 return; 999 case 1: { 1000 int code = 0; 1001 code = __parse_fpscr(current->thread.fpscr.val); 1002 _exception(SIGFPE, regs, code, regs->nip); 1003 return; 1004 } 1005 case -EFAULT: 1006 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1007 return; 1008 } 1009 /* fall through on any other errors */ 1010 #endif /* CONFIG_MATH_EMULATION */ 1011 1012 /* Try to emulate it if we should. */ 1013 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1014 switch (emulate_instruction(regs)) { 1015 case 0: 1016 regs->nip += 4; 1017 emulate_single_step(regs); 1018 return; 1019 case -EFAULT: 1020 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1021 return; 1022 } 1023 } 1024 1025 if (reason & REASON_PRIVILEGED) 1026 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1027 else 1028 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1029 } 1030 1031 void alignment_exception(struct pt_regs *regs) 1032 { 1033 int sig, code, fixed = 0; 1034 1035 /* we don't implement logging of alignment exceptions */ 1036 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1037 fixed = fix_alignment(regs); 1038 1039 if (fixed == 1) { 1040 regs->nip += 4; /* skip over emulated instruction */ 1041 emulate_single_step(regs); 1042 return; 1043 } 1044 1045 /* Operand address was bad */ 1046 if (fixed == -EFAULT) { 1047 sig = SIGSEGV; 1048 code = SEGV_ACCERR; 1049 } else { 1050 sig = SIGBUS; 1051 code = BUS_ADRALN; 1052 } 1053 if (user_mode(regs)) 1054 _exception(sig, regs, code, regs->dar); 1055 else 1056 bad_page_fault(regs, regs->dar, sig); 1057 } 1058 1059 void StackOverflow(struct pt_regs *regs) 1060 { 1061 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 1062 current, regs->gpr[1]); 1063 debugger(regs); 1064 show_regs(regs); 1065 panic("kernel stack overflow"); 1066 } 1067 1068 void nonrecoverable_exception(struct pt_regs *regs) 1069 { 1070 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 1071 regs->nip, regs->msr); 1072 debugger(regs); 1073 die("nonrecoverable exception", regs, SIGKILL); 1074 } 1075 1076 void trace_syscall(struct pt_regs *regs) 1077 { 1078 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 1079 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], 1080 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 1081 } 1082 1083 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1084 { 1085 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1086 "%lx at %lx\n", regs->trap, regs->nip); 1087 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1088 } 1089 1090 void altivec_unavailable_exception(struct pt_regs *regs) 1091 { 1092 if (user_mode(regs)) { 1093 /* A user program has executed an altivec instruction, 1094 but this kernel doesn't support altivec. */ 1095 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1096 return; 1097 } 1098 1099 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1100 "%lx at %lx\n", regs->trap, regs->nip); 1101 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1102 } 1103 1104 void vsx_unavailable_exception(struct pt_regs *regs) 1105 { 1106 if (user_mode(regs)) { 1107 /* A user program has executed an vsx instruction, 1108 but this kernel doesn't support vsx. */ 1109 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1110 return; 1111 } 1112 1113 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1114 "%lx at %lx\n", regs->trap, regs->nip); 1115 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1116 } 1117 1118 void performance_monitor_exception(struct pt_regs *regs) 1119 { 1120 __get_cpu_var(irq_stat).pmu_irqs++; 1121 1122 perf_irq(regs); 1123 } 1124 1125 #ifdef CONFIG_8xx 1126 void SoftwareEmulation(struct pt_regs *regs) 1127 { 1128 extern int do_mathemu(struct pt_regs *); 1129 extern int Soft_emulate_8xx(struct pt_regs *); 1130 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) 1131 int errcode; 1132 #endif 1133 1134 CHECK_FULL_REGS(regs); 1135 1136 if (!user_mode(regs)) { 1137 debugger(regs); 1138 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 1139 } 1140 1141 #ifdef CONFIG_MATH_EMULATION 1142 errcode = do_mathemu(regs); 1143 if (errcode >= 0) 1144 PPC_WARN_EMULATED(math, regs); 1145 1146 switch (errcode) { 1147 case 0: 1148 emulate_single_step(regs); 1149 return; 1150 case 1: { 1151 int code = 0; 1152 code = __parse_fpscr(current->thread.fpscr.val); 1153 _exception(SIGFPE, regs, code, regs->nip); 1154 return; 1155 } 1156 case -EFAULT: 1157 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1158 return; 1159 default: 1160 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1161 return; 1162 } 1163 1164 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1165 errcode = Soft_emulate_8xx(regs); 1166 if (errcode >= 0) 1167 PPC_WARN_EMULATED(8xx, regs); 1168 1169 switch (errcode) { 1170 case 0: 1171 emulate_single_step(regs); 1172 return; 1173 case 1: 1174 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1175 return; 1176 case -EFAULT: 1177 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1178 return; 1179 } 1180 #else 1181 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1182 #endif 1183 } 1184 #endif /* CONFIG_8xx */ 1185 1186 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1187 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1188 { 1189 int changed = 0; 1190 /* 1191 * Determine the cause of the debug event, clear the 1192 * event flags and send a trap to the handler. Torez 1193 */ 1194 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1195 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1196 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1197 current->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1198 #endif 1199 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1200 5); 1201 changed |= 0x01; 1202 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1203 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1204 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 1205 6); 1206 changed |= 0x01; 1207 } else if (debug_status & DBSR_IAC1) { 1208 current->thread.dbcr0 &= ~DBCR0_IAC1; 1209 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1210 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1211 1); 1212 changed |= 0x01; 1213 } else if (debug_status & DBSR_IAC2) { 1214 current->thread.dbcr0 &= ~DBCR0_IAC2; 1215 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1216 2); 1217 changed |= 0x01; 1218 } else if (debug_status & DBSR_IAC3) { 1219 current->thread.dbcr0 &= ~DBCR0_IAC3; 1220 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1221 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1222 3); 1223 changed |= 0x01; 1224 } else if (debug_status & DBSR_IAC4) { 1225 current->thread.dbcr0 &= ~DBCR0_IAC4; 1226 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1227 4); 1228 changed |= 0x01; 1229 } 1230 /* 1231 * At the point this routine was called, the MSR(DE) was turned off. 1232 * Check all other debug flags and see if that bit needs to be turned 1233 * back on or not. 1234 */ 1235 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) 1236 regs->msr |= MSR_DE; 1237 else 1238 /* Make sure the IDM flag is off */ 1239 current->thread.dbcr0 &= ~DBCR0_IDM; 1240 1241 if (changed & 0x01) 1242 mtspr(SPRN_DBCR0, current->thread.dbcr0); 1243 } 1244 1245 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) 1246 { 1247 current->thread.dbsr = debug_status; 1248 1249 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1250 * on server, it stops on the target of the branch. In order to simulate 1251 * the server behaviour, we thus restart right away with a single step 1252 * instead of stopping here when hitting a BT 1253 */ 1254 if (debug_status & DBSR_BT) { 1255 regs->msr &= ~MSR_DE; 1256 1257 /* Disable BT */ 1258 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1259 /* Clear the BT event */ 1260 mtspr(SPRN_DBSR, DBSR_BT); 1261 1262 /* Do the single step trick only when coming from userspace */ 1263 if (user_mode(regs)) { 1264 current->thread.dbcr0 &= ~DBCR0_BT; 1265 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1266 regs->msr |= MSR_DE; 1267 return; 1268 } 1269 1270 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1271 5, SIGTRAP) == NOTIFY_STOP) { 1272 return; 1273 } 1274 if (debugger_sstep(regs)) 1275 return; 1276 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1277 regs->msr &= ~MSR_DE; 1278 1279 /* Disable instruction completion */ 1280 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1281 /* Clear the instruction completion event */ 1282 mtspr(SPRN_DBSR, DBSR_IC); 1283 1284 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1285 5, SIGTRAP) == NOTIFY_STOP) { 1286 return; 1287 } 1288 1289 if (debugger_sstep(regs)) 1290 return; 1291 1292 if (user_mode(regs)) { 1293 current->thread.dbcr0 &= ~DBCR0_IC; 1294 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1295 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, 1296 current->thread.dbcr1)) 1297 regs->msr |= MSR_DE; 1298 else 1299 /* Make sure the IDM bit is off */ 1300 current->thread.dbcr0 &= ~DBCR0_IDM; 1301 #endif 1302 } 1303 1304 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1305 } else 1306 handle_debug(regs, debug_status); 1307 } 1308 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1309 1310 #if !defined(CONFIG_TAU_INT) 1311 void TAUException(struct pt_regs *regs) 1312 { 1313 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1314 regs->nip, regs->msr, regs->trap, print_tainted()); 1315 } 1316 #endif /* CONFIG_INT_TAU */ 1317 1318 #ifdef CONFIG_ALTIVEC 1319 void altivec_assist_exception(struct pt_regs *regs) 1320 { 1321 int err; 1322 1323 if (!user_mode(regs)) { 1324 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1325 " at %lx\n", regs->nip); 1326 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1327 } 1328 1329 flush_altivec_to_thread(current); 1330 1331 PPC_WARN_EMULATED(altivec, regs); 1332 err = emulate_altivec(regs); 1333 if (err == 0) { 1334 regs->nip += 4; /* skip emulated instruction */ 1335 emulate_single_step(regs); 1336 return; 1337 } 1338 1339 if (err == -EFAULT) { 1340 /* got an error reading the instruction */ 1341 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1342 } else { 1343 /* didn't recognize the instruction */ 1344 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1345 if (printk_ratelimit()) 1346 printk(KERN_ERR "Unrecognized altivec instruction " 1347 "in %s at %lx\n", current->comm, regs->nip); 1348 current->thread.vscr.u[3] |= 0x10000; 1349 } 1350 } 1351 #endif /* CONFIG_ALTIVEC */ 1352 1353 #ifdef CONFIG_VSX 1354 void vsx_assist_exception(struct pt_regs *regs) 1355 { 1356 if (!user_mode(regs)) { 1357 printk(KERN_EMERG "VSX assist exception in kernel mode" 1358 " at %lx\n", regs->nip); 1359 die("Kernel VSX assist exception", regs, SIGILL); 1360 } 1361 1362 flush_vsx_to_thread(current); 1363 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); 1364 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1365 } 1366 #endif /* CONFIG_VSX */ 1367 1368 #ifdef CONFIG_FSL_BOOKE 1369 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1370 unsigned long error_code) 1371 { 1372 /* We treat cache locking instructions from the user 1373 * as priv ops, in the future we could try to do 1374 * something smarter 1375 */ 1376 if (error_code & (ESR_DLK|ESR_ILK)) 1377 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1378 return; 1379 } 1380 #endif /* CONFIG_FSL_BOOKE */ 1381 1382 #ifdef CONFIG_SPE 1383 void SPEFloatingPointException(struct pt_regs *regs) 1384 { 1385 extern int do_spe_mathemu(struct pt_regs *regs); 1386 unsigned long spefscr; 1387 int fpexc_mode; 1388 int code = 0; 1389 int err; 1390 1391 preempt_disable(); 1392 if (regs->msr & MSR_SPE) 1393 giveup_spe(current); 1394 preempt_enable(); 1395 1396 spefscr = current->thread.spefscr; 1397 fpexc_mode = current->thread.fpexc_mode; 1398 1399 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1400 code = FPE_FLTOVF; 1401 } 1402 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1403 code = FPE_FLTUND; 1404 } 1405 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1406 code = FPE_FLTDIV; 1407 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1408 code = FPE_FLTINV; 1409 } 1410 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1411 code = FPE_FLTRES; 1412 1413 err = do_spe_mathemu(regs); 1414 if (err == 0) { 1415 regs->nip += 4; /* skip emulated instruction */ 1416 emulate_single_step(regs); 1417 return; 1418 } 1419 1420 if (err == -EFAULT) { 1421 /* got an error reading the instruction */ 1422 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1423 } else if (err == -EINVAL) { 1424 /* didn't recognize the instruction */ 1425 printk(KERN_ERR "unrecognized spe instruction " 1426 "in %s at %lx\n", current->comm, regs->nip); 1427 } else { 1428 _exception(SIGFPE, regs, code, regs->nip); 1429 } 1430 1431 return; 1432 } 1433 1434 void SPEFloatingPointRoundException(struct pt_regs *regs) 1435 { 1436 extern int speround_handler(struct pt_regs *regs); 1437 int err; 1438 1439 preempt_disable(); 1440 if (regs->msr & MSR_SPE) 1441 giveup_spe(current); 1442 preempt_enable(); 1443 1444 regs->nip -= 4; 1445 err = speround_handler(regs); 1446 if (err == 0) { 1447 regs->nip += 4; /* skip emulated instruction */ 1448 emulate_single_step(regs); 1449 return; 1450 } 1451 1452 if (err == -EFAULT) { 1453 /* got an error reading the instruction */ 1454 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1455 } else if (err == -EINVAL) { 1456 /* didn't recognize the instruction */ 1457 printk(KERN_ERR "unrecognized spe instruction " 1458 "in %s at %lx\n", current->comm, regs->nip); 1459 } else { 1460 _exception(SIGFPE, regs, 0, regs->nip); 1461 return; 1462 } 1463 } 1464 #endif 1465 1466 /* 1467 * We enter here if we get an unrecoverable exception, that is, one 1468 * that happened at a point where the RI (recoverable interrupt) bit 1469 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1470 * we therefore lost state by taking this exception. 1471 */ 1472 void unrecoverable_exception(struct pt_regs *regs) 1473 { 1474 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1475 regs->trap, regs->nip); 1476 die("Unrecoverable exception", regs, SIGABRT); 1477 } 1478 1479 #ifdef CONFIG_BOOKE_WDT 1480 /* 1481 * Default handler for a Watchdog exception, 1482 * spins until a reboot occurs 1483 */ 1484 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1485 { 1486 /* Generic WatchdogHandler, implement your own */ 1487 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1488 return; 1489 } 1490 1491 void WatchdogException(struct pt_regs *regs) 1492 { 1493 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1494 WatchdogHandler(regs); 1495 } 1496 #endif 1497 1498 /* 1499 * We enter here if we discover during exception entry that we are 1500 * running in supervisor mode with a userspace value in the stack pointer. 1501 */ 1502 void kernel_bad_stack(struct pt_regs *regs) 1503 { 1504 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1505 regs->gpr[1], regs->nip); 1506 die("Bad kernel stack pointer", regs, SIGABRT); 1507 } 1508 1509 void __init trap_init(void) 1510 { 1511 } 1512 1513 1514 #ifdef CONFIG_PPC_EMULATED_STATS 1515 1516 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 1517 1518 struct ppc_emulated ppc_emulated = { 1519 #ifdef CONFIG_ALTIVEC 1520 WARN_EMULATED_SETUP(altivec), 1521 #endif 1522 WARN_EMULATED_SETUP(dcba), 1523 WARN_EMULATED_SETUP(dcbz), 1524 WARN_EMULATED_SETUP(fp_pair), 1525 WARN_EMULATED_SETUP(isel), 1526 WARN_EMULATED_SETUP(mcrxr), 1527 WARN_EMULATED_SETUP(mfpvr), 1528 WARN_EMULATED_SETUP(multiple), 1529 WARN_EMULATED_SETUP(popcntb), 1530 WARN_EMULATED_SETUP(spe), 1531 WARN_EMULATED_SETUP(string), 1532 WARN_EMULATED_SETUP(unaligned), 1533 #ifdef CONFIG_MATH_EMULATION 1534 WARN_EMULATED_SETUP(math), 1535 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1536 WARN_EMULATED_SETUP(8xx), 1537 #endif 1538 #ifdef CONFIG_VSX 1539 WARN_EMULATED_SETUP(vsx), 1540 #endif 1541 #ifdef CONFIG_PPC64 1542 WARN_EMULATED_SETUP(mfdscr), 1543 WARN_EMULATED_SETUP(mtdscr), 1544 #endif 1545 }; 1546 1547 u32 ppc_warn_emulated; 1548 1549 void ppc_warn_emulated_print(const char *type) 1550 { 1551 if (printk_ratelimit()) 1552 pr_warning("%s used emulated %s instruction\n", current->comm, 1553 type); 1554 } 1555 1556 static int __init ppc_warn_emulated_init(void) 1557 { 1558 struct dentry *dir, *d; 1559 unsigned int i; 1560 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 1561 1562 if (!powerpc_debugfs_root) 1563 return -ENODEV; 1564 1565 dir = debugfs_create_dir("emulated_instructions", 1566 powerpc_debugfs_root); 1567 if (!dir) 1568 return -ENOMEM; 1569 1570 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 1571 &ppc_warn_emulated); 1572 if (!d) 1573 goto fail; 1574 1575 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 1576 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 1577 (u32 *)&entries[i].val.counter); 1578 if (!d) 1579 goto fail; 1580 } 1581 1582 return 0; 1583 1584 fail: 1585 debugfs_remove_recursive(dir); 1586 return -ENOMEM; 1587 } 1588 1589 device_initcall(ppc_warn_emulated_init); 1590 1591 #endif /* CONFIG_PPC_EMULATED_STATS */ 1592