xref: /openbmc/linux/arch/powerpc/kernel/traps.c (revision e7df0d88c455c915376397b4bd72a83b9ed656f7)
114cf11afSPaul Mackerras /*
214cf11afSPaul Mackerras  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
3fe04b112SScott Wood  *  Copyright 2007-2010 Freescale Semiconductor, Inc.
414cf11afSPaul Mackerras  *
514cf11afSPaul Mackerras  *  This program is free software; you can redistribute it and/or
614cf11afSPaul Mackerras  *  modify it under the terms of the GNU General Public License
714cf11afSPaul Mackerras  *  as published by the Free Software Foundation; either version
814cf11afSPaul Mackerras  *  2 of the License, or (at your option) any later version.
914cf11afSPaul Mackerras  *
1014cf11afSPaul Mackerras  *  Modified by Cort Dougan (cort@cs.nmt.edu)
1114cf11afSPaul Mackerras  *  and Paul Mackerras (paulus@samba.org)
1214cf11afSPaul Mackerras  */
1314cf11afSPaul Mackerras 
1414cf11afSPaul Mackerras /*
1514cf11afSPaul Mackerras  * This file handles the architecture-dependent parts of hardware exceptions
1614cf11afSPaul Mackerras  */
1714cf11afSPaul Mackerras 
1814cf11afSPaul Mackerras #include <linux/errno.h>
1914cf11afSPaul Mackerras #include <linux/sched.h>
2014cf11afSPaul Mackerras #include <linux/kernel.h>
2114cf11afSPaul Mackerras #include <linux/mm.h>
2214cf11afSPaul Mackerras #include <linux/stddef.h>
2314cf11afSPaul Mackerras #include <linux/unistd.h>
248dad3f92SPaul Mackerras #include <linux/ptrace.h>
2514cf11afSPaul Mackerras #include <linux/user.h>
2614cf11afSPaul Mackerras #include <linux/interrupt.h>
2714cf11afSPaul Mackerras #include <linux/init.h>
2814cf11afSPaul Mackerras #include <linux/module.h>
298dad3f92SPaul Mackerras #include <linux/prctl.h>
3014cf11afSPaul Mackerras #include <linux/delay.h>
3114cf11afSPaul Mackerras #include <linux/kprobes.h>
32cc532915SMichael Ellerman #include <linux/kexec.h>
335474c120SMichael Hanselmann #include <linux/backlight.h>
3473c9ceabSJeremy Fitzhardinge #include <linux/bug.h>
351eeb66a1SChristoph Hellwig #include <linux/kdebug.h>
3680947e7cSGeert Uytterhoeven #include <linux/debugfs.h>
3776462232SChristian Dietrich #include <linux/ratelimit.h>
38ba12eedeSLi Zhong #include <linux/context_tracking.h>
3914cf11afSPaul Mackerras 
4080947e7cSGeert Uytterhoeven #include <asm/emulated_ops.h>
4114cf11afSPaul Mackerras #include <asm/pgtable.h>
4214cf11afSPaul Mackerras #include <asm/uaccess.h>
4314cf11afSPaul Mackerras #include <asm/io.h>
4486417780SPaul Mackerras #include <asm/machdep.h>
4586417780SPaul Mackerras #include <asm/rtas.h>
46f7f6f4feSDavid Gibson #include <asm/pmc.h>
4714cf11afSPaul Mackerras #include <asm/reg.h>
4814cf11afSPaul Mackerras #ifdef CONFIG_PMAC_BACKLIGHT
4914cf11afSPaul Mackerras #include <asm/backlight.h>
5014cf11afSPaul Mackerras #endif
51dc1c1ca3SStephen Rothwell #ifdef CONFIG_PPC64
5286417780SPaul Mackerras #include <asm/firmware.h>
53dc1c1ca3SStephen Rothwell #include <asm/processor.h>
546ce6c629SMichael Neuling #include <asm/tm.h>
55dc1c1ca3SStephen Rothwell #endif
56c0ce7d08SDavid Wilder #include <asm/kexec.h>
5716c57b36SKumar Gala #include <asm/ppc-opcode.h>
58cce1f106SShaohui Xie #include <asm/rio.h>
59ebaeb5aeSMahesh Salgaonkar #include <asm/fadump.h>
60ae3a197eSDavid Howells #include <asm/switch_to.h>
61f54db641SMichael Neuling #include <asm/tm.h>
62ae3a197eSDavid Howells #include <asm/debug.h>
634e0e3435SHongtao Jia #include <sysdev/fsl_pci.h>
64dc1c1ca3SStephen Rothwell 
657dbb922cSOlof Johansson #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
665be3492fSAnton Blanchard int (*__debugger)(struct pt_regs *regs) __read_mostly;
675be3492fSAnton Blanchard int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
685be3492fSAnton Blanchard int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
695be3492fSAnton Blanchard int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
705be3492fSAnton Blanchard int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
719422de3eSMichael Neuling int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
725be3492fSAnton Blanchard int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
7314cf11afSPaul Mackerras 
7414cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger);
7514cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_ipi);
7614cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_bpt);
7714cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_sstep);
7814cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_iabr_match);
799422de3eSMichael Neuling EXPORT_SYMBOL(__debugger_break_match);
8014cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_fault_handler);
8114cf11afSPaul Mackerras #endif
8214cf11afSPaul Mackerras 
838b3c34cfSMichael Neuling /* Transactional Memory trap debug */
848b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW
858b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x)
868b3c34cfSMichael Neuling #else
878b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0)
888b3c34cfSMichael Neuling #endif
898b3c34cfSMichael Neuling 
9014cf11afSPaul Mackerras /*
9114cf11afSPaul Mackerras  * Trap & Exception support
9214cf11afSPaul Mackerras  */
9314cf11afSPaul Mackerras 
946031d9d9Santon@samba.org #ifdef CONFIG_PMAC_BACKLIGHT
956031d9d9Santon@samba.org static void pmac_backlight_unblank(void)
966031d9d9Santon@samba.org {
976031d9d9Santon@samba.org 	mutex_lock(&pmac_backlight_mutex);
986031d9d9Santon@samba.org 	if (pmac_backlight) {
996031d9d9Santon@samba.org 		struct backlight_properties *props;
1006031d9d9Santon@samba.org 
1016031d9d9Santon@samba.org 		props = &pmac_backlight->props;
1026031d9d9Santon@samba.org 		props->brightness = props->max_brightness;
1036031d9d9Santon@samba.org 		props->power = FB_BLANK_UNBLANK;
1046031d9d9Santon@samba.org 		backlight_update_status(pmac_backlight);
1056031d9d9Santon@samba.org 	}
1066031d9d9Santon@samba.org 	mutex_unlock(&pmac_backlight_mutex);
1076031d9d9Santon@samba.org }
1086031d9d9Santon@samba.org #else
1096031d9d9Santon@samba.org static inline void pmac_backlight_unblank(void) { }
1106031d9d9Santon@samba.org #endif
1116031d9d9Santon@samba.org 
112760ca4dcSAnton Blanchard static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
113760ca4dcSAnton Blanchard static int die_owner = -1;
114760ca4dcSAnton Blanchard static unsigned int die_nest_count;
115c0ce7d08SDavid Wilder static int die_counter;
116760ca4dcSAnton Blanchard 
117760ca4dcSAnton Blanchard static unsigned __kprobes long oops_begin(struct pt_regs *regs)
118760ca4dcSAnton Blanchard {
119760ca4dcSAnton Blanchard 	int cpu;
12034c2a14fSanton@samba.org 	unsigned long flags;
12114cf11afSPaul Mackerras 
12214cf11afSPaul Mackerras 	if (debugger(regs))
12314cf11afSPaul Mackerras 		return 1;
12414cf11afSPaul Mackerras 
125293e4688Santon@samba.org 	oops_enter();
126293e4688Santon@samba.org 
127760ca4dcSAnton Blanchard 	/* racy, but better than risking deadlock. */
128760ca4dcSAnton Blanchard 	raw_local_irq_save(flags);
129760ca4dcSAnton Blanchard 	cpu = smp_processor_id();
130760ca4dcSAnton Blanchard 	if (!arch_spin_trylock(&die_lock)) {
131760ca4dcSAnton Blanchard 		if (cpu == die_owner)
132760ca4dcSAnton Blanchard 			/* nested oops. should stop eventually */;
133760ca4dcSAnton Blanchard 		else
134760ca4dcSAnton Blanchard 			arch_spin_lock(&die_lock);
135760ca4dcSAnton Blanchard 	}
136760ca4dcSAnton Blanchard 	die_nest_count++;
137760ca4dcSAnton Blanchard 	die_owner = cpu;
13814cf11afSPaul Mackerras 	console_verbose();
13914cf11afSPaul Mackerras 	bust_spinlocks(1);
1406031d9d9Santon@samba.org 	if (machine_is(powermac))
1416031d9d9Santon@samba.org 		pmac_backlight_unblank();
142760ca4dcSAnton Blanchard 	return flags;
14334c2a14fSanton@samba.org }
1445474c120SMichael Hanselmann 
145760ca4dcSAnton Blanchard static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
146760ca4dcSAnton Blanchard 			       int signr)
147760ca4dcSAnton Blanchard {
14814cf11afSPaul Mackerras 	bust_spinlocks(0);
149760ca4dcSAnton Blanchard 	die_owner = -1;
150373d4d09SRusty Russell 	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
151760ca4dcSAnton Blanchard 	die_nest_count--;
15258154c8cSAnton Blanchard 	oops_exit();
15358154c8cSAnton Blanchard 	printk("\n");
154760ca4dcSAnton Blanchard 	if (!die_nest_count)
155760ca4dcSAnton Blanchard 		/* Nest count reaches zero, release the lock. */
156760ca4dcSAnton Blanchard 		arch_spin_unlock(&die_lock);
157760ca4dcSAnton Blanchard 	raw_local_irq_restore(flags);
158cc532915SMichael Ellerman 
159ebaeb5aeSMahesh Salgaonkar 	crash_fadump(regs, "die oops");
160ebaeb5aeSMahesh Salgaonkar 
1619b00ac06SAnton Blanchard 	/*
1629b00ac06SAnton Blanchard 	 * A system reset (0x100) is a request to dump, so we always send
1639b00ac06SAnton Blanchard 	 * it through the crashdump code.
1649b00ac06SAnton Blanchard 	 */
1659b00ac06SAnton Blanchard 	if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
166cc532915SMichael Ellerman 		crash_kexec(regs);
1679b00ac06SAnton Blanchard 
1689b00ac06SAnton Blanchard 		/*
1699b00ac06SAnton Blanchard 		 * We aren't the primary crash CPU. We need to send it
1709b00ac06SAnton Blanchard 		 * to a holding pattern to avoid it ending up in the panic
1719b00ac06SAnton Blanchard 		 * code.
1729b00ac06SAnton Blanchard 		 */
173c0ce7d08SDavid Wilder 		crash_kexec_secondary(regs);
1749b00ac06SAnton Blanchard 	}
17514cf11afSPaul Mackerras 
176760ca4dcSAnton Blanchard 	if (!signr)
177760ca4dcSAnton Blanchard 		return;
178760ca4dcSAnton Blanchard 
17958154c8cSAnton Blanchard 	/*
18058154c8cSAnton Blanchard 	 * While our oops output is serialised by a spinlock, output
18158154c8cSAnton Blanchard 	 * from panic() called below can race and corrupt it. If we
18258154c8cSAnton Blanchard 	 * know we are going to panic, delay for 1 second so we have a
18358154c8cSAnton Blanchard 	 * chance to get clean backtraces from all CPUs that are oopsing.
18458154c8cSAnton Blanchard 	 */
18558154c8cSAnton Blanchard 	if (in_interrupt() || panic_on_oops || !current->pid ||
18658154c8cSAnton Blanchard 	    is_global_init(current)) {
18758154c8cSAnton Blanchard 		mdelay(MSEC_PER_SEC);
18858154c8cSAnton Blanchard 	}
18958154c8cSAnton Blanchard 
19014cf11afSPaul Mackerras 	if (in_interrupt())
19114cf11afSPaul Mackerras 		panic("Fatal exception in interrupt");
192cea6a4baSHorms 	if (panic_on_oops)
193012c437dSHorms 		panic("Fatal exception");
194760ca4dcSAnton Blanchard 	do_exit(signr);
195760ca4dcSAnton Blanchard }
196cea6a4baSHorms 
197760ca4dcSAnton Blanchard static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
198760ca4dcSAnton Blanchard {
199760ca4dcSAnton Blanchard 	printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
200760ca4dcSAnton Blanchard #ifdef CONFIG_PREEMPT
201760ca4dcSAnton Blanchard 	printk("PREEMPT ");
202760ca4dcSAnton Blanchard #endif
203760ca4dcSAnton Blanchard #ifdef CONFIG_SMP
204760ca4dcSAnton Blanchard 	printk("SMP NR_CPUS=%d ", NR_CPUS);
205760ca4dcSAnton Blanchard #endif
206*e7df0d88SJoonsoo Kim 	if (debug_pagealloc_enabled())
207760ca4dcSAnton Blanchard 		printk("DEBUG_PAGEALLOC ");
208760ca4dcSAnton Blanchard #ifdef CONFIG_NUMA
209760ca4dcSAnton Blanchard 	printk("NUMA ");
210760ca4dcSAnton Blanchard #endif
211760ca4dcSAnton Blanchard 	printk("%s\n", ppc_md.name ? ppc_md.name : "");
212760ca4dcSAnton Blanchard 
213760ca4dcSAnton Blanchard 	if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
214760ca4dcSAnton Blanchard 		return 1;
215760ca4dcSAnton Blanchard 
216760ca4dcSAnton Blanchard 	print_modules();
217760ca4dcSAnton Blanchard 	show_regs(regs);
21814cf11afSPaul Mackerras 
21914cf11afSPaul Mackerras 	return 0;
22014cf11afSPaul Mackerras }
22114cf11afSPaul Mackerras 
222760ca4dcSAnton Blanchard void die(const char *str, struct pt_regs *regs, long err)
223760ca4dcSAnton Blanchard {
224760ca4dcSAnton Blanchard 	unsigned long flags = oops_begin(regs);
225760ca4dcSAnton Blanchard 
226760ca4dcSAnton Blanchard 	if (__die(str, regs, err))
227760ca4dcSAnton Blanchard 		err = 0;
228760ca4dcSAnton Blanchard 	oops_end(flags, regs, err);
229760ca4dcSAnton Blanchard }
230760ca4dcSAnton Blanchard 
23125baa35bSOleg Nesterov void user_single_step_siginfo(struct task_struct *tsk,
23225baa35bSOleg Nesterov 				struct pt_regs *regs, siginfo_t *info)
23325baa35bSOleg Nesterov {
23425baa35bSOleg Nesterov 	memset(info, 0, sizeof(*info));
23525baa35bSOleg Nesterov 	info->si_signo = SIGTRAP;
23625baa35bSOleg Nesterov 	info->si_code = TRAP_TRACE;
23725baa35bSOleg Nesterov 	info->si_addr = (void __user *)regs->nip;
23825baa35bSOleg Nesterov }
23925baa35bSOleg Nesterov 
24014cf11afSPaul Mackerras void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
24114cf11afSPaul Mackerras {
24214cf11afSPaul Mackerras 	siginfo_t info;
243d0c3d534SOlof Johansson 	const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
244d0c3d534SOlof Johansson 			"at %08lx nip %08lx lr %08lx code %x\n";
245d0c3d534SOlof Johansson 	const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
246d0c3d534SOlof Johansson 			"at %016lx nip %016lx lr %016lx code %x\n";
24714cf11afSPaul Mackerras 
24814cf11afSPaul Mackerras 	if (!user_mode(regs)) {
249760ca4dcSAnton Blanchard 		die("Exception in kernel mode", regs, signr);
25014cf11afSPaul Mackerras 		return;
251760ca4dcSAnton Blanchard 	}
252760ca4dcSAnton Blanchard 
253760ca4dcSAnton Blanchard 	if (show_unhandled_signals && unhandled_signal(current, signr)) {
25476462232SChristian Dietrich 		printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
255d0c3d534SOlof Johansson 				   current->comm, current->pid, signr,
256d0c3d534SOlof Johansson 				   addr, regs->nip, regs->link, code);
25714cf11afSPaul Mackerras 	}
25814cf11afSPaul Mackerras 
259a3512b2dSBenjamin Herrenschmidt 	if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
2609f2f79e3SBenjamin Herrenschmidt 		local_irq_enable();
2619f2f79e3SBenjamin Herrenschmidt 
26241ab5266SAnanth N Mavinakayanahalli 	current->thread.trap_nr = code;
26314cf11afSPaul Mackerras 	memset(&info, 0, sizeof(info));
26414cf11afSPaul Mackerras 	info.si_signo = signr;
26514cf11afSPaul Mackerras 	info.si_code = code;
26614cf11afSPaul Mackerras 	info.si_addr = (void __user *) addr;
26714cf11afSPaul Mackerras 	force_sig_info(signr, &info, current);
26814cf11afSPaul Mackerras }
26914cf11afSPaul Mackerras 
27014cf11afSPaul Mackerras #ifdef CONFIG_PPC64
27114cf11afSPaul Mackerras void system_reset_exception(struct pt_regs *regs)
27214cf11afSPaul Mackerras {
27314cf11afSPaul Mackerras 	/* See if any machine dependent calls */
274c902be71SArnd Bergmann 	if (ppc_md.system_reset_exception) {
275c902be71SArnd Bergmann 		if (ppc_md.system_reset_exception(regs))
276c902be71SArnd Bergmann 			return;
277c902be71SArnd Bergmann 	}
27814cf11afSPaul Mackerras 
2798dad3f92SPaul Mackerras 	die("System Reset", regs, SIGABRT);
28014cf11afSPaul Mackerras 
28114cf11afSPaul Mackerras 	/* Must die if the interrupt is not recoverable */
28214cf11afSPaul Mackerras 	if (!(regs->msr & MSR_RI))
28314cf11afSPaul Mackerras 		panic("Unrecoverable System Reset");
28414cf11afSPaul Mackerras 
28514cf11afSPaul Mackerras 	/* What should we do here? We could issue a shutdown or hard reset. */
28614cf11afSPaul Mackerras }
2871e9b4507SMahesh Salgaonkar 
2881e9b4507SMahesh Salgaonkar /*
2891e9b4507SMahesh Salgaonkar  * This function is called in real mode. Strictly no printk's please.
2901e9b4507SMahesh Salgaonkar  *
2911e9b4507SMahesh Salgaonkar  * regs->nip and regs->msr contains srr0 and ssr1.
2921e9b4507SMahesh Salgaonkar  */
2931e9b4507SMahesh Salgaonkar long machine_check_early(struct pt_regs *regs)
2941e9b4507SMahesh Salgaonkar {
2954c703416SMahesh Salgaonkar 	long handled = 0;
2964c703416SMahesh Salgaonkar 
29769111bacSChristoph Lameter 	__this_cpu_inc(irq_stat.mce_exceptions);
298e6654d5bSMahesh Salgaonkar 
29927ea2c42SDaniel Axtens 	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
30027ea2c42SDaniel Axtens 
3014c703416SMahesh Salgaonkar 	if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
3024c703416SMahesh Salgaonkar 		handled = cur_cpu_spec->machine_check_early(regs);
3034c703416SMahesh Salgaonkar 	return handled;
3041e9b4507SMahesh Salgaonkar }
3051e9b4507SMahesh Salgaonkar 
3060869b6fdSMahesh Salgaonkar long hmi_exception_realmode(struct pt_regs *regs)
3070869b6fdSMahesh Salgaonkar {
30869111bacSChristoph Lameter 	__this_cpu_inc(irq_stat.hmi_exceptions);
3090869b6fdSMahesh Salgaonkar 
3100869b6fdSMahesh Salgaonkar 	if (ppc_md.hmi_exception_early)
3110869b6fdSMahesh Salgaonkar 		ppc_md.hmi_exception_early(regs);
3120869b6fdSMahesh Salgaonkar 
3130869b6fdSMahesh Salgaonkar 	return 0;
3140869b6fdSMahesh Salgaonkar }
3150869b6fdSMahesh Salgaonkar 
31614cf11afSPaul Mackerras #endif
31714cf11afSPaul Mackerras 
31814cf11afSPaul Mackerras /*
31914cf11afSPaul Mackerras  * I/O accesses can cause machine checks on powermacs.
32014cf11afSPaul Mackerras  * Check if the NIP corresponds to the address of a sync
32114cf11afSPaul Mackerras  * instruction for which there is an entry in the exception
32214cf11afSPaul Mackerras  * table.
32314cf11afSPaul Mackerras  * Note that the 601 only takes a machine check on TEA
32414cf11afSPaul Mackerras  * (transfer error ack) signal assertion, and does not
32514cf11afSPaul Mackerras  * set any of the top 16 bits of SRR1.
32614cf11afSPaul Mackerras  *  -- paulus.
32714cf11afSPaul Mackerras  */
32814cf11afSPaul Mackerras static inline int check_io_access(struct pt_regs *regs)
32914cf11afSPaul Mackerras {
33068a64357SBenjamin Herrenschmidt #ifdef CONFIG_PPC32
33114cf11afSPaul Mackerras 	unsigned long msr = regs->msr;
33214cf11afSPaul Mackerras 	const struct exception_table_entry *entry;
33314cf11afSPaul Mackerras 	unsigned int *nip = (unsigned int *)regs->nip;
33414cf11afSPaul Mackerras 
33514cf11afSPaul Mackerras 	if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
33614cf11afSPaul Mackerras 	    && (entry = search_exception_tables(regs->nip)) != NULL) {
33714cf11afSPaul Mackerras 		/*
33814cf11afSPaul Mackerras 		 * Check that it's a sync instruction, or somewhere
33914cf11afSPaul Mackerras 		 * in the twi; isync; nop sequence that inb/inw/inl uses.
34014cf11afSPaul Mackerras 		 * As the address is in the exception table
34114cf11afSPaul Mackerras 		 * we should be able to read the instr there.
34214cf11afSPaul Mackerras 		 * For the debug message, we look at the preceding
34314cf11afSPaul Mackerras 		 * load or store.
34414cf11afSPaul Mackerras 		 */
34514cf11afSPaul Mackerras 		if (*nip == 0x60000000)		/* nop */
34614cf11afSPaul Mackerras 			nip -= 2;
34714cf11afSPaul Mackerras 		else if (*nip == 0x4c00012c)	/* isync */
34814cf11afSPaul Mackerras 			--nip;
34914cf11afSPaul Mackerras 		if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
35014cf11afSPaul Mackerras 			/* sync or twi */
35114cf11afSPaul Mackerras 			unsigned int rb;
35214cf11afSPaul Mackerras 
35314cf11afSPaul Mackerras 			--nip;
35414cf11afSPaul Mackerras 			rb = (*nip >> 11) & 0x1f;
35514cf11afSPaul Mackerras 			printk(KERN_DEBUG "%s bad port %lx at %p\n",
35614cf11afSPaul Mackerras 			       (*nip & 0x100)? "OUT to": "IN from",
35714cf11afSPaul Mackerras 			       regs->gpr[rb] - _IO_BASE, nip);
35814cf11afSPaul Mackerras 			regs->msr |= MSR_RI;
35914cf11afSPaul Mackerras 			regs->nip = entry->fixup;
36014cf11afSPaul Mackerras 			return 1;
36114cf11afSPaul Mackerras 		}
36214cf11afSPaul Mackerras 	}
36368a64357SBenjamin Herrenschmidt #endif /* CONFIG_PPC32 */
36414cf11afSPaul Mackerras 	return 0;
36514cf11afSPaul Mackerras }
36614cf11afSPaul Mackerras 
367172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS
36814cf11afSPaul Mackerras /* On 4xx, the reason for the machine check or program exception
36914cf11afSPaul Mackerras    is in the ESR. */
37014cf11afSPaul Mackerras #define get_reason(regs)	((regs)->dsisr)
37114cf11afSPaul Mackerras #ifndef CONFIG_FSL_BOOKE
37214cf11afSPaul Mackerras #define get_mc_reason(regs)	((regs)->dsisr)
37314cf11afSPaul Mackerras #else
374fe04b112SScott Wood #define get_mc_reason(regs)	(mfspr(SPRN_MCSR))
37514cf11afSPaul Mackerras #endif
37614cf11afSPaul Mackerras #define REASON_FP		ESR_FP
37714cf11afSPaul Mackerras #define REASON_ILLEGAL		(ESR_PIL | ESR_PUO)
37814cf11afSPaul Mackerras #define REASON_PRIVILEGED	ESR_PPR
37914cf11afSPaul Mackerras #define REASON_TRAP		ESR_PTR
38014cf11afSPaul Mackerras 
38114cf11afSPaul Mackerras /* single-step stuff */
38251ae8d4aSBharat Bhushan #define single_stepping(regs)	(current->thread.debug.dbcr0 & DBCR0_IC)
38351ae8d4aSBharat Bhushan #define clear_single_step(regs)	(current->thread.debug.dbcr0 &= ~DBCR0_IC)
38414cf11afSPaul Mackerras 
38514cf11afSPaul Mackerras #else
38614cf11afSPaul Mackerras /* On non-4xx, the reason for the machine check or program
38714cf11afSPaul Mackerras    exception is in the MSR. */
38814cf11afSPaul Mackerras #define get_reason(regs)	((regs)->msr)
38914cf11afSPaul Mackerras #define get_mc_reason(regs)	((regs)->msr)
3908b3c34cfSMichael Neuling #define REASON_TM		0x200000
39114cf11afSPaul Mackerras #define REASON_FP		0x100000
39214cf11afSPaul Mackerras #define REASON_ILLEGAL		0x80000
39314cf11afSPaul Mackerras #define REASON_PRIVILEGED	0x40000
39414cf11afSPaul Mackerras #define REASON_TRAP		0x20000
39514cf11afSPaul Mackerras 
39614cf11afSPaul Mackerras #define single_stepping(regs)	((regs)->msr & MSR_SE)
39714cf11afSPaul Mackerras #define clear_single_step(regs)	((regs)->msr &= ~MSR_SE)
39814cf11afSPaul Mackerras #endif
39914cf11afSPaul Mackerras 
40047c0bd1aSBenjamin Herrenschmidt #if defined(CONFIG_4xx)
40147c0bd1aSBenjamin Herrenschmidt int machine_check_4xx(struct pt_regs *regs)
40214cf11afSPaul Mackerras {
4031a6a4ffeSKumar Gala 	unsigned long reason = get_mc_reason(regs);
40414cf11afSPaul Mackerras 
40514cf11afSPaul Mackerras 	if (reason & ESR_IMCP) {
40614cf11afSPaul Mackerras 		printk("Instruction");
40714cf11afSPaul Mackerras 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
40814cf11afSPaul Mackerras 	} else
40914cf11afSPaul Mackerras 		printk("Data");
41014cf11afSPaul Mackerras 	printk(" machine check in kernel mode.\n");
41147c0bd1aSBenjamin Herrenschmidt 
41247c0bd1aSBenjamin Herrenschmidt 	return 0;
41347c0bd1aSBenjamin Herrenschmidt }
41447c0bd1aSBenjamin Herrenschmidt 
41547c0bd1aSBenjamin Herrenschmidt int machine_check_440A(struct pt_regs *regs)
41647c0bd1aSBenjamin Herrenschmidt {
41747c0bd1aSBenjamin Herrenschmidt 	unsigned long reason = get_mc_reason(regs);
41847c0bd1aSBenjamin Herrenschmidt 
41914cf11afSPaul Mackerras 	printk("Machine check in kernel mode.\n");
42014cf11afSPaul Mackerras 	if (reason & ESR_IMCP){
42114cf11afSPaul Mackerras 		printk("Instruction Synchronous Machine Check exception\n");
42214cf11afSPaul Mackerras 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
42314cf11afSPaul Mackerras 	}
42414cf11afSPaul Mackerras 	else {
42514cf11afSPaul Mackerras 		u32 mcsr = mfspr(SPRN_MCSR);
42614cf11afSPaul Mackerras 		if (mcsr & MCSR_IB)
42714cf11afSPaul Mackerras 			printk("Instruction Read PLB Error\n");
42814cf11afSPaul Mackerras 		if (mcsr & MCSR_DRB)
42914cf11afSPaul Mackerras 			printk("Data Read PLB Error\n");
43014cf11afSPaul Mackerras 		if (mcsr & MCSR_DWB)
43114cf11afSPaul Mackerras 			printk("Data Write PLB Error\n");
43214cf11afSPaul Mackerras 		if (mcsr & MCSR_TLBP)
43314cf11afSPaul Mackerras 			printk("TLB Parity Error\n");
43414cf11afSPaul Mackerras 		if (mcsr & MCSR_ICP){
43514cf11afSPaul Mackerras 			flush_instruction_cache();
43614cf11afSPaul Mackerras 			printk("I-Cache Parity Error\n");
43714cf11afSPaul Mackerras 		}
43814cf11afSPaul Mackerras 		if (mcsr & MCSR_DCSP)
43914cf11afSPaul Mackerras 			printk("D-Cache Search Parity Error\n");
44014cf11afSPaul Mackerras 		if (mcsr & MCSR_DCFP)
44114cf11afSPaul Mackerras 			printk("D-Cache Flush Parity Error\n");
44214cf11afSPaul Mackerras 		if (mcsr & MCSR_IMPE)
44314cf11afSPaul Mackerras 			printk("Machine Check exception is imprecise\n");
44414cf11afSPaul Mackerras 
44514cf11afSPaul Mackerras 		/* Clear MCSR */
44614cf11afSPaul Mackerras 		mtspr(SPRN_MCSR, mcsr);
44714cf11afSPaul Mackerras 	}
44847c0bd1aSBenjamin Herrenschmidt 	return 0;
44947c0bd1aSBenjamin Herrenschmidt }
450fc5e7097SDave Kleikamp 
451fc5e7097SDave Kleikamp int machine_check_47x(struct pt_regs *regs)
452fc5e7097SDave Kleikamp {
453fc5e7097SDave Kleikamp 	unsigned long reason = get_mc_reason(regs);
454fc5e7097SDave Kleikamp 	u32 mcsr;
455fc5e7097SDave Kleikamp 
456fc5e7097SDave Kleikamp 	printk(KERN_ERR "Machine check in kernel mode.\n");
457fc5e7097SDave Kleikamp 	if (reason & ESR_IMCP) {
458fc5e7097SDave Kleikamp 		printk(KERN_ERR
459fc5e7097SDave Kleikamp 		       "Instruction Synchronous Machine Check exception\n");
460fc5e7097SDave Kleikamp 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
461fc5e7097SDave Kleikamp 		return 0;
462fc5e7097SDave Kleikamp 	}
463fc5e7097SDave Kleikamp 	mcsr = mfspr(SPRN_MCSR);
464fc5e7097SDave Kleikamp 	if (mcsr & MCSR_IB)
465fc5e7097SDave Kleikamp 		printk(KERN_ERR "Instruction Read PLB Error\n");
466fc5e7097SDave Kleikamp 	if (mcsr & MCSR_DRB)
467fc5e7097SDave Kleikamp 		printk(KERN_ERR "Data Read PLB Error\n");
468fc5e7097SDave Kleikamp 	if (mcsr & MCSR_DWB)
469fc5e7097SDave Kleikamp 		printk(KERN_ERR "Data Write PLB Error\n");
470fc5e7097SDave Kleikamp 	if (mcsr & MCSR_TLBP)
471fc5e7097SDave Kleikamp 		printk(KERN_ERR "TLB Parity Error\n");
472fc5e7097SDave Kleikamp 	if (mcsr & MCSR_ICP) {
473fc5e7097SDave Kleikamp 		flush_instruction_cache();
474fc5e7097SDave Kleikamp 		printk(KERN_ERR "I-Cache Parity Error\n");
475fc5e7097SDave Kleikamp 	}
476fc5e7097SDave Kleikamp 	if (mcsr & MCSR_DCSP)
477fc5e7097SDave Kleikamp 		printk(KERN_ERR "D-Cache Search Parity Error\n");
478fc5e7097SDave Kleikamp 	if (mcsr & PPC47x_MCSR_GPR)
479fc5e7097SDave Kleikamp 		printk(KERN_ERR "GPR Parity Error\n");
480fc5e7097SDave Kleikamp 	if (mcsr & PPC47x_MCSR_FPR)
481fc5e7097SDave Kleikamp 		printk(KERN_ERR "FPR Parity Error\n");
482fc5e7097SDave Kleikamp 	if (mcsr & PPC47x_MCSR_IPR)
483fc5e7097SDave Kleikamp 		printk(KERN_ERR "Machine Check exception is imprecise\n");
484fc5e7097SDave Kleikamp 
485fc5e7097SDave Kleikamp 	/* Clear MCSR */
486fc5e7097SDave Kleikamp 	mtspr(SPRN_MCSR, mcsr);
487fc5e7097SDave Kleikamp 
488fc5e7097SDave Kleikamp 	return 0;
489fc5e7097SDave Kleikamp }
49014cf11afSPaul Mackerras #elif defined(CONFIG_E500)
491fe04b112SScott Wood int machine_check_e500mc(struct pt_regs *regs)
492fe04b112SScott Wood {
493fe04b112SScott Wood 	unsigned long mcsr = mfspr(SPRN_MCSR);
494fe04b112SScott Wood 	unsigned long reason = mcsr;
495fe04b112SScott Wood 	int recoverable = 1;
496fe04b112SScott Wood 
49782a9a480SScott Wood 	if (reason & MCSR_LD) {
498cce1f106SShaohui Xie 		recoverable = fsl_rio_mcheck_exception(regs);
499cce1f106SShaohui Xie 		if (recoverable == 1)
500cce1f106SShaohui Xie 			goto silent_out;
501cce1f106SShaohui Xie 	}
502cce1f106SShaohui Xie 
503fe04b112SScott Wood 	printk("Machine check in kernel mode.\n");
504fe04b112SScott Wood 	printk("Caused by (from MCSR=%lx): ", reason);
505fe04b112SScott Wood 
506fe04b112SScott Wood 	if (reason & MCSR_MCP)
507fe04b112SScott Wood 		printk("Machine Check Signal\n");
508fe04b112SScott Wood 
509fe04b112SScott Wood 	if (reason & MCSR_ICPERR) {
510fe04b112SScott Wood 		printk("Instruction Cache Parity Error\n");
511fe04b112SScott Wood 
512fe04b112SScott Wood 		/*
513fe04b112SScott Wood 		 * This is recoverable by invalidating the i-cache.
514fe04b112SScott Wood 		 */
515fe04b112SScott Wood 		mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
516fe04b112SScott Wood 		while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
517fe04b112SScott Wood 			;
518fe04b112SScott Wood 
519fe04b112SScott Wood 		/*
520fe04b112SScott Wood 		 * This will generally be accompanied by an instruction
521fe04b112SScott Wood 		 * fetch error report -- only treat MCSR_IF as fatal
522fe04b112SScott Wood 		 * if it wasn't due to an L1 parity error.
523fe04b112SScott Wood 		 */
524fe04b112SScott Wood 		reason &= ~MCSR_IF;
525fe04b112SScott Wood 	}
526fe04b112SScott Wood 
527fe04b112SScott Wood 	if (reason & MCSR_DCPERR_MC) {
528fe04b112SScott Wood 		printk("Data Cache Parity Error\n");
52937caf9f2SKumar Gala 
53037caf9f2SKumar Gala 		/*
53137caf9f2SKumar Gala 		 * In write shadow mode we auto-recover from the error, but it
53237caf9f2SKumar Gala 		 * may still get logged and cause a machine check.  We should
53337caf9f2SKumar Gala 		 * only treat the non-write shadow case as non-recoverable.
53437caf9f2SKumar Gala 		 */
53537caf9f2SKumar Gala 		if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
536fe04b112SScott Wood 			recoverable = 0;
537fe04b112SScott Wood 	}
538fe04b112SScott Wood 
539fe04b112SScott Wood 	if (reason & MCSR_L2MMU_MHIT) {
540fe04b112SScott Wood 		printk("Hit on multiple TLB entries\n");
541fe04b112SScott Wood 		recoverable = 0;
542fe04b112SScott Wood 	}
543fe04b112SScott Wood 
544fe04b112SScott Wood 	if (reason & MCSR_NMI)
545fe04b112SScott Wood 		printk("Non-maskable interrupt\n");
546fe04b112SScott Wood 
547fe04b112SScott Wood 	if (reason & MCSR_IF) {
548fe04b112SScott Wood 		printk("Instruction Fetch Error Report\n");
549fe04b112SScott Wood 		recoverable = 0;
550fe04b112SScott Wood 	}
551fe04b112SScott Wood 
552fe04b112SScott Wood 	if (reason & MCSR_LD) {
553fe04b112SScott Wood 		printk("Load Error Report\n");
554fe04b112SScott Wood 		recoverable = 0;
555fe04b112SScott Wood 	}
556fe04b112SScott Wood 
557fe04b112SScott Wood 	if (reason & MCSR_ST) {
558fe04b112SScott Wood 		printk("Store Error Report\n");
559fe04b112SScott Wood 		recoverable = 0;
560fe04b112SScott Wood 	}
561fe04b112SScott Wood 
562fe04b112SScott Wood 	if (reason & MCSR_LDG) {
563fe04b112SScott Wood 		printk("Guarded Load Error Report\n");
564fe04b112SScott Wood 		recoverable = 0;
565fe04b112SScott Wood 	}
566fe04b112SScott Wood 
567fe04b112SScott Wood 	if (reason & MCSR_TLBSYNC)
568fe04b112SScott Wood 		printk("Simultaneous tlbsync operations\n");
569fe04b112SScott Wood 
570fe04b112SScott Wood 	if (reason & MCSR_BSL2_ERR) {
571fe04b112SScott Wood 		printk("Level 2 Cache Error\n");
572fe04b112SScott Wood 		recoverable = 0;
573fe04b112SScott Wood 	}
574fe04b112SScott Wood 
575fe04b112SScott Wood 	if (reason & MCSR_MAV) {
576fe04b112SScott Wood 		u64 addr;
577fe04b112SScott Wood 
578fe04b112SScott Wood 		addr = mfspr(SPRN_MCAR);
579fe04b112SScott Wood 		addr |= (u64)mfspr(SPRN_MCARU) << 32;
580fe04b112SScott Wood 
581fe04b112SScott Wood 		printk("Machine Check %s Address: %#llx\n",
582fe04b112SScott Wood 		       reason & MCSR_MEA ? "Effective" : "Physical", addr);
583fe04b112SScott Wood 	}
584fe04b112SScott Wood 
585cce1f106SShaohui Xie silent_out:
586fe04b112SScott Wood 	mtspr(SPRN_MCSR, mcsr);
587fe04b112SScott Wood 	return mfspr(SPRN_MCSR) == 0 && recoverable;
588fe04b112SScott Wood }
589fe04b112SScott Wood 
59047c0bd1aSBenjamin Herrenschmidt int machine_check_e500(struct pt_regs *regs)
59147c0bd1aSBenjamin Herrenschmidt {
59247c0bd1aSBenjamin Herrenschmidt 	unsigned long reason = get_mc_reason(regs);
59347c0bd1aSBenjamin Herrenschmidt 
594cce1f106SShaohui Xie 	if (reason & MCSR_BUS_RBERR) {
595cce1f106SShaohui Xie 		if (fsl_rio_mcheck_exception(regs))
596cce1f106SShaohui Xie 			return 1;
5974e0e3435SHongtao Jia 		if (fsl_pci_mcheck_exception(regs))
5984e0e3435SHongtao Jia 			return 1;
599cce1f106SShaohui Xie 	}
600cce1f106SShaohui Xie 
60114cf11afSPaul Mackerras 	printk("Machine check in kernel mode.\n");
60214cf11afSPaul Mackerras 	printk("Caused by (from MCSR=%lx): ", reason);
60314cf11afSPaul Mackerras 
60414cf11afSPaul Mackerras 	if (reason & MCSR_MCP)
60514cf11afSPaul Mackerras 		printk("Machine Check Signal\n");
60614cf11afSPaul Mackerras 	if (reason & MCSR_ICPERR)
60714cf11afSPaul Mackerras 		printk("Instruction Cache Parity Error\n");
60814cf11afSPaul Mackerras 	if (reason & MCSR_DCP_PERR)
60914cf11afSPaul Mackerras 		printk("Data Cache Push Parity Error\n");
61014cf11afSPaul Mackerras 	if (reason & MCSR_DCPERR)
61114cf11afSPaul Mackerras 		printk("Data Cache Parity Error\n");
61214cf11afSPaul Mackerras 	if (reason & MCSR_BUS_IAERR)
61314cf11afSPaul Mackerras 		printk("Bus - Instruction Address Error\n");
61414cf11afSPaul Mackerras 	if (reason & MCSR_BUS_RAERR)
61514cf11afSPaul Mackerras 		printk("Bus - Read Address Error\n");
61614cf11afSPaul Mackerras 	if (reason & MCSR_BUS_WAERR)
61714cf11afSPaul Mackerras 		printk("Bus - Write Address Error\n");
61814cf11afSPaul Mackerras 	if (reason & MCSR_BUS_IBERR)
61914cf11afSPaul Mackerras 		printk("Bus - Instruction Data Error\n");
62014cf11afSPaul Mackerras 	if (reason & MCSR_BUS_RBERR)
62114cf11afSPaul Mackerras 		printk("Bus - Read Data Bus Error\n");
62214cf11afSPaul Mackerras 	if (reason & MCSR_BUS_WBERR)
623c1528339SWladislav Wiebe 		printk("Bus - Write Data Bus Error\n");
62414cf11afSPaul Mackerras 	if (reason & MCSR_BUS_IPERR)
62514cf11afSPaul Mackerras 		printk("Bus - Instruction Parity Error\n");
62614cf11afSPaul Mackerras 	if (reason & MCSR_BUS_RPERR)
62714cf11afSPaul Mackerras 		printk("Bus - Read Parity Error\n");
62847c0bd1aSBenjamin Herrenschmidt 
62947c0bd1aSBenjamin Herrenschmidt 	return 0;
63047c0bd1aSBenjamin Herrenschmidt }
6314490c06bSKumar Gala 
6324490c06bSKumar Gala int machine_check_generic(struct pt_regs *regs)
6334490c06bSKumar Gala {
6344490c06bSKumar Gala 	return 0;
6354490c06bSKumar Gala }
63614cf11afSPaul Mackerras #elif defined(CONFIG_E200)
63747c0bd1aSBenjamin Herrenschmidt int machine_check_e200(struct pt_regs *regs)
63847c0bd1aSBenjamin Herrenschmidt {
63947c0bd1aSBenjamin Herrenschmidt 	unsigned long reason = get_mc_reason(regs);
64047c0bd1aSBenjamin Herrenschmidt 
64114cf11afSPaul Mackerras 	printk("Machine check in kernel mode.\n");
64214cf11afSPaul Mackerras 	printk("Caused by (from MCSR=%lx): ", reason);
64314cf11afSPaul Mackerras 
64414cf11afSPaul Mackerras 	if (reason & MCSR_MCP)
64514cf11afSPaul Mackerras 		printk("Machine Check Signal\n");
64614cf11afSPaul Mackerras 	if (reason & MCSR_CP_PERR)
64714cf11afSPaul Mackerras 		printk("Cache Push Parity Error\n");
64814cf11afSPaul Mackerras 	if (reason & MCSR_CPERR)
64914cf11afSPaul Mackerras 		printk("Cache Parity Error\n");
65014cf11afSPaul Mackerras 	if (reason & MCSR_EXCP_ERR)
65114cf11afSPaul Mackerras 		printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
65214cf11afSPaul Mackerras 	if (reason & MCSR_BUS_IRERR)
65314cf11afSPaul Mackerras 		printk("Bus - Read Bus Error on instruction fetch\n");
65414cf11afSPaul Mackerras 	if (reason & MCSR_BUS_DRERR)
65514cf11afSPaul Mackerras 		printk("Bus - Read Bus Error on data load\n");
65614cf11afSPaul Mackerras 	if (reason & MCSR_BUS_WRERR)
65714cf11afSPaul Mackerras 		printk("Bus - Write Bus Error on buffered store or cache line push\n");
65847c0bd1aSBenjamin Herrenschmidt 
65947c0bd1aSBenjamin Herrenschmidt 	return 0;
66047c0bd1aSBenjamin Herrenschmidt }
66147c0bd1aSBenjamin Herrenschmidt #else
66247c0bd1aSBenjamin Herrenschmidt int machine_check_generic(struct pt_regs *regs)
66347c0bd1aSBenjamin Herrenschmidt {
66447c0bd1aSBenjamin Herrenschmidt 	unsigned long reason = get_mc_reason(regs);
66547c0bd1aSBenjamin Herrenschmidt 
66614cf11afSPaul Mackerras 	printk("Machine check in kernel mode.\n");
66714cf11afSPaul Mackerras 	printk("Caused by (from SRR1=%lx): ", reason);
66814cf11afSPaul Mackerras 	switch (reason & 0x601F0000) {
66914cf11afSPaul Mackerras 	case 0x80000:
67014cf11afSPaul Mackerras 		printk("Machine check signal\n");
67114cf11afSPaul Mackerras 		break;
67214cf11afSPaul Mackerras 	case 0:		/* for 601 */
67314cf11afSPaul Mackerras 	case 0x40000:
67414cf11afSPaul Mackerras 	case 0x140000:	/* 7450 MSS error and TEA */
67514cf11afSPaul Mackerras 		printk("Transfer error ack signal\n");
67614cf11afSPaul Mackerras 		break;
67714cf11afSPaul Mackerras 	case 0x20000:
67814cf11afSPaul Mackerras 		printk("Data parity error signal\n");
67914cf11afSPaul Mackerras 		break;
68014cf11afSPaul Mackerras 	case 0x10000:
68114cf11afSPaul Mackerras 		printk("Address parity error signal\n");
68214cf11afSPaul Mackerras 		break;
68314cf11afSPaul Mackerras 	case 0x20000000:
68414cf11afSPaul Mackerras 		printk("L1 Data Cache error\n");
68514cf11afSPaul Mackerras 		break;
68614cf11afSPaul Mackerras 	case 0x40000000:
68714cf11afSPaul Mackerras 		printk("L1 Instruction Cache error\n");
68814cf11afSPaul Mackerras 		break;
68914cf11afSPaul Mackerras 	case 0x00100000:
69014cf11afSPaul Mackerras 		printk("L2 data cache parity error\n");
69114cf11afSPaul Mackerras 		break;
69214cf11afSPaul Mackerras 	default:
69314cf11afSPaul Mackerras 		printk("Unknown values in msr\n");
69414cf11afSPaul Mackerras 	}
69575918a4bSOlof Johansson 	return 0;
69675918a4bSOlof Johansson }
69747c0bd1aSBenjamin Herrenschmidt #endif /* everything else */
69875918a4bSOlof Johansson 
69975918a4bSOlof Johansson void machine_check_exception(struct pt_regs *regs)
70075918a4bSOlof Johansson {
701ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
70275918a4bSOlof Johansson 	int recover = 0;
70375918a4bSOlof Johansson 
70469111bacSChristoph Lameter 	__this_cpu_inc(irq_stat.mce_exceptions);
70589713ed1SAnton Blanchard 
70647c0bd1aSBenjamin Herrenschmidt 	/* See if any machine dependent calls. In theory, we would want
70747c0bd1aSBenjamin Herrenschmidt 	 * to call the CPU first, and call the ppc_md. one if the CPU
70847c0bd1aSBenjamin Herrenschmidt 	 * one returns a positive number. However there is existing code
70947c0bd1aSBenjamin Herrenschmidt 	 * that assumes the board gets a first chance, so let's keep it
71047c0bd1aSBenjamin Herrenschmidt 	 * that way for now and fix things later. --BenH.
71147c0bd1aSBenjamin Herrenschmidt 	 */
71275918a4bSOlof Johansson 	if (ppc_md.machine_check_exception)
71375918a4bSOlof Johansson 		recover = ppc_md.machine_check_exception(regs);
71447c0bd1aSBenjamin Herrenschmidt 	else if (cur_cpu_spec->machine_check)
71547c0bd1aSBenjamin Herrenschmidt 		recover = cur_cpu_spec->machine_check(regs);
71675918a4bSOlof Johansson 
71747c0bd1aSBenjamin Herrenschmidt 	if (recover > 0)
718ba12eedeSLi Zhong 		goto bail;
71975918a4bSOlof Johansson 
72075918a4bSOlof Johansson #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
72147c0bd1aSBenjamin Herrenschmidt 	/* the qspan pci read routines can cause machine checks -- Cort
72247c0bd1aSBenjamin Herrenschmidt 	 *
72347c0bd1aSBenjamin Herrenschmidt 	 * yuck !!! that totally needs to go away ! There are better ways
72447c0bd1aSBenjamin Herrenschmidt 	 * to deal with that than having a wart in the mcheck handler.
72547c0bd1aSBenjamin Herrenschmidt 	 * -- BenH
72647c0bd1aSBenjamin Herrenschmidt 	 */
72775918a4bSOlof Johansson 	bad_page_fault(regs, regs->dar, SIGBUS);
728ba12eedeSLi Zhong 	goto bail;
72975918a4bSOlof Johansson #endif
73075918a4bSOlof Johansson 
731a443506bSAnton Blanchard 	if (debugger_fault_handler(regs))
732ba12eedeSLi Zhong 		goto bail;
73375918a4bSOlof Johansson 
73475918a4bSOlof Johansson 	if (check_io_access(regs))
735ba12eedeSLi Zhong 		goto bail;
73675918a4bSOlof Johansson 
7378dad3f92SPaul Mackerras 	die("Machine check", regs, SIGBUS);
73814cf11afSPaul Mackerras 
73914cf11afSPaul Mackerras 	/* Must die if the interrupt is not recoverable */
74014cf11afSPaul Mackerras 	if (!(regs->msr & MSR_RI))
74114cf11afSPaul Mackerras 		panic("Unrecoverable Machine check");
742ba12eedeSLi Zhong 
743ba12eedeSLi Zhong bail:
744ba12eedeSLi Zhong 	exception_exit(prev_state);
74514cf11afSPaul Mackerras }
74614cf11afSPaul Mackerras 
74714cf11afSPaul Mackerras void SMIException(struct pt_regs *regs)
74814cf11afSPaul Mackerras {
74914cf11afSPaul Mackerras 	die("System Management Interrupt", regs, SIGABRT);
75014cf11afSPaul Mackerras }
75114cf11afSPaul Mackerras 
7520869b6fdSMahesh Salgaonkar void handle_hmi_exception(struct pt_regs *regs)
7530869b6fdSMahesh Salgaonkar {
7540869b6fdSMahesh Salgaonkar 	struct pt_regs *old_regs;
7550869b6fdSMahesh Salgaonkar 
7560869b6fdSMahesh Salgaonkar 	old_regs = set_irq_regs(regs);
7570869b6fdSMahesh Salgaonkar 	irq_enter();
7580869b6fdSMahesh Salgaonkar 
7590869b6fdSMahesh Salgaonkar 	if (ppc_md.handle_hmi_exception)
7600869b6fdSMahesh Salgaonkar 		ppc_md.handle_hmi_exception(regs);
7610869b6fdSMahesh Salgaonkar 
7620869b6fdSMahesh Salgaonkar 	irq_exit();
7630869b6fdSMahesh Salgaonkar 	set_irq_regs(old_regs);
7640869b6fdSMahesh Salgaonkar }
7650869b6fdSMahesh Salgaonkar 
766dc1c1ca3SStephen Rothwell void unknown_exception(struct pt_regs *regs)
76714cf11afSPaul Mackerras {
768ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
769ba12eedeSLi Zhong 
77014cf11afSPaul Mackerras 	printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
77114cf11afSPaul Mackerras 	       regs->nip, regs->msr, regs->trap);
77214cf11afSPaul Mackerras 
77314cf11afSPaul Mackerras 	_exception(SIGTRAP, regs, 0, 0);
774ba12eedeSLi Zhong 
775ba12eedeSLi Zhong 	exception_exit(prev_state);
77614cf11afSPaul Mackerras }
77714cf11afSPaul Mackerras 
778dc1c1ca3SStephen Rothwell void instruction_breakpoint_exception(struct pt_regs *regs)
77914cf11afSPaul Mackerras {
780ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
781ba12eedeSLi Zhong 
78214cf11afSPaul Mackerras 	if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
78314cf11afSPaul Mackerras 					5, SIGTRAP) == NOTIFY_STOP)
784ba12eedeSLi Zhong 		goto bail;
78514cf11afSPaul Mackerras 	if (debugger_iabr_match(regs))
786ba12eedeSLi Zhong 		goto bail;
78714cf11afSPaul Mackerras 	_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
788ba12eedeSLi Zhong 
789ba12eedeSLi Zhong bail:
790ba12eedeSLi Zhong 	exception_exit(prev_state);
79114cf11afSPaul Mackerras }
79214cf11afSPaul Mackerras 
79314cf11afSPaul Mackerras void RunModeException(struct pt_regs *regs)
79414cf11afSPaul Mackerras {
79514cf11afSPaul Mackerras 	_exception(SIGTRAP, regs, 0, 0);
79614cf11afSPaul Mackerras }
79714cf11afSPaul Mackerras 
7988dad3f92SPaul Mackerras void __kprobes single_step_exception(struct pt_regs *regs)
79914cf11afSPaul Mackerras {
800ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
801ba12eedeSLi Zhong 
8022538c2d0SK.Prasad 	clear_single_step(regs);
80314cf11afSPaul Mackerras 
80414cf11afSPaul Mackerras 	if (notify_die(DIE_SSTEP, "single_step", regs, 5,
80514cf11afSPaul Mackerras 					5, SIGTRAP) == NOTIFY_STOP)
806ba12eedeSLi Zhong 		goto bail;
80714cf11afSPaul Mackerras 	if (debugger_sstep(regs))
808ba12eedeSLi Zhong 		goto bail;
80914cf11afSPaul Mackerras 
81014cf11afSPaul Mackerras 	_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
811ba12eedeSLi Zhong 
812ba12eedeSLi Zhong bail:
813ba12eedeSLi Zhong 	exception_exit(prev_state);
81414cf11afSPaul Mackerras }
81514cf11afSPaul Mackerras 
81614cf11afSPaul Mackerras /*
81714cf11afSPaul Mackerras  * After we have successfully emulated an instruction, we have to
81814cf11afSPaul Mackerras  * check if the instruction was being single-stepped, and if so,
81914cf11afSPaul Mackerras  * pretend we got a single-step exception.  This was pointed out
82014cf11afSPaul Mackerras  * by Kumar Gala.  -- paulus
82114cf11afSPaul Mackerras  */
8228dad3f92SPaul Mackerras static void emulate_single_step(struct pt_regs *regs)
82314cf11afSPaul Mackerras {
8242538c2d0SK.Prasad 	if (single_stepping(regs))
8252538c2d0SK.Prasad 		single_step_exception(regs);
82614cf11afSPaul Mackerras }
82714cf11afSPaul Mackerras 
8285fad293bSKumar Gala static inline int __parse_fpscr(unsigned long fpscr)
829dc1c1ca3SStephen Rothwell {
8305fad293bSKumar Gala 	int ret = 0;
831dc1c1ca3SStephen Rothwell 
832dc1c1ca3SStephen Rothwell 	/* Invalid operation */
833dc1c1ca3SStephen Rothwell 	if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
8345fad293bSKumar Gala 		ret = FPE_FLTINV;
835dc1c1ca3SStephen Rothwell 
836dc1c1ca3SStephen Rothwell 	/* Overflow */
837dc1c1ca3SStephen Rothwell 	else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
8385fad293bSKumar Gala 		ret = FPE_FLTOVF;
839dc1c1ca3SStephen Rothwell 
840dc1c1ca3SStephen Rothwell 	/* Underflow */
841dc1c1ca3SStephen Rothwell 	else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
8425fad293bSKumar Gala 		ret = FPE_FLTUND;
843dc1c1ca3SStephen Rothwell 
844dc1c1ca3SStephen Rothwell 	/* Divide by zero */
845dc1c1ca3SStephen Rothwell 	else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
8465fad293bSKumar Gala 		ret = FPE_FLTDIV;
847dc1c1ca3SStephen Rothwell 
848dc1c1ca3SStephen Rothwell 	/* Inexact result */
849dc1c1ca3SStephen Rothwell 	else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
8505fad293bSKumar Gala 		ret = FPE_FLTRES;
8515fad293bSKumar Gala 
8525fad293bSKumar Gala 	return ret;
8535fad293bSKumar Gala }
8545fad293bSKumar Gala 
8555fad293bSKumar Gala static void parse_fpe(struct pt_regs *regs)
8565fad293bSKumar Gala {
8575fad293bSKumar Gala 	int code = 0;
8585fad293bSKumar Gala 
8595fad293bSKumar Gala 	flush_fp_to_thread(current);
8605fad293bSKumar Gala 
861de79f7b9SPaul Mackerras 	code = __parse_fpscr(current->thread.fp_state.fpscr);
862dc1c1ca3SStephen Rothwell 
863dc1c1ca3SStephen Rothwell 	_exception(SIGFPE, regs, code, regs->nip);
864dc1c1ca3SStephen Rothwell }
865dc1c1ca3SStephen Rothwell 
866dc1c1ca3SStephen Rothwell /*
867dc1c1ca3SStephen Rothwell  * Illegal instruction emulation support.  Originally written to
86814cf11afSPaul Mackerras  * provide the PVR to user applications using the mfspr rd, PVR.
86914cf11afSPaul Mackerras  * Return non-zero if we can't emulate, or -EFAULT if the associated
87014cf11afSPaul Mackerras  * memory access caused an access fault.  Return zero on success.
87114cf11afSPaul Mackerras  *
87214cf11afSPaul Mackerras  * There are a couple of ways to do this, either "decode" the instruction
87314cf11afSPaul Mackerras  * or directly match lots of bits.  In this case, matching lots of
87414cf11afSPaul Mackerras  * bits is faster and easier.
87586417780SPaul Mackerras  *
87614cf11afSPaul Mackerras  */
87714cf11afSPaul Mackerras static int emulate_string_inst(struct pt_regs *regs, u32 instword)
87814cf11afSPaul Mackerras {
87914cf11afSPaul Mackerras 	u8 rT = (instword >> 21) & 0x1f;
88014cf11afSPaul Mackerras 	u8 rA = (instword >> 16) & 0x1f;
88114cf11afSPaul Mackerras 	u8 NB_RB = (instword >> 11) & 0x1f;
88214cf11afSPaul Mackerras 	u32 num_bytes;
88314cf11afSPaul Mackerras 	unsigned long EA;
88414cf11afSPaul Mackerras 	int pos = 0;
88514cf11afSPaul Mackerras 
88614cf11afSPaul Mackerras 	/* Early out if we are an invalid form of lswx */
88716c57b36SKumar Gala 	if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
88814cf11afSPaul Mackerras 		if ((rT == rA) || (rT == NB_RB))
88914cf11afSPaul Mackerras 			return -EINVAL;
89014cf11afSPaul Mackerras 
89114cf11afSPaul Mackerras 	EA = (rA == 0) ? 0 : regs->gpr[rA];
89214cf11afSPaul Mackerras 
89316c57b36SKumar Gala 	switch (instword & PPC_INST_STRING_MASK) {
89416c57b36SKumar Gala 		case PPC_INST_LSWX:
89516c57b36SKumar Gala 		case PPC_INST_STSWX:
89614cf11afSPaul Mackerras 			EA += NB_RB;
89714cf11afSPaul Mackerras 			num_bytes = regs->xer & 0x7f;
89814cf11afSPaul Mackerras 			break;
89916c57b36SKumar Gala 		case PPC_INST_LSWI:
90016c57b36SKumar Gala 		case PPC_INST_STSWI:
90114cf11afSPaul Mackerras 			num_bytes = (NB_RB == 0) ? 32 : NB_RB;
90214cf11afSPaul Mackerras 			break;
90314cf11afSPaul Mackerras 		default:
90414cf11afSPaul Mackerras 			return -EINVAL;
90514cf11afSPaul Mackerras 	}
90614cf11afSPaul Mackerras 
90714cf11afSPaul Mackerras 	while (num_bytes != 0)
90814cf11afSPaul Mackerras 	{
90914cf11afSPaul Mackerras 		u8 val;
91014cf11afSPaul Mackerras 		u32 shift = 8 * (3 - (pos & 0x3));
91114cf11afSPaul Mackerras 
91280aa0fb4SJames Yang 		/* if process is 32-bit, clear upper 32 bits of EA */
91380aa0fb4SJames Yang 		if ((regs->msr & MSR_64BIT) == 0)
91480aa0fb4SJames Yang 			EA &= 0xFFFFFFFF;
91580aa0fb4SJames Yang 
91616c57b36SKumar Gala 		switch ((instword & PPC_INST_STRING_MASK)) {
91716c57b36SKumar Gala 			case PPC_INST_LSWX:
91816c57b36SKumar Gala 			case PPC_INST_LSWI:
91914cf11afSPaul Mackerras 				if (get_user(val, (u8 __user *)EA))
92014cf11afSPaul Mackerras 					return -EFAULT;
92114cf11afSPaul Mackerras 				/* first time updating this reg,
92214cf11afSPaul Mackerras 				 * zero it out */
92314cf11afSPaul Mackerras 				if (pos == 0)
92414cf11afSPaul Mackerras 					regs->gpr[rT] = 0;
92514cf11afSPaul Mackerras 				regs->gpr[rT] |= val << shift;
92614cf11afSPaul Mackerras 				break;
92716c57b36SKumar Gala 			case PPC_INST_STSWI:
92816c57b36SKumar Gala 			case PPC_INST_STSWX:
92914cf11afSPaul Mackerras 				val = regs->gpr[rT] >> shift;
93014cf11afSPaul Mackerras 				if (put_user(val, (u8 __user *)EA))
93114cf11afSPaul Mackerras 					return -EFAULT;
93214cf11afSPaul Mackerras 				break;
93314cf11afSPaul Mackerras 		}
93414cf11afSPaul Mackerras 		/* move EA to next address */
93514cf11afSPaul Mackerras 		EA += 1;
93614cf11afSPaul Mackerras 		num_bytes--;
93714cf11afSPaul Mackerras 
93814cf11afSPaul Mackerras 		/* manage our position within the register */
93914cf11afSPaul Mackerras 		if (++pos == 4) {
94014cf11afSPaul Mackerras 			pos = 0;
94114cf11afSPaul Mackerras 			if (++rT == 32)
94214cf11afSPaul Mackerras 				rT = 0;
94314cf11afSPaul Mackerras 		}
94414cf11afSPaul Mackerras 	}
94514cf11afSPaul Mackerras 
94614cf11afSPaul Mackerras 	return 0;
94714cf11afSPaul Mackerras }
94814cf11afSPaul Mackerras 
949c3412dcbSWill Schmidt static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
950c3412dcbSWill Schmidt {
951c3412dcbSWill Schmidt 	u32 ra,rs;
952c3412dcbSWill Schmidt 	unsigned long tmp;
953c3412dcbSWill Schmidt 
954c3412dcbSWill Schmidt 	ra = (instword >> 16) & 0x1f;
955c3412dcbSWill Schmidt 	rs = (instword >> 21) & 0x1f;
956c3412dcbSWill Schmidt 
957c3412dcbSWill Schmidt 	tmp = regs->gpr[rs];
958c3412dcbSWill Schmidt 	tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
959c3412dcbSWill Schmidt 	tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
960c3412dcbSWill Schmidt 	tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
961c3412dcbSWill Schmidt 	regs->gpr[ra] = tmp;
962c3412dcbSWill Schmidt 
963c3412dcbSWill Schmidt 	return 0;
964c3412dcbSWill Schmidt }
965c3412dcbSWill Schmidt 
966c1469f13SKumar Gala static int emulate_isel(struct pt_regs *regs, u32 instword)
967c1469f13SKumar Gala {
968c1469f13SKumar Gala 	u8 rT = (instword >> 21) & 0x1f;
969c1469f13SKumar Gala 	u8 rA = (instword >> 16) & 0x1f;
970c1469f13SKumar Gala 	u8 rB = (instword >> 11) & 0x1f;
971c1469f13SKumar Gala 	u8 BC = (instword >> 6) & 0x1f;
972c1469f13SKumar Gala 	u8 bit;
973c1469f13SKumar Gala 	unsigned long tmp;
974c1469f13SKumar Gala 
975c1469f13SKumar Gala 	tmp = (rA == 0) ? 0 : regs->gpr[rA];
976c1469f13SKumar Gala 	bit = (regs->ccr >> (31 - BC)) & 0x1;
977c1469f13SKumar Gala 
978c1469f13SKumar Gala 	regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
979c1469f13SKumar Gala 
980c1469f13SKumar Gala 	return 0;
981c1469f13SKumar Gala }
982c1469f13SKumar Gala 
9836ce6c629SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
9846ce6c629SMichael Neuling static inline bool tm_abort_check(struct pt_regs *regs, int cause)
9856ce6c629SMichael Neuling {
9866ce6c629SMichael Neuling         /* If we're emulating a load/store in an active transaction, we cannot
9876ce6c629SMichael Neuling          * emulate it as the kernel operates in transaction suspended context.
9886ce6c629SMichael Neuling          * We need to abort the transaction.  This creates a persistent TM
9896ce6c629SMichael Neuling          * abort so tell the user what caused it with a new code.
9906ce6c629SMichael Neuling 	 */
9916ce6c629SMichael Neuling 	if (MSR_TM_TRANSACTIONAL(regs->msr)) {
9926ce6c629SMichael Neuling 		tm_enable();
9936ce6c629SMichael Neuling 		tm_abort(cause);
9946ce6c629SMichael Neuling 		return true;
9956ce6c629SMichael Neuling 	}
9966ce6c629SMichael Neuling 	return false;
9976ce6c629SMichael Neuling }
9986ce6c629SMichael Neuling #else
9996ce6c629SMichael Neuling static inline bool tm_abort_check(struct pt_regs *regs, int reason)
10006ce6c629SMichael Neuling {
10016ce6c629SMichael Neuling 	return false;
10026ce6c629SMichael Neuling }
10036ce6c629SMichael Neuling #endif
10046ce6c629SMichael Neuling 
100514cf11afSPaul Mackerras static int emulate_instruction(struct pt_regs *regs)
100614cf11afSPaul Mackerras {
100714cf11afSPaul Mackerras 	u32 instword;
100814cf11afSPaul Mackerras 	u32 rd;
100914cf11afSPaul Mackerras 
10104288e343SAnton Blanchard 	if (!user_mode(regs))
101114cf11afSPaul Mackerras 		return -EINVAL;
101214cf11afSPaul Mackerras 	CHECK_FULL_REGS(regs);
101314cf11afSPaul Mackerras 
101414cf11afSPaul Mackerras 	if (get_user(instword, (u32 __user *)(regs->nip)))
101514cf11afSPaul Mackerras 		return -EFAULT;
101614cf11afSPaul Mackerras 
101714cf11afSPaul Mackerras 	/* Emulate the mfspr rD, PVR. */
101816c57b36SKumar Gala 	if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1019eecff81dSAnton Blanchard 		PPC_WARN_EMULATED(mfpvr, regs);
102014cf11afSPaul Mackerras 		rd = (instword >> 21) & 0x1f;
102114cf11afSPaul Mackerras 		regs->gpr[rd] = mfspr(SPRN_PVR);
102214cf11afSPaul Mackerras 		return 0;
102314cf11afSPaul Mackerras 	}
102414cf11afSPaul Mackerras 
102514cf11afSPaul Mackerras 	/* Emulating the dcba insn is just a no-op.  */
102680947e7cSGeert Uytterhoeven 	if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1027eecff81dSAnton Blanchard 		PPC_WARN_EMULATED(dcba, regs);
102814cf11afSPaul Mackerras 		return 0;
102980947e7cSGeert Uytterhoeven 	}
103014cf11afSPaul Mackerras 
103114cf11afSPaul Mackerras 	/* Emulate the mcrxr insn.  */
103216c57b36SKumar Gala 	if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
103386417780SPaul Mackerras 		int shift = (instword >> 21) & 0x1c;
103414cf11afSPaul Mackerras 		unsigned long msk = 0xf0000000UL >> shift;
103514cf11afSPaul Mackerras 
1036eecff81dSAnton Blanchard 		PPC_WARN_EMULATED(mcrxr, regs);
103714cf11afSPaul Mackerras 		regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
103814cf11afSPaul Mackerras 		regs->xer &= ~0xf0000000UL;
103914cf11afSPaul Mackerras 		return 0;
104014cf11afSPaul Mackerras 	}
104114cf11afSPaul Mackerras 
104214cf11afSPaul Mackerras 	/* Emulate load/store string insn. */
104380947e7cSGeert Uytterhoeven 	if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
10446ce6c629SMichael Neuling 		if (tm_abort_check(regs,
10456ce6c629SMichael Neuling 				   TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
10466ce6c629SMichael Neuling 			return -EINVAL;
1047eecff81dSAnton Blanchard 		PPC_WARN_EMULATED(string, regs);
104814cf11afSPaul Mackerras 		return emulate_string_inst(regs, instword);
104980947e7cSGeert Uytterhoeven 	}
105014cf11afSPaul Mackerras 
1051c3412dcbSWill Schmidt 	/* Emulate the popcntb (Population Count Bytes) instruction. */
105216c57b36SKumar Gala 	if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1053eecff81dSAnton Blanchard 		PPC_WARN_EMULATED(popcntb, regs);
1054c3412dcbSWill Schmidt 		return emulate_popcntb_inst(regs, instword);
1055c3412dcbSWill Schmidt 	}
1056c3412dcbSWill Schmidt 
1057c1469f13SKumar Gala 	/* Emulate isel (Integer Select) instruction */
105816c57b36SKumar Gala 	if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1059eecff81dSAnton Blanchard 		PPC_WARN_EMULATED(isel, regs);
1060c1469f13SKumar Gala 		return emulate_isel(regs, instword);
1061c1469f13SKumar Gala 	}
1062c1469f13SKumar Gala 
10639863c28aSJames Yang 	/* Emulate sync instruction variants */
10649863c28aSJames Yang 	if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
10659863c28aSJames Yang 		PPC_WARN_EMULATED(sync, regs);
10669863c28aSJames Yang 		asm volatile("sync");
10679863c28aSJames Yang 		return 0;
10689863c28aSJames Yang 	}
10699863c28aSJames Yang 
1070efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64
1071efcac658SAlexey Kardashevskiy 	/* Emulate the mfspr rD, DSCR. */
107273d2fb75SAnton Blanchard 	if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
107373d2fb75SAnton Blanchard 		PPC_INST_MFSPR_DSCR_USER) ||
107473d2fb75SAnton Blanchard 	     ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
107573d2fb75SAnton Blanchard 		PPC_INST_MFSPR_DSCR)) &&
1076efcac658SAlexey Kardashevskiy 			cpu_has_feature(CPU_FTR_DSCR)) {
1077efcac658SAlexey Kardashevskiy 		PPC_WARN_EMULATED(mfdscr, regs);
1078efcac658SAlexey Kardashevskiy 		rd = (instword >> 21) & 0x1f;
1079efcac658SAlexey Kardashevskiy 		regs->gpr[rd] = mfspr(SPRN_DSCR);
1080efcac658SAlexey Kardashevskiy 		return 0;
1081efcac658SAlexey Kardashevskiy 	}
1082efcac658SAlexey Kardashevskiy 	/* Emulate the mtspr DSCR, rD. */
108373d2fb75SAnton Blanchard 	if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
108473d2fb75SAnton Blanchard 		PPC_INST_MTSPR_DSCR_USER) ||
108573d2fb75SAnton Blanchard 	     ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
108673d2fb75SAnton Blanchard 		PPC_INST_MTSPR_DSCR)) &&
1087efcac658SAlexey Kardashevskiy 			cpu_has_feature(CPU_FTR_DSCR)) {
1088efcac658SAlexey Kardashevskiy 		PPC_WARN_EMULATED(mtdscr, regs);
1089efcac658SAlexey Kardashevskiy 		rd = (instword >> 21) & 0x1f;
109000ca0de0SAnton Blanchard 		current->thread.dscr = regs->gpr[rd];
1091efcac658SAlexey Kardashevskiy 		current->thread.dscr_inherit = 1;
109200ca0de0SAnton Blanchard 		mtspr(SPRN_DSCR, current->thread.dscr);
1093efcac658SAlexey Kardashevskiy 		return 0;
1094efcac658SAlexey Kardashevskiy 	}
1095efcac658SAlexey Kardashevskiy #endif
1096efcac658SAlexey Kardashevskiy 
109714cf11afSPaul Mackerras 	return -EINVAL;
109814cf11afSPaul Mackerras }
109914cf11afSPaul Mackerras 
110073c9ceabSJeremy Fitzhardinge int is_valid_bugaddr(unsigned long addr)
110114cf11afSPaul Mackerras {
110273c9ceabSJeremy Fitzhardinge 	return is_kernel_addr(addr);
110314cf11afSPaul Mackerras }
110414cf11afSPaul Mackerras 
11053a3b5aa6SKevin Hao #ifdef CONFIG_MATH_EMULATION
11063a3b5aa6SKevin Hao static int emulate_math(struct pt_regs *regs)
11073a3b5aa6SKevin Hao {
11083a3b5aa6SKevin Hao 	int ret;
11093a3b5aa6SKevin Hao 	extern int do_mathemu(struct pt_regs *regs);
11103a3b5aa6SKevin Hao 
11113a3b5aa6SKevin Hao 	ret = do_mathemu(regs);
11123a3b5aa6SKevin Hao 	if (ret >= 0)
11133a3b5aa6SKevin Hao 		PPC_WARN_EMULATED(math, regs);
11143a3b5aa6SKevin Hao 
11153a3b5aa6SKevin Hao 	switch (ret) {
11163a3b5aa6SKevin Hao 	case 0:
11173a3b5aa6SKevin Hao 		emulate_single_step(regs);
11183a3b5aa6SKevin Hao 		return 0;
11193a3b5aa6SKevin Hao 	case 1: {
11203a3b5aa6SKevin Hao 			int code = 0;
1121de79f7b9SPaul Mackerras 			code = __parse_fpscr(current->thread.fp_state.fpscr);
11223a3b5aa6SKevin Hao 			_exception(SIGFPE, regs, code, regs->nip);
11233a3b5aa6SKevin Hao 			return 0;
11243a3b5aa6SKevin Hao 		}
11253a3b5aa6SKevin Hao 	case -EFAULT:
11263a3b5aa6SKevin Hao 		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
11273a3b5aa6SKevin Hao 		return 0;
11283a3b5aa6SKevin Hao 	}
11293a3b5aa6SKevin Hao 
11303a3b5aa6SKevin Hao 	return -1;
11313a3b5aa6SKevin Hao }
11323a3b5aa6SKevin Hao #else
11333a3b5aa6SKevin Hao static inline int emulate_math(struct pt_regs *regs) { return -1; }
11343a3b5aa6SKevin Hao #endif
11353a3b5aa6SKevin Hao 
11368dad3f92SPaul Mackerras void __kprobes program_check_exception(struct pt_regs *regs)
113714cf11afSPaul Mackerras {
1138ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
113914cf11afSPaul Mackerras 	unsigned int reason = get_reason(regs);
114014cf11afSPaul Mackerras 
1141aa42c69cSKim Phillips 	/* We can now get here via a FP Unavailable exception if the core
114204903a30SKumar Gala 	 * has no FPU, in that case the reason flags will be 0 */
114314cf11afSPaul Mackerras 
114414cf11afSPaul Mackerras 	if (reason & REASON_FP) {
114514cf11afSPaul Mackerras 		/* IEEE FP exception */
1146dc1c1ca3SStephen Rothwell 		parse_fpe(regs);
1147ba12eedeSLi Zhong 		goto bail;
11488dad3f92SPaul Mackerras 	}
11498dad3f92SPaul Mackerras 	if (reason & REASON_TRAP) {
1150ba797b28SJason Wessel 		/* Debugger is first in line to stop recursive faults in
1151ba797b28SJason Wessel 		 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1152ba797b28SJason Wessel 		if (debugger_bpt(regs))
1153ba12eedeSLi Zhong 			goto bail;
1154ba797b28SJason Wessel 
115514cf11afSPaul Mackerras 		/* trap exception */
1156dc1c1ca3SStephen Rothwell 		if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1157dc1c1ca3SStephen Rothwell 				== NOTIFY_STOP)
1158ba12eedeSLi Zhong 			goto bail;
115973c9ceabSJeremy Fitzhardinge 
116073c9ceabSJeremy Fitzhardinge 		if (!(regs->msr & MSR_PR) &&  /* not user-mode */
1161608e2619SHeiko Carstens 		    report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
116214cf11afSPaul Mackerras 			regs->nip += 4;
1163ba12eedeSLi Zhong 			goto bail;
116414cf11afSPaul Mackerras 		}
11658dad3f92SPaul Mackerras 		_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1166ba12eedeSLi Zhong 		goto bail;
11678dad3f92SPaul Mackerras 	}
1168bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1169bc2a9408SMichael Neuling 	if (reason & REASON_TM) {
1170bc2a9408SMichael Neuling 		/* This is a TM "Bad Thing Exception" program check.
1171bc2a9408SMichael Neuling 		 * This occurs when:
1172bc2a9408SMichael Neuling 		 * -  An rfid/hrfid/mtmsrd attempts to cause an illegal
1173bc2a9408SMichael Neuling 		 *    transition in TM states.
1174bc2a9408SMichael Neuling 		 * -  A trechkpt is attempted when transactional.
1175bc2a9408SMichael Neuling 		 * -  A treclaim is attempted when non transactional.
1176bc2a9408SMichael Neuling 		 * -  A tend is illegally attempted.
1177bc2a9408SMichael Neuling 		 * -  writing a TM SPR when transactional.
1178bc2a9408SMichael Neuling 		 */
1179bc2a9408SMichael Neuling 		if (!user_mode(regs) &&
1180bc2a9408SMichael Neuling 		    report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1181bc2a9408SMichael Neuling 			regs->nip += 4;
1182ba12eedeSLi Zhong 			goto bail;
1183bc2a9408SMichael Neuling 		}
1184bc2a9408SMichael Neuling 		/* If usermode caused this, it's done something illegal and
1185bc2a9408SMichael Neuling 		 * gets a SIGILL slap on the wrist.  We call it an illegal
1186bc2a9408SMichael Neuling 		 * operand to distinguish from the instruction just being bad
1187bc2a9408SMichael Neuling 		 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1188bc2a9408SMichael Neuling 		 * illegal /placement/ of a valid instruction.
1189bc2a9408SMichael Neuling 		 */
1190bc2a9408SMichael Neuling 		if (user_mode(regs)) {
1191bc2a9408SMichael Neuling 			_exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1192ba12eedeSLi Zhong 			goto bail;
1193bc2a9408SMichael Neuling 		} else {
1194bc2a9408SMichael Neuling 			printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1195bc2a9408SMichael Neuling 			       "at %lx (msr 0x%x)\n", regs->nip, reason);
1196bc2a9408SMichael Neuling 			die("Unrecoverable exception", regs, SIGABRT);
1197bc2a9408SMichael Neuling 		}
1198bc2a9408SMichael Neuling 	}
1199bc2a9408SMichael Neuling #endif
12008dad3f92SPaul Mackerras 
1201b3f6a459SMichael Ellerman 	/*
1202b3f6a459SMichael Ellerman 	 * If we took the program check in the kernel skip down to sending a
1203b3f6a459SMichael Ellerman 	 * SIGILL. The subsequent cases all relate to emulating instructions
1204b3f6a459SMichael Ellerman 	 * which we should only do for userspace. We also do not want to enable
1205b3f6a459SMichael Ellerman 	 * interrupts for kernel faults because that might lead to further
1206b3f6a459SMichael Ellerman 	 * faults, and loose the context of the original exception.
1207b3f6a459SMichael Ellerman 	 */
1208b3f6a459SMichael Ellerman 	if (!user_mode(regs))
1209b3f6a459SMichael Ellerman 		goto sigill;
1210b3f6a459SMichael Ellerman 
1211a3512b2dSBenjamin Herrenschmidt 	/* We restore the interrupt state now */
1212a3512b2dSBenjamin Herrenschmidt 	if (!arch_irq_disabled_regs(regs))
1213cd8a5673SPaul Mackerras 		local_irq_enable();
1214cd8a5673SPaul Mackerras 
121504903a30SKumar Gala 	/* (reason & REASON_ILLEGAL) would be the obvious thing here,
121604903a30SKumar Gala 	 * but there seems to be a hardware bug on the 405GP (RevD)
121704903a30SKumar Gala 	 * that means ESR is sometimes set incorrectly - either to
121804903a30SKumar Gala 	 * ESR_DST (!?) or 0.  In the process of chasing this with the
121904903a30SKumar Gala 	 * hardware people - not sure if it can happen on any illegal
122004903a30SKumar Gala 	 * instruction or only on FP instructions, whether there is a
12214e63f8edSBenjamin Herrenschmidt 	 * pattern to occurrences etc. -dgibson 31/Mar/2003
12224e63f8edSBenjamin Herrenschmidt 	 */
12233a3b5aa6SKevin Hao 	if (!emulate_math(regs))
1224ba12eedeSLi Zhong 		goto bail;
122504903a30SKumar Gala 
12268dad3f92SPaul Mackerras 	/* Try to emulate it if we should. */
12278dad3f92SPaul Mackerras 	if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
122814cf11afSPaul Mackerras 		switch (emulate_instruction(regs)) {
122914cf11afSPaul Mackerras 		case 0:
123014cf11afSPaul Mackerras 			regs->nip += 4;
123114cf11afSPaul Mackerras 			emulate_single_step(regs);
1232ba12eedeSLi Zhong 			goto bail;
123314cf11afSPaul Mackerras 		case -EFAULT:
123414cf11afSPaul Mackerras 			_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1235ba12eedeSLi Zhong 			goto bail;
12368dad3f92SPaul Mackerras 		}
12378dad3f92SPaul Mackerras 	}
12388dad3f92SPaul Mackerras 
1239b3f6a459SMichael Ellerman sigill:
124014cf11afSPaul Mackerras 	if (reason & REASON_PRIVILEGED)
124114cf11afSPaul Mackerras 		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
124214cf11afSPaul Mackerras 	else
124314cf11afSPaul Mackerras 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1244ba12eedeSLi Zhong 
1245ba12eedeSLi Zhong bail:
1246ba12eedeSLi Zhong 	exception_exit(prev_state);
124714cf11afSPaul Mackerras }
124814cf11afSPaul Mackerras 
1249bf593907SPaul Mackerras /*
1250bf593907SPaul Mackerras  * This occurs when running in hypervisor mode on POWER6 or later
1251bf593907SPaul Mackerras  * and an illegal instruction is encountered.
1252bf593907SPaul Mackerras  */
1253bf593907SPaul Mackerras void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
1254bf593907SPaul Mackerras {
1255bf593907SPaul Mackerras 	regs->msr |= REASON_ILLEGAL;
1256bf593907SPaul Mackerras 	program_check_exception(regs);
1257bf593907SPaul Mackerras }
1258bf593907SPaul Mackerras 
1259dc1c1ca3SStephen Rothwell void alignment_exception(struct pt_regs *regs)
126014cf11afSPaul Mackerras {
1261ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
12624393c4f6SBenjamin Herrenschmidt 	int sig, code, fixed = 0;
126314cf11afSPaul Mackerras 
1264a3512b2dSBenjamin Herrenschmidt 	/* We restore the interrupt state now */
1265a3512b2dSBenjamin Herrenschmidt 	if (!arch_irq_disabled_regs(regs))
1266a3512b2dSBenjamin Herrenschmidt 		local_irq_enable();
1267a3512b2dSBenjamin Herrenschmidt 
12686ce6c629SMichael Neuling 	if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
12696ce6c629SMichael Neuling 		goto bail;
12706ce6c629SMichael Neuling 
1271e9370ae1SPaul Mackerras 	/* we don't implement logging of alignment exceptions */
1272e9370ae1SPaul Mackerras 	if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
127314cf11afSPaul Mackerras 		fixed = fix_alignment(regs);
127414cf11afSPaul Mackerras 
127514cf11afSPaul Mackerras 	if (fixed == 1) {
127614cf11afSPaul Mackerras 		regs->nip += 4;	/* skip over emulated instruction */
127714cf11afSPaul Mackerras 		emulate_single_step(regs);
1278ba12eedeSLi Zhong 		goto bail;
127914cf11afSPaul Mackerras 	}
128014cf11afSPaul Mackerras 
128114cf11afSPaul Mackerras 	/* Operand address was bad */
128214cf11afSPaul Mackerras 	if (fixed == -EFAULT) {
12834393c4f6SBenjamin Herrenschmidt 		sig = SIGSEGV;
12844393c4f6SBenjamin Herrenschmidt 		code = SEGV_ACCERR;
12854393c4f6SBenjamin Herrenschmidt 	} else {
12864393c4f6SBenjamin Herrenschmidt 		sig = SIGBUS;
12874393c4f6SBenjamin Herrenschmidt 		code = BUS_ADRALN;
128814cf11afSPaul Mackerras 	}
12894393c4f6SBenjamin Herrenschmidt 	if (user_mode(regs))
12904393c4f6SBenjamin Herrenschmidt 		_exception(sig, regs, code, regs->dar);
12914393c4f6SBenjamin Herrenschmidt 	else
12924393c4f6SBenjamin Herrenschmidt 		bad_page_fault(regs, regs->dar, sig);
1293ba12eedeSLi Zhong 
1294ba12eedeSLi Zhong bail:
1295ba12eedeSLi Zhong 	exception_exit(prev_state);
129614cf11afSPaul Mackerras }
129714cf11afSPaul Mackerras 
129814cf11afSPaul Mackerras void StackOverflow(struct pt_regs *regs)
129914cf11afSPaul Mackerras {
130014cf11afSPaul Mackerras 	printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
130114cf11afSPaul Mackerras 	       current, regs->gpr[1]);
130214cf11afSPaul Mackerras 	debugger(regs);
130314cf11afSPaul Mackerras 	show_regs(regs);
130414cf11afSPaul Mackerras 	panic("kernel stack overflow");
130514cf11afSPaul Mackerras }
130614cf11afSPaul Mackerras 
130714cf11afSPaul Mackerras void nonrecoverable_exception(struct pt_regs *regs)
130814cf11afSPaul Mackerras {
130914cf11afSPaul Mackerras 	printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
131014cf11afSPaul Mackerras 	       regs->nip, regs->msr);
131114cf11afSPaul Mackerras 	debugger(regs);
131214cf11afSPaul Mackerras 	die("nonrecoverable exception", regs, SIGKILL);
131314cf11afSPaul Mackerras }
131414cf11afSPaul Mackerras 
1315dc1c1ca3SStephen Rothwell void kernel_fp_unavailable_exception(struct pt_regs *regs)
1316dc1c1ca3SStephen Rothwell {
1317ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
1318ba12eedeSLi Zhong 
1319dc1c1ca3SStephen Rothwell 	printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1320dc1c1ca3SStephen Rothwell 			  "%lx at %lx\n", regs->trap, regs->nip);
1321dc1c1ca3SStephen Rothwell 	die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1322ba12eedeSLi Zhong 
1323ba12eedeSLi Zhong 	exception_exit(prev_state);
1324dc1c1ca3SStephen Rothwell }
1325dc1c1ca3SStephen Rothwell 
1326dc1c1ca3SStephen Rothwell void altivec_unavailable_exception(struct pt_regs *regs)
1327dc1c1ca3SStephen Rothwell {
1328ba12eedeSLi Zhong 	enum ctx_state prev_state = exception_enter();
1329ba12eedeSLi Zhong 
1330dc1c1ca3SStephen Rothwell 	if (user_mode(regs)) {
1331dc1c1ca3SStephen Rothwell 		/* A user program has executed an altivec instruction,
1332dc1c1ca3SStephen Rothwell 		   but this kernel doesn't support altivec. */
1333dc1c1ca3SStephen Rothwell 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1334ba12eedeSLi Zhong 		goto bail;
1335dc1c1ca3SStephen Rothwell 	}
13366c4841c2SAnton Blanchard 
1337dc1c1ca3SStephen Rothwell 	printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1338dc1c1ca3SStephen Rothwell 			"%lx at %lx\n", regs->trap, regs->nip);
1339dc1c1ca3SStephen Rothwell 	die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1340ba12eedeSLi Zhong 
1341ba12eedeSLi Zhong bail:
1342ba12eedeSLi Zhong 	exception_exit(prev_state);
1343dc1c1ca3SStephen Rothwell }
1344dc1c1ca3SStephen Rothwell 
1345ce48b210SMichael Neuling void vsx_unavailable_exception(struct pt_regs *regs)
1346ce48b210SMichael Neuling {
1347ce48b210SMichael Neuling 	if (user_mode(regs)) {
1348ce48b210SMichael Neuling 		/* A user program has executed an vsx instruction,
1349ce48b210SMichael Neuling 		   but this kernel doesn't support vsx. */
1350ce48b210SMichael Neuling 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1351ce48b210SMichael Neuling 		return;
1352ce48b210SMichael Neuling 	}
1353ce48b210SMichael Neuling 
1354ce48b210SMichael Neuling 	printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1355ce48b210SMichael Neuling 			"%lx at %lx\n", regs->trap, regs->nip);
1356ce48b210SMichael Neuling 	die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1357ce48b210SMichael Neuling }
1358ce48b210SMichael Neuling 
13592517617eSMichael Neuling #ifdef CONFIG_PPC64
1360021424a1SMichael Ellerman void facility_unavailable_exception(struct pt_regs *regs)
1361d0c0c9a1SMichael Neuling {
1362021424a1SMichael Ellerman 	static char *facility_strings[] = {
13632517617eSMichael Neuling 		[FSCR_FP_LG] = "FPU",
13642517617eSMichael Neuling 		[FSCR_VECVSX_LG] = "VMX/VSX",
13652517617eSMichael Neuling 		[FSCR_DSCR_LG] = "DSCR",
13662517617eSMichael Neuling 		[FSCR_PM_LG] = "PMU SPRs",
13672517617eSMichael Neuling 		[FSCR_BHRB_LG] = "BHRB",
13682517617eSMichael Neuling 		[FSCR_TM_LG] = "TM",
13692517617eSMichael Neuling 		[FSCR_EBB_LG] = "EBB",
13702517617eSMichael Neuling 		[FSCR_TAR_LG] = "TAR",
1371021424a1SMichael Ellerman 	};
13722517617eSMichael Neuling 	char *facility = "unknown";
1373021424a1SMichael Ellerman 	u64 value;
1374c952c1c4SAnshuman Khandual 	u32 instword, rd;
13752517617eSMichael Neuling 	u8 status;
13762517617eSMichael Neuling 	bool hv;
1377021424a1SMichael Ellerman 
13782517617eSMichael Neuling 	hv = (regs->trap == 0xf80);
13792517617eSMichael Neuling 	if (hv)
1380b14b6260SMichael Ellerman 		value = mfspr(SPRN_HFSCR);
13812517617eSMichael Neuling 	else
13822517617eSMichael Neuling 		value = mfspr(SPRN_FSCR);
13832517617eSMichael Neuling 
13842517617eSMichael Neuling 	status = value >> 56;
13852517617eSMichael Neuling 	if (status == FSCR_DSCR_LG) {
1386c952c1c4SAnshuman Khandual 		/*
1387c952c1c4SAnshuman Khandual 		 * User is accessing the DSCR register using the problem
1388c952c1c4SAnshuman Khandual 		 * state only SPR number (0x03) either through a mfspr or
1389c952c1c4SAnshuman Khandual 		 * a mtspr instruction. If it is a write attempt through
1390c952c1c4SAnshuman Khandual 		 * a mtspr, then we set the inherit bit. This also allows
1391c952c1c4SAnshuman Khandual 		 * the user to write or read the register directly in the
1392c952c1c4SAnshuman Khandual 		 * future by setting via the FSCR DSCR bit. But in case it
1393c952c1c4SAnshuman Khandual 		 * is a read DSCR attempt through a mfspr instruction, we
1394c952c1c4SAnshuman Khandual 		 * just emulate the instruction instead. This code path will
1395c952c1c4SAnshuman Khandual 		 * always emulate all the mfspr instructions till the user
1396c952c1c4SAnshuman Khandual 		 * has attempted atleast one mtspr instruction. This way it
1397c952c1c4SAnshuman Khandual 		 * preserves the same behaviour when the user is accessing
1398c952c1c4SAnshuman Khandual 		 * the DSCR through privilege level only SPR number (0x11)
1399c952c1c4SAnshuman Khandual 		 * which is emulated through illegal instruction exception.
1400c952c1c4SAnshuman Khandual 		 * We always leave HFSCR DSCR set.
14012517617eSMichael Neuling 		 */
1402c952c1c4SAnshuman Khandual 		if (get_user(instword, (u32 __user *)(regs->nip))) {
1403c952c1c4SAnshuman Khandual 			pr_err("Failed to fetch the user instruction\n");
1404c952c1c4SAnshuman Khandual 			return;
1405c952c1c4SAnshuman Khandual 		}
1406c952c1c4SAnshuman Khandual 
1407c952c1c4SAnshuman Khandual 		/* Write into DSCR (mtspr 0x03, RS) */
1408c952c1c4SAnshuman Khandual 		if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1409c952c1c4SAnshuman Khandual 				== PPC_INST_MTSPR_DSCR_USER) {
1410c952c1c4SAnshuman Khandual 			rd = (instword >> 21) & 0x1f;
1411c952c1c4SAnshuman Khandual 			current->thread.dscr = regs->gpr[rd];
14122517617eSMichael Neuling 			current->thread.dscr_inherit = 1;
14132517617eSMichael Neuling 			mtspr(SPRN_FSCR, value | FSCR_DSCR);
1414c952c1c4SAnshuman Khandual 		}
1415c952c1c4SAnshuman Khandual 
1416c952c1c4SAnshuman Khandual 		/* Read from DSCR (mfspr RT, 0x03) */
1417c952c1c4SAnshuman Khandual 		if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1418c952c1c4SAnshuman Khandual 				== PPC_INST_MFSPR_DSCR_USER) {
1419c952c1c4SAnshuman Khandual 			if (emulate_instruction(regs)) {
1420c952c1c4SAnshuman Khandual 				pr_err("DSCR based mfspr emulation failed\n");
1421c952c1c4SAnshuman Khandual 				return;
1422c952c1c4SAnshuman Khandual 			}
1423c952c1c4SAnshuman Khandual 			regs->nip += 4;
1424c952c1c4SAnshuman Khandual 			emulate_single_step(regs);
1425c952c1c4SAnshuman Khandual 		}
14262517617eSMichael Neuling 		return;
1427b14b6260SMichael Ellerman 	}
1428b14b6260SMichael Ellerman 
14292517617eSMichael Neuling 	if ((status < ARRAY_SIZE(facility_strings)) &&
14302517617eSMichael Neuling 	    facility_strings[status])
14312517617eSMichael Neuling 		facility = facility_strings[status];
1432021424a1SMichael Ellerman 
1433d0c0c9a1SMichael Neuling 	/* We restore the interrupt state now */
1434d0c0c9a1SMichael Neuling 	if (!arch_irq_disabled_regs(regs))
1435d0c0c9a1SMichael Neuling 		local_irq_enable();
1436d0c0c9a1SMichael Neuling 
1437ee4ed6faSMichael Neuling 	pr_err_ratelimited(
1438ee4ed6faSMichael Neuling 		"%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
14392517617eSMichael Neuling 		hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
1440d0c0c9a1SMichael Neuling 
1441d0c0c9a1SMichael Neuling 	if (user_mode(regs)) {
1442d0c0c9a1SMichael Neuling 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1443d0c0c9a1SMichael Neuling 		return;
1444d0c0c9a1SMichael Neuling 	}
1445d0c0c9a1SMichael Neuling 
1446021424a1SMichael Ellerman 	die("Unexpected facility unavailable exception", regs, SIGABRT);
1447d0c0c9a1SMichael Neuling }
14482517617eSMichael Neuling #endif
1449d0c0c9a1SMichael Neuling 
1450f54db641SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1451f54db641SMichael Neuling 
1452f54db641SMichael Neuling void fp_unavailable_tm(struct pt_regs *regs)
1453f54db641SMichael Neuling {
1454f54db641SMichael Neuling 	/* Note:  This does not handle any kind of FP laziness. */
1455f54db641SMichael Neuling 
1456f54db641SMichael Neuling 	TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1457f54db641SMichael Neuling 		 regs->nip, regs->msr);
1458f54db641SMichael Neuling 
1459f54db641SMichael Neuling         /* We can only have got here if the task started using FP after
1460f54db641SMichael Neuling          * beginning the transaction.  So, the transactional regs are just a
1461f54db641SMichael Neuling          * copy of the checkpointed ones.  But, we still need to recheckpoint
1462f54db641SMichael Neuling          * as we're enabling FP for the process; it will return, abort the
1463f54db641SMichael Neuling          * transaction, and probably retry but now with FP enabled.  So the
1464f54db641SMichael Neuling          * checkpointed FP registers need to be loaded.
1465f54db641SMichael Neuling 	 */
1466d31626f7SPaul Mackerras 	tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1467f54db641SMichael Neuling 	/* Reclaim didn't save out any FPRs to transact_fprs. */
1468f54db641SMichael Neuling 
1469f54db641SMichael Neuling 	/* Enable FP for the task: */
1470f54db641SMichael Neuling 	regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1471f54db641SMichael Neuling 
1472f54db641SMichael Neuling 	/* This loads and recheckpoints the FP registers from
1473f54db641SMichael Neuling 	 * thread.fpr[].  They will remain in registers after the
1474f54db641SMichael Neuling 	 * checkpoint so we don't need to reload them after.
14753ac8ff1cSPaul Mackerras 	 * If VMX is in use, the VRs now hold checkpointed values,
14763ac8ff1cSPaul Mackerras 	 * so we don't want to load the VRs from the thread_struct.
1477f54db641SMichael Neuling 	 */
14783ac8ff1cSPaul Mackerras 	tm_recheckpoint(&current->thread, MSR_FP);
14793ac8ff1cSPaul Mackerras 
14803ac8ff1cSPaul Mackerras 	/* If VMX is in use, get the transactional values back */
14813ac8ff1cSPaul Mackerras 	if (regs->msr & MSR_VEC) {
14823ac8ff1cSPaul Mackerras 		do_load_up_transact_altivec(&current->thread);
14833ac8ff1cSPaul Mackerras 		/* At this point all the VSX state is loaded, so enable it */
14843ac8ff1cSPaul Mackerras 		regs->msr |= MSR_VSX;
14853ac8ff1cSPaul Mackerras 	}
1486f54db641SMichael Neuling }
1487f54db641SMichael Neuling 
1488f54db641SMichael Neuling void altivec_unavailable_tm(struct pt_regs *regs)
1489f54db641SMichael Neuling {
1490f54db641SMichael Neuling 	/* See the comments in fp_unavailable_tm().  This function operates
1491f54db641SMichael Neuling 	 * the same way.
1492f54db641SMichael Neuling 	 */
1493f54db641SMichael Neuling 
1494f54db641SMichael Neuling 	TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1495f54db641SMichael Neuling 		 "MSR=%lx\n",
1496f54db641SMichael Neuling 		 regs->nip, regs->msr);
1497d31626f7SPaul Mackerras 	tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1498f54db641SMichael Neuling 	regs->msr |= MSR_VEC;
14993ac8ff1cSPaul Mackerras 	tm_recheckpoint(&current->thread, MSR_VEC);
1500f54db641SMichael Neuling 	current->thread.used_vr = 1;
1501f54db641SMichael Neuling 
15023ac8ff1cSPaul Mackerras 	if (regs->msr & MSR_FP) {
15033ac8ff1cSPaul Mackerras 		do_load_up_transact_fpu(&current->thread);
15043ac8ff1cSPaul Mackerras 		regs->msr |= MSR_VSX;
15053ac8ff1cSPaul Mackerras 	}
15063ac8ff1cSPaul Mackerras }
15073ac8ff1cSPaul Mackerras 
1508f54db641SMichael Neuling void vsx_unavailable_tm(struct pt_regs *regs)
1509f54db641SMichael Neuling {
15103ac8ff1cSPaul Mackerras 	unsigned long orig_msr = regs->msr;
15113ac8ff1cSPaul Mackerras 
1512f54db641SMichael Neuling 	/* See the comments in fp_unavailable_tm().  This works similarly,
1513f54db641SMichael Neuling 	 * though we're loading both FP and VEC registers in here.
1514f54db641SMichael Neuling 	 *
1515f54db641SMichael Neuling 	 * If FP isn't in use, load FP regs.  If VEC isn't in use, load VEC
1516f54db641SMichael Neuling 	 * regs.  Either way, set MSR_VSX.
1517f54db641SMichael Neuling 	 */
1518f54db641SMichael Neuling 
1519f54db641SMichael Neuling 	TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1520f54db641SMichael Neuling 		 "MSR=%lx\n",
1521f54db641SMichael Neuling 		 regs->nip, regs->msr);
1522f54db641SMichael Neuling 
15233ac8ff1cSPaul Mackerras 	current->thread.used_vsr = 1;
15243ac8ff1cSPaul Mackerras 
15253ac8ff1cSPaul Mackerras 	/* If FP and VMX are already loaded, we have all the state we need */
15263ac8ff1cSPaul Mackerras 	if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
15273ac8ff1cSPaul Mackerras 		regs->msr |= MSR_VSX;
15283ac8ff1cSPaul Mackerras 		return;
15293ac8ff1cSPaul Mackerras 	}
15303ac8ff1cSPaul Mackerras 
1531f54db641SMichael Neuling 	/* This reclaims FP and/or VR regs if they're already enabled */
1532d31626f7SPaul Mackerras 	tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1533f54db641SMichael Neuling 
1534f54db641SMichael Neuling 	regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1535f54db641SMichael Neuling 		MSR_VSX;
15363ac8ff1cSPaul Mackerras 
15373ac8ff1cSPaul Mackerras 	/* This loads & recheckpoints FP and VRs; but we have
15383ac8ff1cSPaul Mackerras 	 * to be sure not to overwrite previously-valid state.
15393ac8ff1cSPaul Mackerras 	 */
15403ac8ff1cSPaul Mackerras 	tm_recheckpoint(&current->thread, regs->msr & ~orig_msr);
15413ac8ff1cSPaul Mackerras 
15423ac8ff1cSPaul Mackerras 	if (orig_msr & MSR_FP)
15433ac8ff1cSPaul Mackerras 		do_load_up_transact_fpu(&current->thread);
15443ac8ff1cSPaul Mackerras 	if (orig_msr & MSR_VEC)
15453ac8ff1cSPaul Mackerras 		do_load_up_transact_altivec(&current->thread);
1546f54db641SMichael Neuling }
1547f54db641SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1548f54db641SMichael Neuling 
1549dc1c1ca3SStephen Rothwell void performance_monitor_exception(struct pt_regs *regs)
1550dc1c1ca3SStephen Rothwell {
155169111bacSChristoph Lameter 	__this_cpu_inc(irq_stat.pmu_irqs);
155289713ed1SAnton Blanchard 
1553dc1c1ca3SStephen Rothwell 	perf_irq(regs);
1554dc1c1ca3SStephen Rothwell }
1555dc1c1ca3SStephen Rothwell 
15568dad3f92SPaul Mackerras #ifdef CONFIG_8xx
155714cf11afSPaul Mackerras void SoftwareEmulation(struct pt_regs *regs)
155814cf11afSPaul Mackerras {
155914cf11afSPaul Mackerras 	CHECK_FULL_REGS(regs);
156014cf11afSPaul Mackerras 
156114cf11afSPaul Mackerras 	if (!user_mode(regs)) {
156214cf11afSPaul Mackerras 		debugger(regs);
15631eb2819dSLEROY Christophe 		die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
15641eb2819dSLEROY Christophe 			regs, SIGFPE);
156514cf11afSPaul Mackerras 	}
156614cf11afSPaul Mackerras 
15673a3b5aa6SKevin Hao 	if (!emulate_math(regs))
15683a3b5aa6SKevin Hao 		return;
15695fad293bSKumar Gala 
15705fad293bSKumar Gala 	_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
157114cf11afSPaul Mackerras }
15728dad3f92SPaul Mackerras #endif /* CONFIG_8xx */
157314cf11afSPaul Mackerras 
1574172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS
15753bffb652SDave Kleikamp static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
15763bffb652SDave Kleikamp {
15773bffb652SDave Kleikamp 	int changed = 0;
15783bffb652SDave Kleikamp 	/*
15793bffb652SDave Kleikamp 	 * Determine the cause of the debug event, clear the
15803bffb652SDave Kleikamp 	 * event flags and send a trap to the handler. Torez
15813bffb652SDave Kleikamp 	 */
15823bffb652SDave Kleikamp 	if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
15833bffb652SDave Kleikamp 		dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
15843bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
158551ae8d4aSBharat Bhushan 		current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
15863bffb652SDave Kleikamp #endif
15873bffb652SDave Kleikamp 		do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
15883bffb652SDave Kleikamp 			     5);
15893bffb652SDave Kleikamp 		changed |= 0x01;
15903bffb652SDave Kleikamp 	}  else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
15913bffb652SDave Kleikamp 		dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
15923bffb652SDave Kleikamp 		do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
15933bffb652SDave Kleikamp 			     6);
15943bffb652SDave Kleikamp 		changed |= 0x01;
15953bffb652SDave Kleikamp 	}  else if (debug_status & DBSR_IAC1) {
159651ae8d4aSBharat Bhushan 		current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
15973bffb652SDave Kleikamp 		dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
15983bffb652SDave Kleikamp 		do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
15993bffb652SDave Kleikamp 			     1);
16003bffb652SDave Kleikamp 		changed |= 0x01;
16013bffb652SDave Kleikamp 	}  else if (debug_status & DBSR_IAC2) {
160251ae8d4aSBharat Bhushan 		current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
16033bffb652SDave Kleikamp 		do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
16043bffb652SDave Kleikamp 			     2);
16053bffb652SDave Kleikamp 		changed |= 0x01;
16063bffb652SDave Kleikamp 	}  else if (debug_status & DBSR_IAC3) {
160751ae8d4aSBharat Bhushan 		current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
16083bffb652SDave Kleikamp 		dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
16093bffb652SDave Kleikamp 		do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
16103bffb652SDave Kleikamp 			     3);
16113bffb652SDave Kleikamp 		changed |= 0x01;
16123bffb652SDave Kleikamp 	}  else if (debug_status & DBSR_IAC4) {
161351ae8d4aSBharat Bhushan 		current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
16143bffb652SDave Kleikamp 		do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
16153bffb652SDave Kleikamp 			     4);
16163bffb652SDave Kleikamp 		changed |= 0x01;
16173bffb652SDave Kleikamp 	}
16183bffb652SDave Kleikamp 	/*
16193bffb652SDave Kleikamp 	 * At the point this routine was called, the MSR(DE) was turned off.
16203bffb652SDave Kleikamp 	 * Check all other debug flags and see if that bit needs to be turned
16213bffb652SDave Kleikamp 	 * back on or not.
16223bffb652SDave Kleikamp 	 */
162351ae8d4aSBharat Bhushan 	if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
162451ae8d4aSBharat Bhushan 			       current->thread.debug.dbcr1))
16253bffb652SDave Kleikamp 		regs->msr |= MSR_DE;
16263bffb652SDave Kleikamp 	else
16273bffb652SDave Kleikamp 		/* Make sure the IDM flag is off */
162851ae8d4aSBharat Bhushan 		current->thread.debug.dbcr0 &= ~DBCR0_IDM;
16293bffb652SDave Kleikamp 
16303bffb652SDave Kleikamp 	if (changed & 0x01)
163151ae8d4aSBharat Bhushan 		mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
16323bffb652SDave Kleikamp }
163314cf11afSPaul Mackerras 
1634f8279621SKumar Gala void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
163514cf11afSPaul Mackerras {
163651ae8d4aSBharat Bhushan 	current->thread.debug.dbsr = debug_status;
16373bffb652SDave Kleikamp 
1638ec097c84SRoland McGrath 	/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1639ec097c84SRoland McGrath 	 * on server, it stops on the target of the branch. In order to simulate
1640ec097c84SRoland McGrath 	 * the server behaviour, we thus restart right away with a single step
1641ec097c84SRoland McGrath 	 * instead of stopping here when hitting a BT
1642ec097c84SRoland McGrath 	 */
1643ec097c84SRoland McGrath 	if (debug_status & DBSR_BT) {
1644ec097c84SRoland McGrath 		regs->msr &= ~MSR_DE;
1645ec097c84SRoland McGrath 
1646ec097c84SRoland McGrath 		/* Disable BT */
1647ec097c84SRoland McGrath 		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1648ec097c84SRoland McGrath 		/* Clear the BT event */
1649ec097c84SRoland McGrath 		mtspr(SPRN_DBSR, DBSR_BT);
1650ec097c84SRoland McGrath 
1651ec097c84SRoland McGrath 		/* Do the single step trick only when coming from userspace */
1652ec097c84SRoland McGrath 		if (user_mode(regs)) {
165351ae8d4aSBharat Bhushan 			current->thread.debug.dbcr0 &= ~DBCR0_BT;
165451ae8d4aSBharat Bhushan 			current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1655ec097c84SRoland McGrath 			regs->msr |= MSR_DE;
1656ec097c84SRoland McGrath 			return;
1657ec097c84SRoland McGrath 		}
1658ec097c84SRoland McGrath 
1659ec097c84SRoland McGrath 		if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1660ec097c84SRoland McGrath 			       5, SIGTRAP) == NOTIFY_STOP) {
1661ec097c84SRoland McGrath 			return;
1662ec097c84SRoland McGrath 		}
1663ec097c84SRoland McGrath 		if (debugger_sstep(regs))
1664ec097c84SRoland McGrath 			return;
1665ec097c84SRoland McGrath 	} else if (debug_status & DBSR_IC) { 	/* Instruction complete */
166614cf11afSPaul Mackerras 		regs->msr &= ~MSR_DE;
1667f8279621SKumar Gala 
166814cf11afSPaul Mackerras 		/* Disable instruction completion */
166914cf11afSPaul Mackerras 		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
167014cf11afSPaul Mackerras 		/* Clear the instruction completion event */
167114cf11afSPaul Mackerras 		mtspr(SPRN_DBSR, DBSR_IC);
1672f8279621SKumar Gala 
1673f8279621SKumar Gala 		if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1674f8279621SKumar Gala 			       5, SIGTRAP) == NOTIFY_STOP) {
167514cf11afSPaul Mackerras 			return;
167614cf11afSPaul Mackerras 		}
1677f8279621SKumar Gala 
1678f8279621SKumar Gala 		if (debugger_sstep(regs))
1679f8279621SKumar Gala 			return;
1680f8279621SKumar Gala 
16813bffb652SDave Kleikamp 		if (user_mode(regs)) {
168251ae8d4aSBharat Bhushan 			current->thread.debug.dbcr0 &= ~DBCR0_IC;
168351ae8d4aSBharat Bhushan 			if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
168451ae8d4aSBharat Bhushan 					       current->thread.debug.dbcr1))
16853bffb652SDave Kleikamp 				regs->msr |= MSR_DE;
16863bffb652SDave Kleikamp 			else
16873bffb652SDave Kleikamp 				/* Make sure the IDM bit is off */
168851ae8d4aSBharat Bhushan 				current->thread.debug.dbcr0 &= ~DBCR0_IDM;
16893bffb652SDave Kleikamp 		}
1690f8279621SKumar Gala 
1691f8279621SKumar Gala 		_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
16923bffb652SDave Kleikamp 	} else
16933bffb652SDave Kleikamp 		handle_debug(regs, debug_status);
169414cf11afSPaul Mackerras }
1695172ae2e7SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
169614cf11afSPaul Mackerras 
169714cf11afSPaul Mackerras #if !defined(CONFIG_TAU_INT)
169814cf11afSPaul Mackerras void TAUException(struct pt_regs *regs)
169914cf11afSPaul Mackerras {
170014cf11afSPaul Mackerras 	printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
170114cf11afSPaul Mackerras 	       regs->nip, regs->msr, regs->trap, print_tainted());
170214cf11afSPaul Mackerras }
170314cf11afSPaul Mackerras #endif /* CONFIG_INT_TAU */
170414cf11afSPaul Mackerras 
170514cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC
1706dc1c1ca3SStephen Rothwell void altivec_assist_exception(struct pt_regs *regs)
170714cf11afSPaul Mackerras {
170814cf11afSPaul Mackerras 	int err;
170914cf11afSPaul Mackerras 
171014cf11afSPaul Mackerras 	if (!user_mode(regs)) {
171114cf11afSPaul Mackerras 		printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
171214cf11afSPaul Mackerras 		       " at %lx\n", regs->nip);
17138dad3f92SPaul Mackerras 		die("Kernel VMX/Altivec assist exception", regs, SIGILL);
171414cf11afSPaul Mackerras 	}
171514cf11afSPaul Mackerras 
1716dc1c1ca3SStephen Rothwell 	flush_altivec_to_thread(current);
1717dc1c1ca3SStephen Rothwell 
1718eecff81dSAnton Blanchard 	PPC_WARN_EMULATED(altivec, regs);
171914cf11afSPaul Mackerras 	err = emulate_altivec(regs);
172014cf11afSPaul Mackerras 	if (err == 0) {
172114cf11afSPaul Mackerras 		regs->nip += 4;		/* skip emulated instruction */
172214cf11afSPaul Mackerras 		emulate_single_step(regs);
172314cf11afSPaul Mackerras 		return;
172414cf11afSPaul Mackerras 	}
172514cf11afSPaul Mackerras 
172614cf11afSPaul Mackerras 	if (err == -EFAULT) {
172714cf11afSPaul Mackerras 		/* got an error reading the instruction */
172814cf11afSPaul Mackerras 		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
172914cf11afSPaul Mackerras 	} else {
173014cf11afSPaul Mackerras 		/* didn't recognize the instruction */
173114cf11afSPaul Mackerras 		/* XXX quick hack for now: set the non-Java bit in the VSCR */
173276462232SChristian Dietrich 		printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
173314cf11afSPaul Mackerras 				   "in %s at %lx\n", current->comm, regs->nip);
1734de79f7b9SPaul Mackerras 		current->thread.vr_state.vscr.u[3] |= 0x10000;
173514cf11afSPaul Mackerras 	}
173614cf11afSPaul Mackerras }
173714cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */
173814cf11afSPaul Mackerras 
173914cf11afSPaul Mackerras #ifdef CONFIG_FSL_BOOKE
174014cf11afSPaul Mackerras void CacheLockingException(struct pt_regs *regs, unsigned long address,
174114cf11afSPaul Mackerras 			   unsigned long error_code)
174214cf11afSPaul Mackerras {
174314cf11afSPaul Mackerras 	/* We treat cache locking instructions from the user
174414cf11afSPaul Mackerras 	 * as priv ops, in the future we could try to do
174514cf11afSPaul Mackerras 	 * something smarter
174614cf11afSPaul Mackerras 	 */
174714cf11afSPaul Mackerras 	if (error_code & (ESR_DLK|ESR_ILK))
174814cf11afSPaul Mackerras 		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
174914cf11afSPaul Mackerras 	return;
175014cf11afSPaul Mackerras }
175114cf11afSPaul Mackerras #endif /* CONFIG_FSL_BOOKE */
175214cf11afSPaul Mackerras 
175314cf11afSPaul Mackerras #ifdef CONFIG_SPE
175414cf11afSPaul Mackerras void SPEFloatingPointException(struct pt_regs *regs)
175514cf11afSPaul Mackerras {
17566a800f36SLiu Yu 	extern int do_spe_mathemu(struct pt_regs *regs);
175714cf11afSPaul Mackerras 	unsigned long spefscr;
175814cf11afSPaul Mackerras 	int fpexc_mode;
175914cf11afSPaul Mackerras 	int code = 0;
17606a800f36SLiu Yu 	int err;
17616a800f36SLiu Yu 
1762685659eeSyu liu 	flush_spe_to_thread(current);
176314cf11afSPaul Mackerras 
176414cf11afSPaul Mackerras 	spefscr = current->thread.spefscr;
176514cf11afSPaul Mackerras 	fpexc_mode = current->thread.fpexc_mode;
176614cf11afSPaul Mackerras 
176714cf11afSPaul Mackerras 	if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
176814cf11afSPaul Mackerras 		code = FPE_FLTOVF;
176914cf11afSPaul Mackerras 	}
177014cf11afSPaul Mackerras 	else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
177114cf11afSPaul Mackerras 		code = FPE_FLTUND;
177214cf11afSPaul Mackerras 	}
177314cf11afSPaul Mackerras 	else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
177414cf11afSPaul Mackerras 		code = FPE_FLTDIV;
177514cf11afSPaul Mackerras 	else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
177614cf11afSPaul Mackerras 		code = FPE_FLTINV;
177714cf11afSPaul Mackerras 	}
177814cf11afSPaul Mackerras 	else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
177914cf11afSPaul Mackerras 		code = FPE_FLTRES;
178014cf11afSPaul Mackerras 
17816a800f36SLiu Yu 	err = do_spe_mathemu(regs);
17826a800f36SLiu Yu 	if (err == 0) {
17836a800f36SLiu Yu 		regs->nip += 4;		/* skip emulated instruction */
17846a800f36SLiu Yu 		emulate_single_step(regs);
178514cf11afSPaul Mackerras 		return;
178614cf11afSPaul Mackerras 	}
17876a800f36SLiu Yu 
17886a800f36SLiu Yu 	if (err == -EFAULT) {
17896a800f36SLiu Yu 		/* got an error reading the instruction */
17906a800f36SLiu Yu 		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
17916a800f36SLiu Yu 	} else if (err == -EINVAL) {
17926a800f36SLiu Yu 		/* didn't recognize the instruction */
17936a800f36SLiu Yu 		printk(KERN_ERR "unrecognized spe instruction "
17946a800f36SLiu Yu 		       "in %s at %lx\n", current->comm, regs->nip);
17956a800f36SLiu Yu 	} else {
17966a800f36SLiu Yu 		_exception(SIGFPE, regs, code, regs->nip);
17976a800f36SLiu Yu 	}
17986a800f36SLiu Yu 
17996a800f36SLiu Yu 	return;
18006a800f36SLiu Yu }
18016a800f36SLiu Yu 
18026a800f36SLiu Yu void SPEFloatingPointRoundException(struct pt_regs *regs)
18036a800f36SLiu Yu {
18046a800f36SLiu Yu 	extern int speround_handler(struct pt_regs *regs);
18056a800f36SLiu Yu 	int err;
18066a800f36SLiu Yu 
18076a800f36SLiu Yu 	preempt_disable();
18086a800f36SLiu Yu 	if (regs->msr & MSR_SPE)
18096a800f36SLiu Yu 		giveup_spe(current);
18106a800f36SLiu Yu 	preempt_enable();
18116a800f36SLiu Yu 
18126a800f36SLiu Yu 	regs->nip -= 4;
18136a800f36SLiu Yu 	err = speround_handler(regs);
18146a800f36SLiu Yu 	if (err == 0) {
18156a800f36SLiu Yu 		regs->nip += 4;		/* skip emulated instruction */
18166a800f36SLiu Yu 		emulate_single_step(regs);
18176a800f36SLiu Yu 		return;
18186a800f36SLiu Yu 	}
18196a800f36SLiu Yu 
18206a800f36SLiu Yu 	if (err == -EFAULT) {
18216a800f36SLiu Yu 		/* got an error reading the instruction */
18226a800f36SLiu Yu 		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
18236a800f36SLiu Yu 	} else if (err == -EINVAL) {
18246a800f36SLiu Yu 		/* didn't recognize the instruction */
18256a800f36SLiu Yu 		printk(KERN_ERR "unrecognized spe instruction "
18266a800f36SLiu Yu 		       "in %s at %lx\n", current->comm, regs->nip);
18276a800f36SLiu Yu 	} else {
18286a800f36SLiu Yu 		_exception(SIGFPE, regs, 0, regs->nip);
18296a800f36SLiu Yu 		return;
18306a800f36SLiu Yu 	}
18316a800f36SLiu Yu }
183214cf11afSPaul Mackerras #endif
183314cf11afSPaul Mackerras 
1834dc1c1ca3SStephen Rothwell /*
1835dc1c1ca3SStephen Rothwell  * We enter here if we get an unrecoverable exception, that is, one
1836dc1c1ca3SStephen Rothwell  * that happened at a point where the RI (recoverable interrupt) bit
1837dc1c1ca3SStephen Rothwell  * in the MSR is 0.  This indicates that SRR0/1 are live, and that
1838dc1c1ca3SStephen Rothwell  * we therefore lost state by taking this exception.
1839dc1c1ca3SStephen Rothwell  */
1840dc1c1ca3SStephen Rothwell void unrecoverable_exception(struct pt_regs *regs)
1841dc1c1ca3SStephen Rothwell {
1842dc1c1ca3SStephen Rothwell 	printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1843dc1c1ca3SStephen Rothwell 	       regs->trap, regs->nip);
1844dc1c1ca3SStephen Rothwell 	die("Unrecoverable exception", regs, SIGABRT);
1845dc1c1ca3SStephen Rothwell }
1846dc1c1ca3SStephen Rothwell 
18471e18c17aSJason Gunthorpe #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
184814cf11afSPaul Mackerras /*
184914cf11afSPaul Mackerras  * Default handler for a Watchdog exception,
185014cf11afSPaul Mackerras  * spins until a reboot occurs
185114cf11afSPaul Mackerras  */
185214cf11afSPaul Mackerras void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
185314cf11afSPaul Mackerras {
185414cf11afSPaul Mackerras 	/* Generic WatchdogHandler, implement your own */
185514cf11afSPaul Mackerras 	mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
185614cf11afSPaul Mackerras 	return;
185714cf11afSPaul Mackerras }
185814cf11afSPaul Mackerras 
185914cf11afSPaul Mackerras void WatchdogException(struct pt_regs *regs)
186014cf11afSPaul Mackerras {
186114cf11afSPaul Mackerras 	printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
186214cf11afSPaul Mackerras 	WatchdogHandler(regs);
186314cf11afSPaul Mackerras }
186414cf11afSPaul Mackerras #endif
1865dc1c1ca3SStephen Rothwell 
1866dc1c1ca3SStephen Rothwell /*
1867dc1c1ca3SStephen Rothwell  * We enter here if we discover during exception entry that we are
1868dc1c1ca3SStephen Rothwell  * running in supervisor mode with a userspace value in the stack pointer.
1869dc1c1ca3SStephen Rothwell  */
1870dc1c1ca3SStephen Rothwell void kernel_bad_stack(struct pt_regs *regs)
1871dc1c1ca3SStephen Rothwell {
1872dc1c1ca3SStephen Rothwell 	printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1873dc1c1ca3SStephen Rothwell 	       regs->gpr[1], regs->nip);
1874dc1c1ca3SStephen Rothwell 	die("Bad kernel stack pointer", regs, SIGABRT);
1875dc1c1ca3SStephen Rothwell }
187614cf11afSPaul Mackerras 
187714cf11afSPaul Mackerras void __init trap_init(void)
187814cf11afSPaul Mackerras {
187914cf11afSPaul Mackerras }
188080947e7cSGeert Uytterhoeven 
188180947e7cSGeert Uytterhoeven 
188280947e7cSGeert Uytterhoeven #ifdef CONFIG_PPC_EMULATED_STATS
188380947e7cSGeert Uytterhoeven 
188480947e7cSGeert Uytterhoeven #define WARN_EMULATED_SETUP(type)	.type = { .name = #type }
188580947e7cSGeert Uytterhoeven 
188680947e7cSGeert Uytterhoeven struct ppc_emulated ppc_emulated = {
188780947e7cSGeert Uytterhoeven #ifdef CONFIG_ALTIVEC
188880947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(altivec),
188980947e7cSGeert Uytterhoeven #endif
189080947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(dcba),
189180947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(dcbz),
189280947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(fp_pair),
189380947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(isel),
189480947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(mcrxr),
189580947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(mfpvr),
189680947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(multiple),
189780947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(popcntb),
189880947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(spe),
189980947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(string),
1900a3821b2aSScott Wood 	WARN_EMULATED_SETUP(sync),
190180947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(unaligned),
190280947e7cSGeert Uytterhoeven #ifdef CONFIG_MATH_EMULATION
190380947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(math),
190480947e7cSGeert Uytterhoeven #endif
190580947e7cSGeert Uytterhoeven #ifdef CONFIG_VSX
190680947e7cSGeert Uytterhoeven 	WARN_EMULATED_SETUP(vsx),
190780947e7cSGeert Uytterhoeven #endif
1908efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64
1909efcac658SAlexey Kardashevskiy 	WARN_EMULATED_SETUP(mfdscr),
1910efcac658SAlexey Kardashevskiy 	WARN_EMULATED_SETUP(mtdscr),
1911f83319d7SAnton Blanchard 	WARN_EMULATED_SETUP(lq_stq),
1912efcac658SAlexey Kardashevskiy #endif
191380947e7cSGeert Uytterhoeven };
191480947e7cSGeert Uytterhoeven 
191580947e7cSGeert Uytterhoeven u32 ppc_warn_emulated;
191680947e7cSGeert Uytterhoeven 
191780947e7cSGeert Uytterhoeven void ppc_warn_emulated_print(const char *type)
191880947e7cSGeert Uytterhoeven {
191976462232SChristian Dietrich 	pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
192080947e7cSGeert Uytterhoeven 			    type);
192180947e7cSGeert Uytterhoeven }
192280947e7cSGeert Uytterhoeven 
192380947e7cSGeert Uytterhoeven static int __init ppc_warn_emulated_init(void)
192480947e7cSGeert Uytterhoeven {
192580947e7cSGeert Uytterhoeven 	struct dentry *dir, *d;
192680947e7cSGeert Uytterhoeven 	unsigned int i;
192780947e7cSGeert Uytterhoeven 	struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
192880947e7cSGeert Uytterhoeven 
192980947e7cSGeert Uytterhoeven 	if (!powerpc_debugfs_root)
193080947e7cSGeert Uytterhoeven 		return -ENODEV;
193180947e7cSGeert Uytterhoeven 
193280947e7cSGeert Uytterhoeven 	dir = debugfs_create_dir("emulated_instructions",
193380947e7cSGeert Uytterhoeven 				 powerpc_debugfs_root);
193480947e7cSGeert Uytterhoeven 	if (!dir)
193580947e7cSGeert Uytterhoeven 		return -ENOMEM;
193680947e7cSGeert Uytterhoeven 
193780947e7cSGeert Uytterhoeven 	d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
193880947e7cSGeert Uytterhoeven 			       &ppc_warn_emulated);
193980947e7cSGeert Uytterhoeven 	if (!d)
194080947e7cSGeert Uytterhoeven 		goto fail;
194180947e7cSGeert Uytterhoeven 
194280947e7cSGeert Uytterhoeven 	for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
194380947e7cSGeert Uytterhoeven 		d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
194480947e7cSGeert Uytterhoeven 				       (u32 *)&entries[i].val.counter);
194580947e7cSGeert Uytterhoeven 		if (!d)
194680947e7cSGeert Uytterhoeven 			goto fail;
194780947e7cSGeert Uytterhoeven 	}
194880947e7cSGeert Uytterhoeven 
194980947e7cSGeert Uytterhoeven 	return 0;
195080947e7cSGeert Uytterhoeven 
195180947e7cSGeert Uytterhoeven fail:
195280947e7cSGeert Uytterhoeven 	debugfs_remove_recursive(dir);
195380947e7cSGeert Uytterhoeven 	return -ENOMEM;
195480947e7cSGeert Uytterhoeven }
195580947e7cSGeert Uytterhoeven 
195680947e7cSGeert Uytterhoeven device_initcall(ppc_warn_emulated_init);
195780947e7cSGeert Uytterhoeven 
195880947e7cSGeert Uytterhoeven #endif /* CONFIG_PPC_EMULATED_STATS */
1959