1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/device.h> 3 #include <linux/cpu.h> 4 #include <linux/smp.h> 5 #include <linux/percpu.h> 6 #include <linux/init.h> 7 #include <linux/sched.h> 8 #include <linux/export.h> 9 #include <linux/nodemask.h> 10 #include <linux/cpumask.h> 11 #include <linux/notifier.h> 12 13 #include <asm/current.h> 14 #include <asm/processor.h> 15 #include <asm/cputable.h> 16 #include <asm/hvcall.h> 17 #include <asm/prom.h> 18 #include <asm/machdep.h> 19 #include <asm/smp.h> 20 #include <asm/pmc.h> 21 #include <asm/firmware.h> 22 #include <asm/idle.h> 23 #include <asm/svm.h> 24 25 #include "cacheinfo.h" 26 #include "setup.h" 27 28 #ifdef CONFIG_PPC64 29 #include <asm/paca.h> 30 #include <asm/lppaca.h> 31 #endif 32 33 static DEFINE_PER_CPU(struct cpu, cpu_devices); 34 35 #ifdef CONFIG_PPC64 36 37 /* 38 * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle: 39 * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in 40 * 2014: 41 * 42 * "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean 43 * up the kernel code." 44 * 45 * powerpc-utils stopped using it as of 1.3.8. At some point in the future this 46 * code should be removed. 47 */ 48 49 static ssize_t store_smt_snooze_delay(struct device *dev, 50 struct device_attribute *attr, 51 const char *buf, 52 size_t count) 53 { 54 pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n", 55 current->comm, current->pid); 56 return count; 57 } 58 59 static ssize_t show_smt_snooze_delay(struct device *dev, 60 struct device_attribute *attr, 61 char *buf) 62 { 63 pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n", 64 current->comm, current->pid); 65 return sprintf(buf, "100\n"); 66 } 67 68 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay, 69 store_smt_snooze_delay); 70 71 static int __init setup_smt_snooze_delay(char *str) 72 { 73 if (!cpu_has_feature(CPU_FTR_SMT)) 74 return 1; 75 76 pr_warn("smt-snooze-delay command line option has no effect\n"); 77 return 1; 78 } 79 __setup("smt-snooze-delay=", setup_smt_snooze_delay); 80 81 #endif /* CONFIG_PPC64 */ 82 83 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \ 84 static void read_##NAME(void *val) \ 85 { \ 86 *(unsigned long *)val = mfspr(ADDRESS); \ 87 } \ 88 static void write_##NAME(void *val) \ 89 { \ 90 EXTRA; \ 91 mtspr(ADDRESS, *(unsigned long *)val); \ 92 } 93 94 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \ 95 static ssize_t show_##NAME(struct device *dev, \ 96 struct device_attribute *attr, \ 97 char *buf) \ 98 { \ 99 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 100 unsigned long val; \ 101 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \ 102 return sprintf(buf, "%lx\n", val); \ 103 } \ 104 static ssize_t __used \ 105 store_##NAME(struct device *dev, struct device_attribute *attr, \ 106 const char *buf, size_t count) \ 107 { \ 108 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 109 unsigned long val; \ 110 int ret = sscanf(buf, "%lx", &val); \ 111 if (ret != 1) \ 112 return -EINVAL; \ 113 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \ 114 return count; \ 115 } 116 117 #define SYSFS_PMCSETUP(NAME, ADDRESS) \ 118 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \ 119 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 120 #define SYSFS_SPRSETUP(NAME, ADDRESS) \ 121 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \ 122 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 123 124 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \ 125 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 126 127 #ifdef CONFIG_PPC64 128 129 /* 130 * This is the system wide DSCR register default value. Any 131 * change to this default value through the sysfs interface 132 * will update all per cpu DSCR default values across the 133 * system stored in their respective PACA structures. 134 */ 135 static unsigned long dscr_default; 136 137 /** 138 * read_dscr() - Fetch the cpu specific DSCR default 139 * @val: Returned cpu specific DSCR default value 140 * 141 * This function returns the per cpu DSCR default value 142 * for any cpu which is contained in it's PACA structure. 143 */ 144 static void read_dscr(void *val) 145 { 146 *(unsigned long *)val = get_paca()->dscr_default; 147 } 148 149 150 /** 151 * write_dscr() - Update the cpu specific DSCR default 152 * @val: New cpu specific DSCR default value to update 153 * 154 * This function updates the per cpu DSCR default value 155 * for any cpu which is contained in it's PACA structure. 156 */ 157 static void write_dscr(void *val) 158 { 159 get_paca()->dscr_default = *(unsigned long *)val; 160 if (!current->thread.dscr_inherit) { 161 current->thread.dscr = *(unsigned long *)val; 162 mtspr(SPRN_DSCR, *(unsigned long *)val); 163 } 164 } 165 166 SYSFS_SPRSETUP_SHOW_STORE(dscr); 167 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr); 168 169 static void add_write_permission_dev_attr(struct device_attribute *attr) 170 { 171 attr->attr.mode |= 0200; 172 } 173 174 /** 175 * show_dscr_default() - Fetch the system wide DSCR default 176 * @dev: Device structure 177 * @attr: Device attribute structure 178 * @buf: Interface buffer 179 * 180 * This function returns the system wide DSCR default value. 181 */ 182 static ssize_t show_dscr_default(struct device *dev, 183 struct device_attribute *attr, char *buf) 184 { 185 return sprintf(buf, "%lx\n", dscr_default); 186 } 187 188 /** 189 * store_dscr_default() - Update the system wide DSCR default 190 * @dev: Device structure 191 * @attr: Device attribute structure 192 * @buf: Interface buffer 193 * @count: Size of the update 194 * 195 * This function updates the system wide DSCR default value. 196 */ 197 static ssize_t __used store_dscr_default(struct device *dev, 198 struct device_attribute *attr, const char *buf, 199 size_t count) 200 { 201 unsigned long val; 202 int ret = 0; 203 204 ret = sscanf(buf, "%lx", &val); 205 if (ret != 1) 206 return -EINVAL; 207 dscr_default = val; 208 209 on_each_cpu(write_dscr, &val, 1); 210 211 return count; 212 } 213 214 static DEVICE_ATTR(dscr_default, 0600, 215 show_dscr_default, store_dscr_default); 216 217 static void sysfs_create_dscr_default(void) 218 { 219 if (cpu_has_feature(CPU_FTR_DSCR)) { 220 int err = 0; 221 int cpu; 222 223 dscr_default = spr_default_dscr; 224 for_each_possible_cpu(cpu) 225 paca_ptrs[cpu]->dscr_default = dscr_default; 226 227 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default); 228 } 229 } 230 #endif /* CONFIG_PPC64 */ 231 232 #ifdef CONFIG_PPC_FSL_BOOK3E 233 #define MAX_BIT 63 234 235 static u64 pw20_wt; 236 static u64 altivec_idle_wt; 237 238 static unsigned int get_idle_ticks_bit(u64 ns) 239 { 240 u64 cycle; 241 242 if (ns >= 10000) 243 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec; 244 else 245 cycle = div_u64(ns * tb_ticks_per_usec, 1000); 246 247 if (!cycle) 248 return 0; 249 250 return ilog2(cycle); 251 } 252 253 static void do_show_pwrmgtcr0(void *val) 254 { 255 u32 *value = val; 256 257 *value = mfspr(SPRN_PWRMGTCR0); 258 } 259 260 static ssize_t show_pw20_state(struct device *dev, 261 struct device_attribute *attr, char *buf) 262 { 263 u32 value; 264 unsigned int cpu = dev->id; 265 266 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 267 268 value &= PWRMGTCR0_PW20_WAIT; 269 270 return sprintf(buf, "%u\n", value ? 1 : 0); 271 } 272 273 static void do_store_pw20_state(void *val) 274 { 275 u32 *value = val; 276 u32 pw20_state; 277 278 pw20_state = mfspr(SPRN_PWRMGTCR0); 279 280 if (*value) 281 pw20_state |= PWRMGTCR0_PW20_WAIT; 282 else 283 pw20_state &= ~PWRMGTCR0_PW20_WAIT; 284 285 mtspr(SPRN_PWRMGTCR0, pw20_state); 286 } 287 288 static ssize_t store_pw20_state(struct device *dev, 289 struct device_attribute *attr, 290 const char *buf, size_t count) 291 { 292 u32 value; 293 unsigned int cpu = dev->id; 294 295 if (kstrtou32(buf, 0, &value)) 296 return -EINVAL; 297 298 if (value > 1) 299 return -EINVAL; 300 301 smp_call_function_single(cpu, do_store_pw20_state, &value, 1); 302 303 return count; 304 } 305 306 static ssize_t show_pw20_wait_time(struct device *dev, 307 struct device_attribute *attr, char *buf) 308 { 309 u32 value; 310 u64 tb_cycle = 1; 311 u64 time; 312 313 unsigned int cpu = dev->id; 314 315 if (!pw20_wt) { 316 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 317 value = (value & PWRMGTCR0_PW20_ENT) >> 318 PWRMGTCR0_PW20_ENT_SHIFT; 319 320 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 321 /* convert ms to ns */ 322 if (tb_ticks_per_usec > 1000) { 323 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 324 } else { 325 u32 rem_us; 326 327 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 328 &rem_us); 329 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 330 } 331 } else { 332 time = pw20_wt; 333 } 334 335 return sprintf(buf, "%llu\n", time > 0 ? time : 0); 336 } 337 338 static void set_pw20_wait_entry_bit(void *val) 339 { 340 u32 *value = val; 341 u32 pw20_idle; 342 343 pw20_idle = mfspr(SPRN_PWRMGTCR0); 344 345 /* Set Automatic PW20 Core Idle Count */ 346 /* clear count */ 347 pw20_idle &= ~PWRMGTCR0_PW20_ENT; 348 349 /* set count */ 350 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT); 351 352 mtspr(SPRN_PWRMGTCR0, pw20_idle); 353 } 354 355 static ssize_t store_pw20_wait_time(struct device *dev, 356 struct device_attribute *attr, 357 const char *buf, size_t count) 358 { 359 u32 entry_bit; 360 u64 value; 361 362 unsigned int cpu = dev->id; 363 364 if (kstrtou64(buf, 0, &value)) 365 return -EINVAL; 366 367 if (!value) 368 return -EINVAL; 369 370 entry_bit = get_idle_ticks_bit(value); 371 if (entry_bit > MAX_BIT) 372 return -EINVAL; 373 374 pw20_wt = value; 375 376 smp_call_function_single(cpu, set_pw20_wait_entry_bit, 377 &entry_bit, 1); 378 379 return count; 380 } 381 382 static ssize_t show_altivec_idle(struct device *dev, 383 struct device_attribute *attr, char *buf) 384 { 385 u32 value; 386 unsigned int cpu = dev->id; 387 388 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 389 390 value &= PWRMGTCR0_AV_IDLE_PD_EN; 391 392 return sprintf(buf, "%u\n", value ? 1 : 0); 393 } 394 395 static void do_store_altivec_idle(void *val) 396 { 397 u32 *value = val; 398 u32 altivec_idle; 399 400 altivec_idle = mfspr(SPRN_PWRMGTCR0); 401 402 if (*value) 403 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN; 404 else 405 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN; 406 407 mtspr(SPRN_PWRMGTCR0, altivec_idle); 408 } 409 410 static ssize_t store_altivec_idle(struct device *dev, 411 struct device_attribute *attr, 412 const char *buf, size_t count) 413 { 414 u32 value; 415 unsigned int cpu = dev->id; 416 417 if (kstrtou32(buf, 0, &value)) 418 return -EINVAL; 419 420 if (value > 1) 421 return -EINVAL; 422 423 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1); 424 425 return count; 426 } 427 428 static ssize_t show_altivec_idle_wait_time(struct device *dev, 429 struct device_attribute *attr, char *buf) 430 { 431 u32 value; 432 u64 tb_cycle = 1; 433 u64 time; 434 435 unsigned int cpu = dev->id; 436 437 if (!altivec_idle_wt) { 438 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 439 value = (value & PWRMGTCR0_AV_IDLE_CNT) >> 440 PWRMGTCR0_AV_IDLE_CNT_SHIFT; 441 442 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 443 /* convert ms to ns */ 444 if (tb_ticks_per_usec > 1000) { 445 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 446 } else { 447 u32 rem_us; 448 449 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 450 &rem_us); 451 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 452 } 453 } else { 454 time = altivec_idle_wt; 455 } 456 457 return sprintf(buf, "%llu\n", time > 0 ? time : 0); 458 } 459 460 static void set_altivec_idle_wait_entry_bit(void *val) 461 { 462 u32 *value = val; 463 u32 altivec_idle; 464 465 altivec_idle = mfspr(SPRN_PWRMGTCR0); 466 467 /* Set Automatic AltiVec Idle Count */ 468 /* clear count */ 469 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT; 470 471 /* set count */ 472 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT); 473 474 mtspr(SPRN_PWRMGTCR0, altivec_idle); 475 } 476 477 static ssize_t store_altivec_idle_wait_time(struct device *dev, 478 struct device_attribute *attr, 479 const char *buf, size_t count) 480 { 481 u32 entry_bit; 482 u64 value; 483 484 unsigned int cpu = dev->id; 485 486 if (kstrtou64(buf, 0, &value)) 487 return -EINVAL; 488 489 if (!value) 490 return -EINVAL; 491 492 entry_bit = get_idle_ticks_bit(value); 493 if (entry_bit > MAX_BIT) 494 return -EINVAL; 495 496 altivec_idle_wt = value; 497 498 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit, 499 &entry_bit, 1); 500 501 return count; 502 } 503 504 /* 505 * Enable/Disable interface: 506 * 0, disable. 1, enable. 507 */ 508 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state); 509 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle); 510 511 /* 512 * Set wait time interface:(Nanosecond) 513 * Example: Base on TBfreq is 41MHZ. 514 * 1~48(ns): TB[63] 515 * 49~97(ns): TB[62] 516 * 98~195(ns): TB[61] 517 * 196~390(ns): TB[60] 518 * 391~780(ns): TB[59] 519 * 781~1560(ns): TB[58] 520 * ... 521 */ 522 static DEVICE_ATTR(pw20_wait_time, 0600, 523 show_pw20_wait_time, 524 store_pw20_wait_time); 525 static DEVICE_ATTR(altivec_idle_wait_time, 0600, 526 show_altivec_idle_wait_time, 527 store_altivec_idle_wait_time); 528 #endif 529 530 /* 531 * Enabling PMCs will slow partition context switch times so we only do 532 * it the first time we write to the PMCs. 533 */ 534 535 static DEFINE_PER_CPU(char, pmcs_enabled); 536 537 void ppc_enable_pmcs(void) 538 { 539 ppc_set_pmu_inuse(1); 540 541 /* Only need to enable them once */ 542 if (__this_cpu_read(pmcs_enabled)) 543 return; 544 545 __this_cpu_write(pmcs_enabled, 1); 546 547 if (ppc_md.enable_pmcs) 548 ppc_md.enable_pmcs(); 549 } 550 EXPORT_SYMBOL(ppc_enable_pmcs); 551 552 553 554 /* Let's define all possible registers, we'll only hook up the ones 555 * that are implemented on the current processor 556 */ 557 558 #ifdef CONFIG_PMU_SYSFS 559 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32) 560 #define HAS_PPC_PMC_CLASSIC 1 561 #define HAS_PPC_PMC_IBM 1 562 #endif 563 564 #ifdef CONFIG_PPC64 565 #define HAS_PPC_PMC_PA6T 1 566 #define HAS_PPC_PMC56 1 567 #endif 568 569 #ifdef CONFIG_PPC_BOOK3S_32 570 #define HAS_PPC_PMC_G4 1 571 #endif 572 #endif /* CONFIG_PMU_SYSFS */ 573 574 #if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC) 575 #define HAS_PPC_PA6T 576 #endif 577 /* 578 * SPRs which are not related to PMU. 579 */ 580 #ifdef CONFIG_PPC64 581 SYSFS_SPRSETUP(purr, SPRN_PURR); 582 SYSFS_SPRSETUP(spurr, SPRN_SPURR); 583 SYSFS_SPRSETUP(pir, SPRN_PIR); 584 SYSFS_SPRSETUP(tscr, SPRN_TSCR); 585 586 /* 587 Lets only enable read for phyp resources and 588 enable write when needed with a separate function. 589 Lets be conservative and default to pseries. 590 */ 591 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL); 592 static DEVICE_ATTR(purr, 0400, show_purr, store_purr); 593 static DEVICE_ATTR(pir, 0400, show_pir, NULL); 594 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr); 595 #endif /* CONFIG_PPC64 */ 596 597 #ifdef HAS_PPC_PMC_CLASSIC 598 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0); 599 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1); 600 SYSFS_PMCSETUP(pmc1, SPRN_PMC1); 601 SYSFS_PMCSETUP(pmc2, SPRN_PMC2); 602 SYSFS_PMCSETUP(pmc3, SPRN_PMC3); 603 SYSFS_PMCSETUP(pmc4, SPRN_PMC4); 604 SYSFS_PMCSETUP(pmc5, SPRN_PMC5); 605 SYSFS_PMCSETUP(pmc6, SPRN_PMC6); 606 #endif 607 608 #ifdef HAS_PPC_PMC_G4 609 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2); 610 #endif 611 612 #ifdef HAS_PPC_PMC56 613 SYSFS_PMCSETUP(pmc7, SPRN_PMC7); 614 SYSFS_PMCSETUP(pmc8, SPRN_PMC8); 615 616 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA); 617 SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3); 618 619 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra); 620 static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3); 621 #endif /* HAS_PPC_PMC56 */ 622 623 624 625 626 #ifdef HAS_PPC_PMC_PA6T 627 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0); 628 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1); 629 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2); 630 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3); 631 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4); 632 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5); 633 #endif 634 635 #ifdef HAS_PPC_PA6T 636 SYSFS_SPRSETUP(hid0, SPRN_HID0); 637 SYSFS_SPRSETUP(hid1, SPRN_HID1); 638 SYSFS_SPRSETUP(hid4, SPRN_HID4); 639 SYSFS_SPRSETUP(hid5, SPRN_HID5); 640 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0); 641 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1); 642 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2); 643 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3); 644 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4); 645 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5); 646 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6); 647 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7); 648 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8); 649 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9); 650 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT); 651 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR); 652 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR); 653 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR); 654 SYSFS_SPRSETUP(der, SPRN_PA6T_DER); 655 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER); 656 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER); 657 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER); 658 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER); 659 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR); 660 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0); 661 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1); 662 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2); 663 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3); 664 #endif /* HAS_PPC_PA6T */ 665 666 #ifdef HAS_PPC_PMC_IBM 667 static struct device_attribute ibm_common_attrs[] = { 668 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 669 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 670 }; 671 #endif /* HAS_PPC_PMC_IBM */ 672 673 #ifdef HAS_PPC_PMC_G4 674 static struct device_attribute g4_common_attrs[] = { 675 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 676 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 677 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2), 678 }; 679 #endif /* HAS_PPC_PMC_G4 */ 680 681 #ifdef HAS_PPC_PMC_CLASSIC 682 static struct device_attribute classic_pmc_attrs[] = { 683 __ATTR(pmc1, 0600, show_pmc1, store_pmc1), 684 __ATTR(pmc2, 0600, show_pmc2, store_pmc2), 685 __ATTR(pmc3, 0600, show_pmc3, store_pmc3), 686 __ATTR(pmc4, 0600, show_pmc4, store_pmc4), 687 __ATTR(pmc5, 0600, show_pmc5, store_pmc5), 688 __ATTR(pmc6, 0600, show_pmc6, store_pmc6), 689 #ifdef HAS_PPC_PMC56 690 __ATTR(pmc7, 0600, show_pmc7, store_pmc7), 691 __ATTR(pmc8, 0600, show_pmc8, store_pmc8), 692 #endif 693 }; 694 #endif 695 696 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T) 697 static struct device_attribute pa6t_attrs[] = { 698 #ifdef HAS_PPC_PMC_PA6T 699 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 700 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 701 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0), 702 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1), 703 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2), 704 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3), 705 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4), 706 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5), 707 #endif 708 #ifdef HAS_PPC_PA6T 709 __ATTR(hid0, 0600, show_hid0, store_hid0), 710 __ATTR(hid1, 0600, show_hid1, store_hid1), 711 __ATTR(hid4, 0600, show_hid4, store_hid4), 712 __ATTR(hid5, 0600, show_hid5, store_hid5), 713 __ATTR(ima0, 0600, show_ima0, store_ima0), 714 __ATTR(ima1, 0600, show_ima1, store_ima1), 715 __ATTR(ima2, 0600, show_ima2, store_ima2), 716 __ATTR(ima3, 0600, show_ima3, store_ima3), 717 __ATTR(ima4, 0600, show_ima4, store_ima4), 718 __ATTR(ima5, 0600, show_ima5, store_ima5), 719 __ATTR(ima6, 0600, show_ima6, store_ima6), 720 __ATTR(ima7, 0600, show_ima7, store_ima7), 721 __ATTR(ima8, 0600, show_ima8, store_ima8), 722 __ATTR(ima9, 0600, show_ima9, store_ima9), 723 __ATTR(imaat, 0600, show_imaat, store_imaat), 724 __ATTR(btcr, 0600, show_btcr, store_btcr), 725 __ATTR(pccr, 0600, show_pccr, store_pccr), 726 __ATTR(rpccr, 0600, show_rpccr, store_rpccr), 727 __ATTR(der, 0600, show_der, store_der), 728 __ATTR(mer, 0600, show_mer, store_mer), 729 __ATTR(ber, 0600, show_ber, store_ber), 730 __ATTR(ier, 0600, show_ier, store_ier), 731 __ATTR(sier, 0600, show_sier, store_sier), 732 __ATTR(siar, 0600, show_siar, store_siar), 733 __ATTR(tsr0, 0600, show_tsr0, store_tsr0), 734 __ATTR(tsr1, 0600, show_tsr1, store_tsr1), 735 __ATTR(tsr2, 0600, show_tsr2, store_tsr2), 736 __ATTR(tsr3, 0600, show_tsr3, store_tsr3), 737 #endif /* HAS_PPC_PA6T */ 738 }; 739 #endif 740 741 #ifdef CONFIG_PPC_SVM 742 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf) 743 { 744 return sprintf(buf, "%u\n", is_secure_guest()); 745 } 746 static DEVICE_ATTR(svm, 0444, show_svm, NULL); 747 748 static void create_svm_file(void) 749 { 750 device_create_file(cpu_subsys.dev_root, &dev_attr_svm); 751 } 752 #else 753 static void create_svm_file(void) 754 { 755 } 756 #endif /* CONFIG_PPC_SVM */ 757 758 #ifdef CONFIG_PPC_PSERIES 759 static void read_idle_purr(void *val) 760 { 761 u64 *ret = val; 762 763 *ret = read_this_idle_purr(); 764 } 765 766 static ssize_t idle_purr_show(struct device *dev, 767 struct device_attribute *attr, char *buf) 768 { 769 struct cpu *cpu = container_of(dev, struct cpu, dev); 770 u64 val; 771 772 smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1); 773 return sprintf(buf, "%llx\n", val); 774 } 775 static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL); 776 777 static void create_idle_purr_file(struct device *s) 778 { 779 if (firmware_has_feature(FW_FEATURE_LPAR)) 780 device_create_file(s, &dev_attr_idle_purr); 781 } 782 783 static void remove_idle_purr_file(struct device *s) 784 { 785 if (firmware_has_feature(FW_FEATURE_LPAR)) 786 device_remove_file(s, &dev_attr_idle_purr); 787 } 788 789 static void read_idle_spurr(void *val) 790 { 791 u64 *ret = val; 792 793 *ret = read_this_idle_spurr(); 794 } 795 796 static ssize_t idle_spurr_show(struct device *dev, 797 struct device_attribute *attr, char *buf) 798 { 799 struct cpu *cpu = container_of(dev, struct cpu, dev); 800 u64 val; 801 802 smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1); 803 return sprintf(buf, "%llx\n", val); 804 } 805 static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL); 806 807 static void create_idle_spurr_file(struct device *s) 808 { 809 if (firmware_has_feature(FW_FEATURE_LPAR)) 810 device_create_file(s, &dev_attr_idle_spurr); 811 } 812 813 static void remove_idle_spurr_file(struct device *s) 814 { 815 if (firmware_has_feature(FW_FEATURE_LPAR)) 816 device_remove_file(s, &dev_attr_idle_spurr); 817 } 818 819 #else /* CONFIG_PPC_PSERIES */ 820 #define create_idle_purr_file(s) 821 #define remove_idle_purr_file(s) 822 #define create_idle_spurr_file(s) 823 #define remove_idle_spurr_file(s) 824 #endif /* CONFIG_PPC_PSERIES */ 825 826 static int register_cpu_online(unsigned int cpu) 827 { 828 struct cpu *c = &per_cpu(cpu_devices, cpu); 829 struct device *s = &c->dev; 830 struct device_attribute *attrs, *pmc_attrs; 831 int i, nattrs; 832 833 /* For cpus present at boot a reference was already grabbed in register_cpu() */ 834 if (!s->of_node) 835 s->of_node = of_get_cpu_node(cpu, NULL); 836 837 #ifdef CONFIG_PPC64 838 if (cpu_has_feature(CPU_FTR_SMT)) 839 device_create_file(s, &dev_attr_smt_snooze_delay); 840 #endif 841 842 /* PMC stuff */ 843 switch (cur_cpu_spec->pmc_type) { 844 #ifdef HAS_PPC_PMC_IBM 845 case PPC_PMC_IBM: 846 attrs = ibm_common_attrs; 847 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); 848 pmc_attrs = classic_pmc_attrs; 849 break; 850 #endif /* HAS_PPC_PMC_IBM */ 851 #ifdef HAS_PPC_PMC_G4 852 case PPC_PMC_G4: 853 attrs = g4_common_attrs; 854 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); 855 pmc_attrs = classic_pmc_attrs; 856 break; 857 #endif /* HAS_PPC_PMC_G4 */ 858 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T) 859 case PPC_PMC_PA6T: 860 /* PA Semi starts counting at PMC0 */ 861 attrs = pa6t_attrs; 862 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); 863 pmc_attrs = NULL; 864 break; 865 #endif 866 default: 867 attrs = NULL; 868 nattrs = 0; 869 pmc_attrs = NULL; 870 } 871 872 for (i = 0; i < nattrs; i++) 873 device_create_file(s, &attrs[i]); 874 875 if (pmc_attrs) 876 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 877 device_create_file(s, &pmc_attrs[i]); 878 879 #ifdef CONFIG_PPC64 880 #ifdef CONFIG_PMU_SYSFS 881 if (cpu_has_feature(CPU_FTR_MMCRA)) 882 device_create_file(s, &dev_attr_mmcra); 883 884 if (cpu_has_feature(CPU_FTR_ARCH_31)) 885 device_create_file(s, &dev_attr_mmcr3); 886 #endif /* CONFIG_PMU_SYSFS */ 887 888 if (cpu_has_feature(CPU_FTR_PURR)) { 889 if (!firmware_has_feature(FW_FEATURE_LPAR)) 890 add_write_permission_dev_attr(&dev_attr_purr); 891 device_create_file(s, &dev_attr_purr); 892 create_idle_purr_file(s); 893 } 894 895 if (cpu_has_feature(CPU_FTR_SPURR)) { 896 device_create_file(s, &dev_attr_spurr); 897 create_idle_spurr_file(s); 898 } 899 900 if (cpu_has_feature(CPU_FTR_DSCR)) 901 device_create_file(s, &dev_attr_dscr); 902 903 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 904 device_create_file(s, &dev_attr_pir); 905 906 if (cpu_has_feature(CPU_FTR_ARCH_206) && 907 !firmware_has_feature(FW_FEATURE_LPAR)) 908 device_create_file(s, &dev_attr_tscr); 909 #endif /* CONFIG_PPC64 */ 910 911 #ifdef CONFIG_PPC_FSL_BOOK3E 912 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 913 device_create_file(s, &dev_attr_pw20_state); 914 device_create_file(s, &dev_attr_pw20_wait_time); 915 916 device_create_file(s, &dev_attr_altivec_idle); 917 device_create_file(s, &dev_attr_altivec_idle_wait_time); 918 } 919 #endif 920 cacheinfo_cpu_online(cpu); 921 return 0; 922 } 923 924 #ifdef CONFIG_HOTPLUG_CPU 925 static int unregister_cpu_online(unsigned int cpu) 926 { 927 struct cpu *c = &per_cpu(cpu_devices, cpu); 928 struct device *s = &c->dev; 929 struct device_attribute *attrs, *pmc_attrs; 930 int i, nattrs; 931 932 BUG_ON(!c->hotpluggable); 933 934 #ifdef CONFIG_PPC64 935 if (cpu_has_feature(CPU_FTR_SMT)) 936 device_remove_file(s, &dev_attr_smt_snooze_delay); 937 #endif 938 939 /* PMC stuff */ 940 switch (cur_cpu_spec->pmc_type) { 941 #ifdef HAS_PPC_PMC_IBM 942 case PPC_PMC_IBM: 943 attrs = ibm_common_attrs; 944 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); 945 pmc_attrs = classic_pmc_attrs; 946 break; 947 #endif /* HAS_PPC_PMC_IBM */ 948 #ifdef HAS_PPC_PMC_G4 949 case PPC_PMC_G4: 950 attrs = g4_common_attrs; 951 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); 952 pmc_attrs = classic_pmc_attrs; 953 break; 954 #endif /* HAS_PPC_PMC_G4 */ 955 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T) 956 case PPC_PMC_PA6T: 957 /* PA Semi starts counting at PMC0 */ 958 attrs = pa6t_attrs; 959 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); 960 pmc_attrs = NULL; 961 break; 962 #endif 963 default: 964 attrs = NULL; 965 nattrs = 0; 966 pmc_attrs = NULL; 967 } 968 969 for (i = 0; i < nattrs; i++) 970 device_remove_file(s, &attrs[i]); 971 972 if (pmc_attrs) 973 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 974 device_remove_file(s, &pmc_attrs[i]); 975 976 #ifdef CONFIG_PPC64 977 #ifdef CONFIG_PMU_SYSFS 978 if (cpu_has_feature(CPU_FTR_MMCRA)) 979 device_remove_file(s, &dev_attr_mmcra); 980 981 if (cpu_has_feature(CPU_FTR_ARCH_31)) 982 device_remove_file(s, &dev_attr_mmcr3); 983 #endif /* CONFIG_PMU_SYSFS */ 984 985 if (cpu_has_feature(CPU_FTR_PURR)) { 986 device_remove_file(s, &dev_attr_purr); 987 remove_idle_purr_file(s); 988 } 989 990 if (cpu_has_feature(CPU_FTR_SPURR)) { 991 device_remove_file(s, &dev_attr_spurr); 992 remove_idle_spurr_file(s); 993 } 994 995 if (cpu_has_feature(CPU_FTR_DSCR)) 996 device_remove_file(s, &dev_attr_dscr); 997 998 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 999 device_remove_file(s, &dev_attr_pir); 1000 1001 if (cpu_has_feature(CPU_FTR_ARCH_206) && 1002 !firmware_has_feature(FW_FEATURE_LPAR)) 1003 device_remove_file(s, &dev_attr_tscr); 1004 #endif /* CONFIG_PPC64 */ 1005 1006 #ifdef CONFIG_PPC_FSL_BOOK3E 1007 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 1008 device_remove_file(s, &dev_attr_pw20_state); 1009 device_remove_file(s, &dev_attr_pw20_wait_time); 1010 1011 device_remove_file(s, &dev_attr_altivec_idle); 1012 device_remove_file(s, &dev_attr_altivec_idle_wait_time); 1013 } 1014 #endif 1015 cacheinfo_cpu_offline(cpu); 1016 of_node_put(s->of_node); 1017 s->of_node = NULL; 1018 return 0; 1019 } 1020 #else /* !CONFIG_HOTPLUG_CPU */ 1021 #define unregister_cpu_online NULL 1022 #endif 1023 1024 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE 1025 ssize_t arch_cpu_probe(const char *buf, size_t count) 1026 { 1027 if (ppc_md.cpu_probe) 1028 return ppc_md.cpu_probe(buf, count); 1029 1030 return -EINVAL; 1031 } 1032 1033 ssize_t arch_cpu_release(const char *buf, size_t count) 1034 { 1035 if (ppc_md.cpu_release) 1036 return ppc_md.cpu_release(buf, count); 1037 1038 return -EINVAL; 1039 } 1040 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ 1041 1042 static DEFINE_MUTEX(cpu_mutex); 1043 1044 int cpu_add_dev_attr(struct device_attribute *attr) 1045 { 1046 int cpu; 1047 1048 mutex_lock(&cpu_mutex); 1049 1050 for_each_possible_cpu(cpu) { 1051 device_create_file(get_cpu_device(cpu), attr); 1052 } 1053 1054 mutex_unlock(&cpu_mutex); 1055 return 0; 1056 } 1057 EXPORT_SYMBOL_GPL(cpu_add_dev_attr); 1058 1059 int cpu_add_dev_attr_group(struct attribute_group *attrs) 1060 { 1061 int cpu; 1062 struct device *dev; 1063 int ret; 1064 1065 mutex_lock(&cpu_mutex); 1066 1067 for_each_possible_cpu(cpu) { 1068 dev = get_cpu_device(cpu); 1069 ret = sysfs_create_group(&dev->kobj, attrs); 1070 WARN_ON(ret != 0); 1071 } 1072 1073 mutex_unlock(&cpu_mutex); 1074 return 0; 1075 } 1076 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group); 1077 1078 1079 void cpu_remove_dev_attr(struct device_attribute *attr) 1080 { 1081 int cpu; 1082 1083 mutex_lock(&cpu_mutex); 1084 1085 for_each_possible_cpu(cpu) { 1086 device_remove_file(get_cpu_device(cpu), attr); 1087 } 1088 1089 mutex_unlock(&cpu_mutex); 1090 } 1091 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr); 1092 1093 void cpu_remove_dev_attr_group(struct attribute_group *attrs) 1094 { 1095 int cpu; 1096 struct device *dev; 1097 1098 mutex_lock(&cpu_mutex); 1099 1100 for_each_possible_cpu(cpu) { 1101 dev = get_cpu_device(cpu); 1102 sysfs_remove_group(&dev->kobj, attrs); 1103 } 1104 1105 mutex_unlock(&cpu_mutex); 1106 } 1107 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group); 1108 1109 1110 /* NUMA stuff */ 1111 1112 #ifdef CONFIG_NUMA 1113 static void register_nodes(void) 1114 { 1115 int i; 1116 1117 for (i = 0; i < MAX_NUMNODES; i++) 1118 register_one_node(i); 1119 } 1120 1121 int sysfs_add_device_to_node(struct device *dev, int nid) 1122 { 1123 struct node *node = node_devices[nid]; 1124 return sysfs_create_link(&node->dev.kobj, &dev->kobj, 1125 kobject_name(&dev->kobj)); 1126 } 1127 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node); 1128 1129 void sysfs_remove_device_from_node(struct device *dev, int nid) 1130 { 1131 struct node *node = node_devices[nid]; 1132 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj)); 1133 } 1134 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node); 1135 1136 #else 1137 static void register_nodes(void) 1138 { 1139 return; 1140 } 1141 1142 #endif 1143 1144 /* Only valid if CPU is present. */ 1145 static ssize_t show_physical_id(struct device *dev, 1146 struct device_attribute *attr, char *buf) 1147 { 1148 struct cpu *cpu = container_of(dev, struct cpu, dev); 1149 1150 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id)); 1151 } 1152 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL); 1153 1154 static int __init topology_init(void) 1155 { 1156 int cpu, r; 1157 1158 register_nodes(); 1159 1160 for_each_possible_cpu(cpu) { 1161 struct cpu *c = &per_cpu(cpu_devices, cpu); 1162 1163 #ifdef CONFIG_HOTPLUG_CPU 1164 /* 1165 * For now, we just see if the system supports making 1166 * the RTAS calls for CPU hotplug. But, there may be a 1167 * more comprehensive way to do this for an individual 1168 * CPU. For instance, the boot cpu might never be valid 1169 * for hotplugging. 1170 */ 1171 if (smp_ops->cpu_offline_self) 1172 c->hotpluggable = 1; 1173 #endif 1174 1175 if (cpu_online(cpu) || c->hotpluggable) { 1176 register_cpu(c, cpu); 1177 1178 device_create_file(&c->dev, &dev_attr_physical_id); 1179 } 1180 } 1181 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online", 1182 register_cpu_online, unregister_cpu_online); 1183 WARN_ON(r < 0); 1184 #ifdef CONFIG_PPC64 1185 sysfs_create_dscr_default(); 1186 #endif /* CONFIG_PPC64 */ 1187 1188 create_svm_file(); 1189 1190 return 0; 1191 } 1192 subsys_initcall(topology_init); 1193