1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #undef DEBUG 20 21 #include <linux/kernel.h> 22 #include <linux/pci.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 #include <linux/mm.h> 27 #include <linux/list.h> 28 #include <linux/syscalls.h> 29 #include <linux/irq.h> 30 #include <linux/vmalloc.h> 31 32 #include <asm/processor.h> 33 #include <asm/io.h> 34 #include <asm/prom.h> 35 #include <asm/pci-bridge.h> 36 #include <asm/byteorder.h> 37 #include <asm/machdep.h> 38 #include <asm/ppc-pci.h> 39 #include <asm/firmware.h> 40 41 #ifdef DEBUG 42 #include <asm/udbg.h> 43 #define DBG(fmt...) printk(fmt) 44 #else 45 #define DBG(fmt...) 46 #endif 47 48 static DEFINE_SPINLOCK(hose_spinlock); 49 50 /* XXX kill that some day ... */ 51 static int global_phb_number; /* Global phb counter */ 52 53 /* ISA Memory physical address */ 54 resource_size_t isa_mem_base; 55 56 /* Default PCI flags is 0 */ 57 unsigned int ppc_pci_flags; 58 59 static struct dma_mapping_ops *pci_dma_ops; 60 61 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops) 62 { 63 pci_dma_ops = dma_ops; 64 } 65 66 struct dma_mapping_ops *get_pci_dma_ops(void) 67 { 68 return pci_dma_ops; 69 } 70 EXPORT_SYMBOL(get_pci_dma_ops); 71 72 int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 73 { 74 return dma_set_mask(&dev->dev, mask); 75 } 76 77 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 78 { 79 int rc; 80 81 rc = dma_set_mask(&dev->dev, mask); 82 dev->dev.coherent_dma_mask = dev->dma_mask; 83 84 return rc; 85 } 86 87 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 88 { 89 struct pci_controller *phb; 90 91 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 92 if (phb == NULL) 93 return NULL; 94 spin_lock(&hose_spinlock); 95 phb->global_number = global_phb_number++; 96 list_add_tail(&phb->list_node, &hose_list); 97 spin_unlock(&hose_spinlock); 98 phb->dn = dev; 99 phb->is_dynamic = mem_init_done; 100 #ifdef CONFIG_PPC64 101 if (dev) { 102 int nid = of_node_to_nid(dev); 103 104 if (nid < 0 || !node_online(nid)) 105 nid = -1; 106 107 PHB_SET_NODE(phb, nid); 108 } 109 #endif 110 return phb; 111 } 112 113 void pcibios_free_controller(struct pci_controller *phb) 114 { 115 spin_lock(&hose_spinlock); 116 list_del(&phb->list_node); 117 spin_unlock(&hose_spinlock); 118 119 if (phb->is_dynamic) 120 kfree(phb); 121 } 122 123 int pcibios_vaddr_is_ioport(void __iomem *address) 124 { 125 int ret = 0; 126 struct pci_controller *hose; 127 unsigned long size; 128 129 spin_lock(&hose_spinlock); 130 list_for_each_entry(hose, &hose_list, list_node) { 131 #ifdef CONFIG_PPC64 132 size = hose->pci_io_size; 133 #else 134 size = hose->io_resource.end - hose->io_resource.start + 1; 135 #endif 136 if (address >= hose->io_base_virt && 137 address < (hose->io_base_virt + size)) { 138 ret = 1; 139 break; 140 } 141 } 142 spin_unlock(&hose_spinlock); 143 return ret; 144 } 145 146 /* 147 * Return the domain number for this bus. 148 */ 149 int pci_domain_nr(struct pci_bus *bus) 150 { 151 struct pci_controller *hose = pci_bus_to_host(bus); 152 153 return hose->global_number; 154 } 155 EXPORT_SYMBOL(pci_domain_nr); 156 157 #ifdef CONFIG_PPC_OF 158 159 /* This routine is meant to be used early during boot, when the 160 * PCI bus numbers have not yet been assigned, and you need to 161 * issue PCI config cycles to an OF device. 162 * It could also be used to "fix" RTAS config cycles if you want 163 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 164 * config cycles. 165 */ 166 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 167 { 168 if (!have_of) 169 return NULL; 170 while(node) { 171 struct pci_controller *hose, *tmp; 172 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 173 if (hose->dn == node) 174 return hose; 175 node = node->parent; 176 } 177 return NULL; 178 } 179 180 static ssize_t pci_show_devspec(struct device *dev, 181 struct device_attribute *attr, char *buf) 182 { 183 struct pci_dev *pdev; 184 struct device_node *np; 185 186 pdev = to_pci_dev (dev); 187 np = pci_device_to_OF_node(pdev); 188 if (np == NULL || np->full_name == NULL) 189 return 0; 190 return sprintf(buf, "%s", np->full_name); 191 } 192 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 193 #endif /* CONFIG_PPC_OF */ 194 195 /* Add sysfs properties */ 196 int pcibios_add_platform_entries(struct pci_dev *pdev) 197 { 198 #ifdef CONFIG_PPC_OF 199 return device_create_file(&pdev->dev, &dev_attr_devspec); 200 #else 201 return 0; 202 #endif /* CONFIG_PPC_OF */ 203 204 } 205 206 char __devinit *pcibios_setup(char *str) 207 { 208 return str; 209 } 210 211 void __devinit pcibios_setup_new_device(struct pci_dev *dev) 212 { 213 struct dev_archdata *sd = &dev->dev.archdata; 214 215 sd->of_node = pci_device_to_OF_node(dev); 216 217 DBG("PCI: device %s OF node: %s\n", pci_name(dev), 218 sd->of_node ? sd->of_node->full_name : "<none>"); 219 220 sd->dma_ops = pci_dma_ops; 221 #ifdef CONFIG_PPC32 222 sd->dma_data = (void *)PCI_DRAM_OFFSET; 223 #endif 224 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 225 226 if (ppc_md.pci_dma_dev_setup) 227 ppc_md.pci_dma_dev_setup(dev); 228 } 229 EXPORT_SYMBOL(pcibios_setup_new_device); 230 231 /* 232 * Reads the interrupt pin to determine if interrupt is use by card. 233 * If the interrupt is used, then gets the interrupt line from the 234 * openfirmware and sets it in the pci_dev and pci_config line. 235 */ 236 int pci_read_irq_line(struct pci_dev *pci_dev) 237 { 238 struct of_irq oirq; 239 unsigned int virq; 240 241 /* The current device-tree that iSeries generates from the HV 242 * PCI informations doesn't contain proper interrupt routing, 243 * and all the fallback would do is print out crap, so we 244 * don't attempt to resolve the interrupts here at all, some 245 * iSeries specific fixup does it. 246 * 247 * In the long run, we will hopefully fix the generated device-tree 248 * instead. 249 */ 250 #ifdef CONFIG_PPC_ISERIES 251 if (firmware_has_feature(FW_FEATURE_ISERIES)) 252 return -1; 253 #endif 254 255 DBG("Try to map irq for %s...\n", pci_name(pci_dev)); 256 257 #ifdef DEBUG 258 memset(&oirq, 0xff, sizeof(oirq)); 259 #endif 260 /* Try to get a mapping from the device-tree */ 261 if (of_irq_map_pci(pci_dev, &oirq)) { 262 u8 line, pin; 263 264 /* If that fails, lets fallback to what is in the config 265 * space and map that through the default controller. We 266 * also set the type to level low since that's what PCI 267 * interrupts are. If your platform does differently, then 268 * either provide a proper interrupt tree or don't use this 269 * function. 270 */ 271 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 272 return -1; 273 if (pin == 0) 274 return -1; 275 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 276 line == 0xff || line == 0) { 277 return -1; 278 } 279 DBG(" -> no map ! Using line %d (pin %d) from PCI config\n", 280 line, pin); 281 282 virq = irq_create_mapping(NULL, line); 283 if (virq != NO_IRQ) 284 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 285 } else { 286 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 287 oirq.size, oirq.specifier[0], oirq.specifier[1], 288 oirq.controller->full_name); 289 290 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 291 oirq.size); 292 } 293 if(virq == NO_IRQ) { 294 DBG(" -> failed to map !\n"); 295 return -1; 296 } 297 298 DBG(" -> mapped to linux irq %d\n", virq); 299 300 pci_dev->irq = virq; 301 302 return 0; 303 } 304 EXPORT_SYMBOL(pci_read_irq_line); 305 306 /* 307 * Platform support for /proc/bus/pci/X/Y mmap()s, 308 * modelled on the sparc64 implementation by Dave Miller. 309 * -- paulus. 310 */ 311 312 /* 313 * Adjust vm_pgoff of VMA such that it is the physical page offset 314 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 315 * 316 * Basically, the user finds the base address for his device which he wishes 317 * to mmap. They read the 32-bit value from the config space base register, 318 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 319 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 320 * 321 * Returns negative error code on failure, zero on success. 322 */ 323 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 324 resource_size_t *offset, 325 enum pci_mmap_state mmap_state) 326 { 327 struct pci_controller *hose = pci_bus_to_host(dev->bus); 328 unsigned long io_offset = 0; 329 int i, res_bit; 330 331 if (hose == 0) 332 return NULL; /* should never happen */ 333 334 /* If memory, add on the PCI bridge address offset */ 335 if (mmap_state == pci_mmap_mem) { 336 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 337 *offset += hose->pci_mem_offset; 338 #endif 339 res_bit = IORESOURCE_MEM; 340 } else { 341 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 342 *offset += io_offset; 343 res_bit = IORESOURCE_IO; 344 } 345 346 /* 347 * Check that the offset requested corresponds to one of the 348 * resources of the device. 349 */ 350 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 351 struct resource *rp = &dev->resource[i]; 352 int flags = rp->flags; 353 354 /* treat ROM as memory (should be already) */ 355 if (i == PCI_ROM_RESOURCE) 356 flags |= IORESOURCE_MEM; 357 358 /* Active and same type? */ 359 if ((flags & res_bit) == 0) 360 continue; 361 362 /* In the range of this resource? */ 363 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 364 continue; 365 366 /* found it! construct the final physical address */ 367 if (mmap_state == pci_mmap_io) 368 *offset += hose->io_base_phys - io_offset; 369 return rp; 370 } 371 372 return NULL; 373 } 374 375 /* 376 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 377 * device mapping. 378 */ 379 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 380 pgprot_t protection, 381 enum pci_mmap_state mmap_state, 382 int write_combine) 383 { 384 unsigned long prot = pgprot_val(protection); 385 386 /* Write combine is always 0 on non-memory space mappings. On 387 * memory space, if the user didn't pass 1, we check for a 388 * "prefetchable" resource. This is a bit hackish, but we use 389 * this to workaround the inability of /sysfs to provide a write 390 * combine bit 391 */ 392 if (mmap_state != pci_mmap_mem) 393 write_combine = 0; 394 else if (write_combine == 0) { 395 if (rp->flags & IORESOURCE_PREFETCH) 396 write_combine = 1; 397 } 398 399 /* XXX would be nice to have a way to ask for write-through */ 400 prot |= _PAGE_NO_CACHE; 401 if (write_combine) 402 prot &= ~_PAGE_GUARDED; 403 else 404 prot |= _PAGE_GUARDED; 405 406 return __pgprot(prot); 407 } 408 409 /* 410 * This one is used by /dev/mem and fbdev who have no clue about the 411 * PCI device, it tries to find the PCI device first and calls the 412 * above routine 413 */ 414 pgprot_t pci_phys_mem_access_prot(struct file *file, 415 unsigned long pfn, 416 unsigned long size, 417 pgprot_t protection) 418 { 419 struct pci_dev *pdev = NULL; 420 struct resource *found = NULL; 421 unsigned long prot = pgprot_val(protection); 422 unsigned long offset = pfn << PAGE_SHIFT; 423 int i; 424 425 if (page_is_ram(pfn)) 426 return __pgprot(prot); 427 428 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; 429 430 for_each_pci_dev(pdev) { 431 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 432 struct resource *rp = &pdev->resource[i]; 433 int flags = rp->flags; 434 435 /* Active and same type? */ 436 if ((flags & IORESOURCE_MEM) == 0) 437 continue; 438 /* In the range of this resource? */ 439 if (offset < (rp->start & PAGE_MASK) || 440 offset > rp->end) 441 continue; 442 found = rp; 443 break; 444 } 445 if (found) 446 break; 447 } 448 if (found) { 449 if (found->flags & IORESOURCE_PREFETCH) 450 prot &= ~_PAGE_GUARDED; 451 pci_dev_put(pdev); 452 } 453 454 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); 455 456 return __pgprot(prot); 457 } 458 459 460 /* 461 * Perform the actual remap of the pages for a PCI device mapping, as 462 * appropriate for this architecture. The region in the process to map 463 * is described by vm_start and vm_end members of VMA, the base physical 464 * address is found in vm_pgoff. 465 * The pci device structure is provided so that architectures may make mapping 466 * decisions on a per-device or per-bus basis. 467 * 468 * Returns a negative error code on failure, zero on success. 469 */ 470 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 471 enum pci_mmap_state mmap_state, int write_combine) 472 { 473 resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT; 474 struct resource *rp; 475 int ret; 476 477 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 478 if (rp == NULL) 479 return -EINVAL; 480 481 vma->vm_pgoff = offset >> PAGE_SHIFT; 482 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 483 vma->vm_page_prot, 484 mmap_state, write_combine); 485 486 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 487 vma->vm_end - vma->vm_start, vma->vm_page_prot); 488 489 return ret; 490 } 491 492 void pci_resource_to_user(const struct pci_dev *dev, int bar, 493 const struct resource *rsrc, 494 resource_size_t *start, resource_size_t *end) 495 { 496 struct pci_controller *hose = pci_bus_to_host(dev->bus); 497 resource_size_t offset = 0; 498 499 if (hose == NULL) 500 return; 501 502 if (rsrc->flags & IORESOURCE_IO) 503 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 504 505 /* We pass a fully fixed up address to userland for MMIO instead of 506 * a BAR value because X is lame and expects to be able to use that 507 * to pass to /dev/mem ! 508 * 509 * That means that we'll have potentially 64 bits values where some 510 * userland apps only expect 32 (like X itself since it thinks only 511 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 512 * 32 bits CHRPs :-( 513 * 514 * Hopefully, the sysfs insterface is immune to that gunk. Once X 515 * has been fixed (and the fix spread enough), we can re-enable the 516 * 2 lines below and pass down a BAR value to userland. In that case 517 * we'll also have to re-enable the matching code in 518 * __pci_mmap_make_offset(). 519 * 520 * BenH. 521 */ 522 #if 0 523 else if (rsrc->flags & IORESOURCE_MEM) 524 offset = hose->pci_mem_offset; 525 #endif 526 527 *start = rsrc->start - offset; 528 *end = rsrc->end - offset; 529 } 530 531 /** 532 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 533 * @hose: newly allocated pci_controller to be setup 534 * @dev: device node of the host bridge 535 * @primary: set if primary bus (32 bits only, soon to be deprecated) 536 * 537 * This function will parse the "ranges" property of a PCI host bridge device 538 * node and setup the resource mapping of a pci controller based on its 539 * content. 540 * 541 * Life would be boring if it wasn't for a few issues that we have to deal 542 * with here: 543 * 544 * - We can only cope with one IO space range and up to 3 Memory space 545 * ranges. However, some machines (thanks Apple !) tend to split their 546 * space into lots of small contiguous ranges. So we have to coalesce. 547 * 548 * - We can only cope with all memory ranges having the same offset 549 * between CPU addresses and PCI addresses. Unfortunately, some bridges 550 * are setup for a large 1:1 mapping along with a small "window" which 551 * maps PCI address 0 to some arbitrary high address of the CPU space in 552 * order to give access to the ISA memory hole. 553 * The way out of here that I've chosen for now is to always set the 554 * offset based on the first resource found, then override it if we 555 * have a different offset and the previous was set by an ISA hole. 556 * 557 * - Some busses have IO space not starting at 0, which causes trouble with 558 * the way we do our IO resource renumbering. The code somewhat deals with 559 * it for 64 bits but I would expect problems on 32 bits. 560 * 561 * - Some 32 bits platforms such as 4xx can have physical space larger than 562 * 32 bits so we need to use 64 bits values for the parsing 563 */ 564 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 565 struct device_node *dev, 566 int primary) 567 { 568 const u32 *ranges; 569 int rlen; 570 int pna = of_n_addr_cells(dev); 571 int np = pna + 5; 572 int memno = 0, isa_hole = -1; 573 u32 pci_space; 574 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 575 unsigned long long isa_mb = 0; 576 struct resource *res; 577 578 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 579 dev->full_name, primary ? "(primary)" : ""); 580 581 /* Get ranges property */ 582 ranges = of_get_property(dev, "ranges", &rlen); 583 if (ranges == NULL) 584 return; 585 586 /* Parse it */ 587 while ((rlen -= np * 4) >= 0) { 588 /* Read next ranges element */ 589 pci_space = ranges[0]; 590 pci_addr = of_read_number(ranges + 1, 2); 591 cpu_addr = of_translate_address(dev, ranges + 3); 592 size = of_read_number(ranges + pna + 3, 2); 593 ranges += np; 594 if (cpu_addr == OF_BAD_ADDR || size == 0) 595 continue; 596 597 /* Now consume following elements while they are contiguous */ 598 for (; rlen >= np * sizeof(u32); 599 ranges += np, rlen -= np * 4) { 600 if (ranges[0] != pci_space) 601 break; 602 pci_next = of_read_number(ranges + 1, 2); 603 cpu_next = of_translate_address(dev, ranges + 3); 604 if (pci_next != pci_addr + size || 605 cpu_next != cpu_addr + size) 606 break; 607 size += of_read_number(ranges + pna + 3, 2); 608 } 609 610 /* Act based on address space type */ 611 res = NULL; 612 switch ((pci_space >> 24) & 0x3) { 613 case 1: /* PCI IO space */ 614 printk(KERN_INFO 615 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 616 cpu_addr, cpu_addr + size - 1, pci_addr); 617 618 /* We support only one IO range */ 619 if (hose->pci_io_size) { 620 printk(KERN_INFO 621 " \\--> Skipped (too many) !\n"); 622 continue; 623 } 624 #ifdef CONFIG_PPC32 625 /* On 32 bits, limit I/O space to 16MB */ 626 if (size > 0x01000000) 627 size = 0x01000000; 628 629 /* 32 bits needs to map IOs here */ 630 hose->io_base_virt = ioremap(cpu_addr, size); 631 632 /* Expect trouble if pci_addr is not 0 */ 633 if (primary) 634 isa_io_base = 635 (unsigned long)hose->io_base_virt; 636 #endif /* CONFIG_PPC32 */ 637 /* pci_io_size and io_base_phys always represent IO 638 * space starting at 0 so we factor in pci_addr 639 */ 640 hose->pci_io_size = pci_addr + size; 641 hose->io_base_phys = cpu_addr - pci_addr; 642 643 /* Build resource */ 644 res = &hose->io_resource; 645 res->flags = IORESOURCE_IO; 646 res->start = pci_addr; 647 break; 648 case 2: /* PCI Memory space */ 649 case 3: /* PCI 64 bits Memory space */ 650 printk(KERN_INFO 651 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 652 cpu_addr, cpu_addr + size - 1, pci_addr, 653 (pci_space & 0x40000000) ? "Prefetch" : ""); 654 655 /* We support only 3 memory ranges */ 656 if (memno >= 3) { 657 printk(KERN_INFO 658 " \\--> Skipped (too many) !\n"); 659 continue; 660 } 661 /* Handles ISA memory hole space here */ 662 if (pci_addr == 0) { 663 isa_mb = cpu_addr; 664 isa_hole = memno; 665 if (primary || isa_mem_base == 0) 666 isa_mem_base = cpu_addr; 667 } 668 669 /* We get the PCI/Mem offset from the first range or 670 * the, current one if the offset came from an ISA 671 * hole. If they don't match, bugger. 672 */ 673 if (memno == 0 || 674 (isa_hole >= 0 && pci_addr != 0 && 675 hose->pci_mem_offset == isa_mb)) 676 hose->pci_mem_offset = cpu_addr - pci_addr; 677 else if (pci_addr != 0 && 678 hose->pci_mem_offset != cpu_addr - pci_addr) { 679 printk(KERN_INFO 680 " \\--> Skipped (offset mismatch) !\n"); 681 continue; 682 } 683 684 /* Build resource */ 685 res = &hose->mem_resources[memno++]; 686 res->flags = IORESOURCE_MEM; 687 if (pci_space & 0x40000000) 688 res->flags |= IORESOURCE_PREFETCH; 689 res->start = cpu_addr; 690 break; 691 } 692 if (res != NULL) { 693 res->name = dev->full_name; 694 res->end = res->start + size - 1; 695 res->parent = NULL; 696 res->sibling = NULL; 697 res->child = NULL; 698 } 699 } 700 701 /* If there's an ISA hole and the pci_mem_offset is -not- matching 702 * the ISA hole offset, then we need to remove the ISA hole from 703 * the resource list for that brige 704 */ 705 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 706 unsigned int next = isa_hole + 1; 707 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 708 if (next < memno) 709 memmove(&hose->mem_resources[isa_hole], 710 &hose->mem_resources[next], 711 sizeof(struct resource) * (memno - next)); 712 hose->mem_resources[--memno].flags = 0; 713 } 714 } 715 716 /* Decide whether to display the domain number in /proc */ 717 int pci_proc_domain(struct pci_bus *bus) 718 { 719 struct pci_controller *hose = pci_bus_to_host(bus); 720 #ifdef CONFIG_PPC64 721 return hose->buid != 0; 722 #else 723 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) 724 return 0; 725 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) 726 return hose->global_number != 0; 727 return 1; 728 #endif 729 } 730 731 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 732 struct resource *res) 733 { 734 resource_size_t offset = 0, mask = (resource_size_t)-1; 735 struct pci_controller *hose = pci_bus_to_host(dev->bus); 736 737 if (!hose) 738 return; 739 if (res->flags & IORESOURCE_IO) { 740 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 741 mask = 0xffffffffu; 742 } else if (res->flags & IORESOURCE_MEM) 743 offset = hose->pci_mem_offset; 744 745 region->start = (res->start - offset) & mask; 746 region->end = (res->end - offset) & mask; 747 } 748 EXPORT_SYMBOL(pcibios_resource_to_bus); 749 750 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 751 struct pci_bus_region *region) 752 { 753 resource_size_t offset = 0, mask = (resource_size_t)-1; 754 struct pci_controller *hose = pci_bus_to_host(dev->bus); 755 756 if (!hose) 757 return; 758 if (res->flags & IORESOURCE_IO) { 759 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 760 mask = 0xffffffffu; 761 } else if (res->flags & IORESOURCE_MEM) 762 offset = hose->pci_mem_offset; 763 res->start = (region->start + offset) & mask; 764 res->end = (region->end + offset) & mask; 765 } 766 EXPORT_SYMBOL(pcibios_bus_to_resource); 767 768 /* Fixup a bus resource into a linux resource */ 769 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) 770 { 771 struct pci_controller *hose = pci_bus_to_host(dev->bus); 772 resource_size_t offset = 0, mask = (resource_size_t)-1; 773 774 if (res->flags & IORESOURCE_IO) { 775 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 776 mask = 0xffffffffu; 777 } else if (res->flags & IORESOURCE_MEM) 778 offset = hose->pci_mem_offset; 779 780 res->start = (res->start + offset) & mask; 781 res->end = (res->end + offset) & mask; 782 783 pr_debug("PCI:%s %016llx-%016llx\n", 784 pci_name(dev), 785 (unsigned long long)res->start, 786 (unsigned long long)res->end); 787 } 788 789 790 /* This header fixup will do the resource fixup for all devices as they are 791 * probed, but not for bridge ranges 792 */ 793 static void __devinit pcibios_fixup_resources(struct pci_dev *dev) 794 { 795 struct pci_controller *hose = pci_bus_to_host(dev->bus); 796 int i; 797 798 if (!hose) { 799 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 800 pci_name(dev)); 801 return; 802 } 803 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 804 struct resource *res = dev->resource + i; 805 if (!res->flags) 806 continue; 807 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't 808 * consider 0 as an unassigned BAR value. It's technically 809 * a valid value, but linux doesn't like it... so when we can 810 * re-assign things, we do so, but if we can't, we keep it 811 * around and hope for the best... 812 */ 813 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 814 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 815 pci_name(dev), i, 816 (unsigned long long)res->start, 817 (unsigned long long)res->end, 818 (unsigned int)res->flags); 819 res->end -= res->start; 820 res->start = 0; 821 res->flags |= IORESOURCE_UNSET; 822 continue; 823 } 824 825 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", 826 pci_name(dev), i, 827 (unsigned long long)res->start,\ 828 (unsigned long long)res->end, 829 (unsigned int)res->flags); 830 831 fixup_resource(res, dev); 832 } 833 834 /* Call machine specific resource fixup */ 835 if (ppc_md.pcibios_fixup_resources) 836 ppc_md.pcibios_fixup_resources(dev); 837 } 838 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 839 840 static void __devinit __pcibios_fixup_bus(struct pci_bus *bus) 841 { 842 struct pci_controller *hose = pci_bus_to_host(bus); 843 struct pci_dev *dev = bus->self; 844 845 pr_debug("PCI: Fixup bus %d (%s)\n", bus->number, dev ? pci_name(dev) : "PHB"); 846 847 /* Fixup PCI<->PCI bridges. Host bridges are handled separately, for 848 * now differently between 32 and 64 bits. 849 */ 850 if (dev != NULL) { 851 struct resource *res; 852 int i; 853 854 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 855 if ((res = bus->resource[i]) == NULL) 856 continue; 857 if (!res->flags) 858 continue; 859 if (i >= 3 && bus->self->transparent) 860 continue; 861 /* On PowerMac, Apple leaves bridge windows open over 862 * an inaccessible region of memory space (0...fffff) 863 * which is somewhat bogus, but that's what they think 864 * means disabled... 865 * 866 * We clear those to force them to be reallocated later 867 * 868 * We detect such regions by the fact that the base is 869 * equal to the pci_mem_offset of the host bridge and 870 * their size is smaller than 1M. 871 */ 872 if (res->flags & IORESOURCE_MEM && 873 res->start == hose->pci_mem_offset && 874 res->end < 0x100000) { 875 printk(KERN_INFO 876 "PCI: Closing bogus Apple Firmware" 877 " region %d on bus 0x%02x\n", 878 i, bus->number); 879 res->flags = 0; 880 continue; 881 } 882 883 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", 884 pci_name(dev), i, 885 (unsigned long long)res->start,\ 886 (unsigned long long)res->end, 887 (unsigned int)res->flags); 888 889 fixup_resource(res, dev); 890 } 891 } 892 893 /* Additional setup that is different between 32 and 64 bits for now */ 894 pcibios_do_bus_setup(bus); 895 896 /* Platform specific bus fixups */ 897 if (ppc_md.pcibios_fixup_bus) 898 ppc_md.pcibios_fixup_bus(bus); 899 900 /* Read default IRQs and fixup if necessary */ 901 list_for_each_entry(dev, &bus->devices, bus_list) { 902 pci_read_irq_line(dev); 903 if (ppc_md.pci_irq_fixup) 904 ppc_md.pci_irq_fixup(dev); 905 } 906 } 907 908 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 909 { 910 /* When called from the generic PCI probe, read PCI<->PCI bridge 911 * bases before proceeding 912 */ 913 if (bus->self != NULL) 914 pci_read_bridge_bases(bus); 915 __pcibios_fixup_bus(bus); 916 } 917 EXPORT_SYMBOL(pcibios_fixup_bus); 918 919 /* When building a bus from the OF tree rather than probing, we need a 920 * slightly different version of the fixup which doesn't read the 921 * bridge bases using config space accesses 922 */ 923 void __devinit pcibios_fixup_of_probed_bus(struct pci_bus *bus) 924 { 925 __pcibios_fixup_bus(bus); 926 } 927 928 static int skip_isa_ioresource_align(struct pci_dev *dev) 929 { 930 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && 931 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 932 return 1; 933 return 0; 934 } 935 936 /* 937 * We need to avoid collisions with `mirrored' VGA ports 938 * and other strange ISA hardware, so we always want the 939 * addresses to be allocated in the 0x000-0x0ff region 940 * modulo 0x400. 941 * 942 * Why? Because some silly external IO cards only decode 943 * the low 10 bits of the IO address. The 0x00-0xff region 944 * is reserved for motherboard devices that decode all 16 945 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 946 * but we want to try to avoid allocating at 0x2900-0x2bff 947 * which might have be mirrored at 0x0100-0x03ff.. 948 */ 949 void pcibios_align_resource(void *data, struct resource *res, 950 resource_size_t size, resource_size_t align) 951 { 952 struct pci_dev *dev = data; 953 954 if (res->flags & IORESOURCE_IO) { 955 resource_size_t start = res->start; 956 957 if (skip_isa_ioresource_align(dev)) 958 return; 959 if (start & 0x300) { 960 start = (start + 0x3ff) & ~0x3ff; 961 res->start = start; 962 } 963 } 964 } 965 EXPORT_SYMBOL(pcibios_align_resource); 966 967 /* 968 * Reparent resource children of pr that conflict with res 969 * under res, and make res replace those children. 970 */ 971 static int __init reparent_resources(struct resource *parent, 972 struct resource *res) 973 { 974 struct resource *p, **pp; 975 struct resource **firstpp = NULL; 976 977 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 978 if (p->end < res->start) 979 continue; 980 if (res->end < p->start) 981 break; 982 if (p->start < res->start || p->end > res->end) 983 return -1; /* not completely contained */ 984 if (firstpp == NULL) 985 firstpp = pp; 986 } 987 if (firstpp == NULL) 988 return -1; /* didn't find any conflicting entries? */ 989 res->parent = parent; 990 res->child = *firstpp; 991 res->sibling = *pp; 992 *firstpp = res; 993 *pp = NULL; 994 for (p = res->child; p != NULL; p = p->sibling) { 995 p->parent = res; 996 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", 997 p->name, 998 (unsigned long long)p->start, 999 (unsigned long long)p->end, res->name); 1000 } 1001 return 0; 1002 } 1003 1004 /* 1005 * Handle resources of PCI devices. If the world were perfect, we could 1006 * just allocate all the resource regions and do nothing more. It isn't. 1007 * On the other hand, we cannot just re-allocate all devices, as it would 1008 * require us to know lots of host bridge internals. So we attempt to 1009 * keep as much of the original configuration as possible, but tweak it 1010 * when it's found to be wrong. 1011 * 1012 * Known BIOS problems we have to work around: 1013 * - I/O or memory regions not configured 1014 * - regions configured, but not enabled in the command register 1015 * - bogus I/O addresses above 64K used 1016 * - expansion ROMs left enabled (this may sound harmless, but given 1017 * the fact the PCI specs explicitly allow address decoders to be 1018 * shared between expansion ROMs and other resource regions, it's 1019 * at least dangerous) 1020 * 1021 * Our solution: 1022 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1023 * This gives us fixed barriers on where we can allocate. 1024 * (2) Allocate resources for all enabled devices. If there is 1025 * a collision, just mark the resource as unallocated. Also 1026 * disable expansion ROMs during this step. 1027 * (3) Try to allocate resources for disabled devices. If the 1028 * resources were assigned correctly, everything goes well, 1029 * if they weren't, they won't disturb allocation of other 1030 * resources. 1031 * (4) Assign new addresses to resources which were either 1032 * not configured at all or misconfigured. If explicitly 1033 * requested by the user, configure expansion ROM address 1034 * as well. 1035 */ 1036 1037 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 1038 { 1039 struct pci_bus *bus; 1040 int i; 1041 struct resource *res, *pr; 1042 1043 /* Depth-First Search on bus tree */ 1044 list_for_each_entry(bus, bus_list, node) { 1045 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 1046 if ((res = bus->resource[i]) == NULL || !res->flags 1047 || res->start > res->end) 1048 continue; 1049 if (bus->parent == NULL) 1050 pr = (res->flags & IORESOURCE_IO) ? 1051 &ioport_resource : &iomem_resource; 1052 else { 1053 /* Don't bother with non-root busses when 1054 * re-assigning all resources. We clear the 1055 * resource flags as if they were colliding 1056 * and as such ensure proper re-allocation 1057 * later. 1058 */ 1059 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) 1060 goto clear_resource; 1061 pr = pci_find_parent_resource(bus->self, res); 1062 if (pr == res) { 1063 /* this happens when the generic PCI 1064 * code (wrongly) decides that this 1065 * bridge is transparent -- paulus 1066 */ 1067 continue; 1068 } 1069 } 1070 1071 DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1072 "[0x%x], parent %p (%s)\n", 1073 bus->self ? pci_name(bus->self) : "PHB", 1074 bus->number, i, 1075 (unsigned long long)res->start, 1076 (unsigned long long)res->end, 1077 (unsigned int)res->flags, 1078 pr, (pr && pr->name) ? pr->name : "nil"); 1079 1080 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1081 if (request_resource(pr, res) == 0) 1082 continue; 1083 /* 1084 * Must be a conflict with an existing entry. 1085 * Move that entry (or entries) under the 1086 * bridge resource and try again. 1087 */ 1088 if (reparent_resources(pr, res) == 0) 1089 continue; 1090 } 1091 printk(KERN_WARNING 1092 "PCI: Cannot allocate resource region " 1093 "%d of PCI bridge %d, will remap\n", 1094 i, bus->number); 1095 clear_resource: 1096 res->flags = 0; 1097 } 1098 pcibios_allocate_bus_resources(&bus->children); 1099 } 1100 } 1101 1102 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) 1103 { 1104 struct resource *pr, *r = &dev->resource[idx]; 1105 1106 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1107 pci_name(dev), idx, 1108 (unsigned long long)r->start, 1109 (unsigned long long)r->end, 1110 (unsigned int)r->flags); 1111 1112 pr = pci_find_parent_resource(dev, r); 1113 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1114 request_resource(pr, r) < 0) { 1115 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1116 " of device %s, will remap\n", idx, pci_name(dev)); 1117 if (pr) 1118 DBG("PCI: parent is %p: %016llx-%016llx [%x]\n", pr, 1119 (unsigned long long)pr->start, 1120 (unsigned long long)pr->end, 1121 (unsigned int)pr->flags); 1122 /* We'll assign a new address later */ 1123 r->flags |= IORESOURCE_UNSET; 1124 r->end -= r->start; 1125 r->start = 0; 1126 } 1127 } 1128 1129 static void __init pcibios_allocate_resources(int pass) 1130 { 1131 struct pci_dev *dev = NULL; 1132 int idx, disabled; 1133 u16 command; 1134 struct resource *r; 1135 1136 for_each_pci_dev(dev) { 1137 pci_read_config_word(dev, PCI_COMMAND, &command); 1138 for (idx = 0; idx < 6; idx++) { 1139 r = &dev->resource[idx]; 1140 if (r->parent) /* Already allocated */ 1141 continue; 1142 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1143 continue; /* Not assigned at all */ 1144 if (r->flags & IORESOURCE_IO) 1145 disabled = !(command & PCI_COMMAND_IO); 1146 else 1147 disabled = !(command & PCI_COMMAND_MEMORY); 1148 if (pass == disabled) 1149 alloc_resource(dev, idx); 1150 } 1151 if (pass) 1152 continue; 1153 r = &dev->resource[PCI_ROM_RESOURCE]; 1154 if (r->flags & IORESOURCE_ROM_ENABLE) { 1155 /* Turn the ROM off, leave the resource region, 1156 * but keep it unregistered. 1157 */ 1158 u32 reg; 1159 DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); 1160 r->flags &= ~IORESOURCE_ROM_ENABLE; 1161 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1162 pci_write_config_dword(dev, dev->rom_base_reg, 1163 reg & ~PCI_ROM_ADDRESS_ENABLE); 1164 } 1165 } 1166 } 1167 1168 void __init pcibios_resource_survey(void) 1169 { 1170 /* Allocate and assign resources. If we re-assign everything, then 1171 * we skip the allocate phase 1172 */ 1173 pcibios_allocate_bus_resources(&pci_root_buses); 1174 1175 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { 1176 pcibios_allocate_resources(0); 1177 pcibios_allocate_resources(1); 1178 } 1179 1180 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1181 DBG("PCI: Assigning unassigned resouces...\n"); 1182 pci_assign_unassigned_resources(); 1183 } 1184 1185 /* Call machine dependent fixup */ 1186 if (ppc_md.pcibios_fixup) 1187 ppc_md.pcibios_fixup(); 1188 } 1189 1190 #ifdef CONFIG_HOTPLUG 1191 /* This is used by the pSeries hotplug driver to allocate resource 1192 * of newly plugged busses. We can try to consolidate with the 1193 * rest of the code later, for now, keep it as-is 1194 */ 1195 void __devinit pcibios_claim_one_bus(struct pci_bus *bus) 1196 { 1197 struct pci_dev *dev; 1198 struct pci_bus *child_bus; 1199 1200 list_for_each_entry(dev, &bus->devices, bus_list) { 1201 int i; 1202 1203 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1204 struct resource *r = &dev->resource[i]; 1205 1206 if (r->parent || !r->start || !r->flags) 1207 continue; 1208 pci_claim_resource(dev, i); 1209 } 1210 } 1211 1212 list_for_each_entry(child_bus, &bus->children, node) 1213 pcibios_claim_one_bus(child_bus); 1214 } 1215 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1216 #endif /* CONFIG_HOTPLUG */ 1217 1218 int pcibios_enable_device(struct pci_dev *dev, int mask) 1219 { 1220 if (ppc_md.pcibios_enable_device_hook) 1221 if (ppc_md.pcibios_enable_device_hook(dev)) 1222 return -EINVAL; 1223 1224 return pci_enable_resources(dev, mask); 1225 } 1226