1/* 2 * This file contains miscellaneous low-level functions. 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) 6 * and Paul Mackerras. 7 * 8 * kexec bits: 9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> 10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 * 17 */ 18 19#include <linux/sys.h> 20#include <asm/unistd.h> 21#include <asm/errno.h> 22#include <asm/reg.h> 23#include <asm/page.h> 24#include <asm/cache.h> 25#include <asm/cputable.h> 26#include <asm/mmu.h> 27#include <asm/ppc_asm.h> 28#include <asm/thread_info.h> 29#include <asm/asm-offsets.h> 30#include <asm/processor.h> 31#include <asm/kexec.h> 32 33 .text 34 35/* 36 * This returns the high 64 bits of the product of two 64-bit numbers. 37 */ 38_GLOBAL(mulhdu) 39 cmpwi r6,0 40 cmpwi cr1,r3,0 41 mr r10,r4 42 mulhwu r4,r4,r5 43 beq 1f 44 mulhwu r0,r10,r6 45 mullw r7,r10,r5 46 addc r7,r0,r7 47 addze r4,r4 481: beqlr cr1 /* all done if high part of A is 0 */ 49 mr r10,r3 50 mullw r9,r3,r5 51 mulhwu r3,r3,r5 52 beq 2f 53 mullw r0,r10,r6 54 mulhwu r8,r10,r6 55 addc r7,r0,r7 56 adde r4,r4,r8 57 addze r3,r3 582: addc r4,r4,r9 59 addze r3,r3 60 blr 61 62/* 63 * sub_reloc_offset(x) returns x - reloc_offset(). 64 */ 65_GLOBAL(sub_reloc_offset) 66 mflr r0 67 bl 1f 681: mflr r5 69 lis r4,1b@ha 70 addi r4,r4,1b@l 71 subf r5,r4,r5 72 subf r3,r5,r3 73 mtlr r0 74 blr 75 76/* 77 * reloc_got2 runs through the .got2 section adding an offset 78 * to each entry. 79 */ 80_GLOBAL(reloc_got2) 81 mflr r11 82 lis r7,__got2_start@ha 83 addi r7,r7,__got2_start@l 84 lis r8,__got2_end@ha 85 addi r8,r8,__got2_end@l 86 subf r8,r7,r8 87 srwi. r8,r8,2 88 beqlr 89 mtctr r8 90 bl 1f 911: mflr r0 92 lis r4,1b@ha 93 addi r4,r4,1b@l 94 subf r0,r4,r0 95 add r7,r0,r7 962: lwz r0,0(r7) 97 add r0,r0,r3 98 stw r0,0(r7) 99 addi r7,r7,4 100 bdnz 2b 101 mtlr r11 102 blr 103 104/* 105 * call_setup_cpu - call the setup_cpu function for this cpu 106 * r3 = data offset, r24 = cpu number 107 * 108 * Setup function is called with: 109 * r3 = data offset 110 * r4 = ptr to CPU spec (relocated) 111 */ 112_GLOBAL(call_setup_cpu) 113 addis r4,r3,cur_cpu_spec@ha 114 addi r4,r4,cur_cpu_spec@l 115 lwz r4,0(r4) 116 add r4,r4,r3 117 lwz r5,CPU_SPEC_SETUP(r4) 118 cmpwi 0,r5,0 119 add r5,r5,r3 120 beqlr 121 mtctr r5 122 bctr 123 124#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) 125 126/* This gets called by via-pmu.c to switch the PLL selection 127 * on 750fx CPU. This function should really be moved to some 128 * other place (as most of the cpufreq code in via-pmu 129 */ 130_GLOBAL(low_choose_750fx_pll) 131 /* Clear MSR:EE */ 132 mfmsr r7 133 rlwinm r0,r7,0,17,15 134 mtmsr r0 135 136 /* If switching to PLL1, disable HID0:BTIC */ 137 cmplwi cr0,r3,0 138 beq 1f 139 mfspr r5,SPRN_HID0 140 rlwinm r5,r5,0,27,25 141 sync 142 mtspr SPRN_HID0,r5 143 isync 144 sync 145 1461: 147 /* Calc new HID1 value */ 148 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ 149 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ 150 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ 151 or r4,r4,r5 152 mtspr SPRN_HID1,r4 153 154 /* Store new HID1 image */ 155 rlwinm r6,r1,0,0,18 156 lwz r6,TI_CPU(r6) 157 slwi r6,r6,2 158 addis r6,r6,nap_save_hid1@ha 159 stw r4,nap_save_hid1@l(r6) 160 161 /* If switching to PLL0, enable HID0:BTIC */ 162 cmplwi cr0,r3,0 163 bne 1f 164 mfspr r5,SPRN_HID0 165 ori r5,r5,HID0_BTIC 166 sync 167 mtspr SPRN_HID0,r5 168 isync 169 sync 170 1711: 172 /* Return */ 173 mtmsr r7 174 blr 175 176_GLOBAL(low_choose_7447a_dfs) 177 /* Clear MSR:EE */ 178 mfmsr r7 179 rlwinm r0,r7,0,17,15 180 mtmsr r0 181 182 /* Calc new HID1 value */ 183 mfspr r4,SPRN_HID1 184 insrwi r4,r3,1,9 /* insert parameter into bit 9 */ 185 sync 186 mtspr SPRN_HID1,r4 187 sync 188 isync 189 190 /* Return */ 191 mtmsr r7 192 blr 193 194#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ 195 196/* 197 * complement mask on the msr then "or" some values on. 198 * _nmask_and_or_msr(nmask, value_to_or) 199 */ 200_GLOBAL(_nmask_and_or_msr) 201 mfmsr r0 /* Get current msr */ 202 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ 203 or r0,r0,r4 /* Or on the bits in r4 (second parm) */ 204 SYNC /* Some chip revs have problems here... */ 205 mtmsr r0 /* Update machine state */ 206 isync 207 blr /* Done */ 208 209 210/* 211 * Flush MMU TLB 212 */ 213_GLOBAL(_tlbia) 214#if defined(CONFIG_40x) 215 sync /* Flush to memory before changing mapping */ 216 tlbia 217 isync /* Flush shadow TLB */ 218#elif defined(CONFIG_44x) 219 li r3,0 220 sync 221 222 /* Load high watermark */ 223 lis r4,tlb_44x_hwater@ha 224 lwz r5,tlb_44x_hwater@l(r4) 225 2261: tlbwe r3,r3,PPC44x_TLB_PAGEID 227 addi r3,r3,1 228 cmpw 0,r3,r5 229 ble 1b 230 231 isync 232#elif defined(CONFIG_FSL_BOOKE) 233 /* Invalidate all entries in TLB0 */ 234 li r3, 0x04 235 tlbivax 0,3 236 /* Invalidate all entries in TLB1 */ 237 li r3, 0x0c 238 tlbivax 0,3 239 /* Invalidate all entries in TLB2 */ 240 li r3, 0x14 241 tlbivax 0,3 242 /* Invalidate all entries in TLB3 */ 243 li r3, 0x1c 244 tlbivax 0,3 245 msync 246#ifdef CONFIG_SMP 247 tlbsync 248#endif /* CONFIG_SMP */ 249#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ 250#if defined(CONFIG_SMP) 251 rlwinm r8,r1,0,0,18 252 lwz r8,TI_CPU(r8) 253 oris r8,r8,10 254 mfmsr r10 255 SYNC 256 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 257 rlwinm r0,r0,0,28,26 /* clear DR */ 258 mtmsr r0 259 SYNC_601 260 isync 261 lis r9,mmu_hash_lock@h 262 ori r9,r9,mmu_hash_lock@l 263 tophys(r9,r9) 26410: lwarx r7,0,r9 265 cmpwi 0,r7,0 266 bne- 10b 267 stwcx. r8,0,r9 268 bne- 10b 269 sync 270 tlbia 271 sync 272 TLBSYNC 273 li r0,0 274 stw r0,0(r9) /* clear mmu_hash_lock */ 275 mtmsr r10 276 SYNC_601 277 isync 278#else /* CONFIG_SMP */ 279 sync 280 tlbia 281 sync 282#endif /* CONFIG_SMP */ 283#endif /* ! defined(CONFIG_40x) */ 284 blr 285 286/* 287 * Flush MMU TLB for a particular address 288 */ 289_GLOBAL(_tlbie) 290#if defined(CONFIG_40x) 291 tlbsx. r3, 0, r3 292 bne 10f 293 sync 294 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. 295 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate 296 * the TLB entry. */ 297 tlbwe r3, r3, TLB_TAG 298 isync 29910: 300#elif defined(CONFIG_44x) 301 mfspr r4,SPRN_MMUCR 302 mfspr r5,SPRN_PID /* Get PID */ 303 rlwimi r4,r5,0,24,31 /* Set TID */ 304 305 /* We have to run the search with interrupts disabled, even critical 306 * and debug interrupts (in fact the only critical exceptions we have 307 * are debug and machine check). Otherwise an interrupt which causes 308 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ 309 mfmsr r5 310 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha 311 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l 312 andc r6,r5,r6 313 mtmsr r6 314 mtspr SPRN_MMUCR,r4 315 tlbsx. r3, 0, r3 316 mtmsr r5 317 bne 10f 318 sync 319 /* There are only 64 TLB entries, so r3 < 64, 320 * which means bit 22, is clear. Since 22 is 321 * the V bit in the TLB_PAGEID, loading this 322 * value will invalidate the TLB entry. 323 */ 324 tlbwe r3, r3, PPC44x_TLB_PAGEID 325 isync 32610: 327#elif defined(CONFIG_FSL_BOOKE) 328 rlwinm r4, r3, 0, 0, 19 329 ori r5, r4, 0x08 /* TLBSEL = 1 */ 330 ori r6, r4, 0x10 /* TLBSEL = 2 */ 331 ori r7, r4, 0x18 /* TLBSEL = 3 */ 332 tlbivax 0, r4 333 tlbivax 0, r5 334 tlbivax 0, r6 335 tlbivax 0, r7 336 msync 337#if defined(CONFIG_SMP) 338 tlbsync 339#endif /* CONFIG_SMP */ 340#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ 341#if defined(CONFIG_SMP) 342 rlwinm r8,r1,0,0,18 343 lwz r8,TI_CPU(r8) 344 oris r8,r8,11 345 mfmsr r10 346 SYNC 347 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 348 rlwinm r0,r0,0,28,26 /* clear DR */ 349 mtmsr r0 350 SYNC_601 351 isync 352 lis r9,mmu_hash_lock@h 353 ori r9,r9,mmu_hash_lock@l 354 tophys(r9,r9) 35510: lwarx r7,0,r9 356 cmpwi 0,r7,0 357 bne- 10b 358 stwcx. r8,0,r9 359 bne- 10b 360 eieio 361 tlbie r3 362 sync 363 TLBSYNC 364 li r0,0 365 stw r0,0(r9) /* clear mmu_hash_lock */ 366 mtmsr r10 367 SYNC_601 368 isync 369#else /* CONFIG_SMP */ 370 tlbie r3 371 sync 372#endif /* CONFIG_SMP */ 373#endif /* ! CONFIG_40x */ 374 blr 375 376/* 377 * Flush instruction cache. 378 * This is a no-op on the 601. 379 */ 380_GLOBAL(flush_instruction_cache) 381#if defined(CONFIG_8xx) 382 isync 383 lis r5, IDC_INVALL@h 384 mtspr SPRN_IC_CST, r5 385#elif defined(CONFIG_4xx) 386#ifdef CONFIG_403GCX 387 li r3, 512 388 mtctr r3 389 lis r4, KERNELBASE@h 3901: iccci 0, r4 391 addi r4, r4, 16 392 bdnz 1b 393#else 394 lis r3, KERNELBASE@h 395 iccci 0,r3 396#endif 397#elif CONFIG_FSL_BOOKE 398BEGIN_FTR_SECTION 399 mfspr r3,SPRN_L1CSR0 400 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC 401 /* msync; isync recommended here */ 402 mtspr SPRN_L1CSR0,r3 403 isync 404 blr 405END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) 406 mfspr r3,SPRN_L1CSR1 407 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR 408 mtspr SPRN_L1CSR1,r3 409#else 410 mfspr r3,SPRN_PVR 411 rlwinm r3,r3,16,16,31 412 cmpwi 0,r3,1 413 beqlr /* for 601, do nothing */ 414 /* 603/604 processor - use invalidate-all bit in HID0 */ 415 mfspr r3,SPRN_HID0 416 ori r3,r3,HID0_ICFI 417 mtspr SPRN_HID0,r3 418#endif /* CONFIG_8xx/4xx */ 419 isync 420 blr 421 422/* 423 * Write any modified data cache blocks out to memory 424 * and invalidate the corresponding instruction cache blocks. 425 * This is a no-op on the 601. 426 * 427 * flush_icache_range(unsigned long start, unsigned long stop) 428 */ 429_GLOBAL(__flush_icache_range) 430BEGIN_FTR_SECTION 431 blr /* for 601, do nothing */ 432END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 433 li r5,L1_CACHE_BYTES-1 434 andc r3,r3,r5 435 subf r4,r3,r4 436 add r4,r4,r5 437 srwi. r4,r4,L1_CACHE_SHIFT 438 beqlr 439 mtctr r4 440 mr r6,r3 4411: dcbst 0,r3 442 addi r3,r3,L1_CACHE_BYTES 443 bdnz 1b 444 sync /* wait for dcbst's to get to ram */ 445 mtctr r4 4462: icbi 0,r6 447 addi r6,r6,L1_CACHE_BYTES 448 bdnz 2b 449 sync /* additional sync needed on g4 */ 450 isync 451 blr 452/* 453 * Write any modified data cache blocks out to memory. 454 * Does not invalidate the corresponding cache lines (especially for 455 * any corresponding instruction cache). 456 * 457 * clean_dcache_range(unsigned long start, unsigned long stop) 458 */ 459_GLOBAL(clean_dcache_range) 460 li r5,L1_CACHE_BYTES-1 461 andc r3,r3,r5 462 subf r4,r3,r4 463 add r4,r4,r5 464 srwi. r4,r4,L1_CACHE_SHIFT 465 beqlr 466 mtctr r4 467 4681: dcbst 0,r3 469 addi r3,r3,L1_CACHE_BYTES 470 bdnz 1b 471 sync /* wait for dcbst's to get to ram */ 472 blr 473 474/* 475 * Write any modified data cache blocks out to memory and invalidate them. 476 * Does not invalidate the corresponding instruction cache blocks. 477 * 478 * flush_dcache_range(unsigned long start, unsigned long stop) 479 */ 480_GLOBAL(flush_dcache_range) 481 li r5,L1_CACHE_BYTES-1 482 andc r3,r3,r5 483 subf r4,r3,r4 484 add r4,r4,r5 485 srwi. r4,r4,L1_CACHE_SHIFT 486 beqlr 487 mtctr r4 488 4891: dcbf 0,r3 490 addi r3,r3,L1_CACHE_BYTES 491 bdnz 1b 492 sync /* wait for dcbst's to get to ram */ 493 blr 494 495/* 496 * Like above, but invalidate the D-cache. This is used by the 8xx 497 * to invalidate the cache so the PPC core doesn't get stale data 498 * from the CPM (no cache snooping here :-). 499 * 500 * invalidate_dcache_range(unsigned long start, unsigned long stop) 501 */ 502_GLOBAL(invalidate_dcache_range) 503 li r5,L1_CACHE_BYTES-1 504 andc r3,r3,r5 505 subf r4,r3,r4 506 add r4,r4,r5 507 srwi. r4,r4,L1_CACHE_SHIFT 508 beqlr 509 mtctr r4 510 5111: dcbi 0,r3 512 addi r3,r3,L1_CACHE_BYTES 513 bdnz 1b 514 sync /* wait for dcbi's to get to ram */ 515 blr 516 517/* 518 * Flush a particular page from the data cache to RAM. 519 * Note: this is necessary because the instruction cache does *not* 520 * snoop from the data cache. 521 * This is a no-op on the 601 which has a unified cache. 522 * 523 * void __flush_dcache_icache(void *page) 524 */ 525_GLOBAL(__flush_dcache_icache) 526BEGIN_FTR_SECTION 527 blr 528END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 529 rlwinm r3,r3,0,0,19 /* Get page base address */ 530 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ 531 mtctr r4 532 mr r6,r3 5330: dcbst 0,r3 /* Write line to ram */ 534 addi r3,r3,L1_CACHE_BYTES 535 bdnz 0b 536 sync 537 mtctr r4 5381: icbi 0,r6 539 addi r6,r6,L1_CACHE_BYTES 540 bdnz 1b 541 sync 542 isync 543 blr 544 545/* 546 * Flush a particular page from the data cache to RAM, identified 547 * by its physical address. We turn off the MMU so we can just use 548 * the physical address (this may be a highmem page without a kernel 549 * mapping). 550 * 551 * void __flush_dcache_icache_phys(unsigned long physaddr) 552 */ 553_GLOBAL(__flush_dcache_icache_phys) 554BEGIN_FTR_SECTION 555 blr /* for 601, do nothing */ 556END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 557 mfmsr r10 558 rlwinm r0,r10,0,28,26 /* clear DR */ 559 mtmsr r0 560 isync 561 rlwinm r3,r3,0,0,19 /* Get page base address */ 562 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ 563 mtctr r4 564 mr r6,r3 5650: dcbst 0,r3 /* Write line to ram */ 566 addi r3,r3,L1_CACHE_BYTES 567 bdnz 0b 568 sync 569 mtctr r4 5701: icbi 0,r6 571 addi r6,r6,L1_CACHE_BYTES 572 bdnz 1b 573 sync 574 mtmsr r10 /* restore DR */ 575 isync 576 blr 577 578/* 579 * Clear pages using the dcbz instruction, which doesn't cause any 580 * memory traffic (except to write out any cache lines which get 581 * displaced). This only works on cacheable memory. 582 * 583 * void clear_pages(void *page, int order) ; 584 */ 585_GLOBAL(clear_pages) 586 li r0,4096/L1_CACHE_BYTES 587 slw r0,r0,r4 588 mtctr r0 589#ifdef CONFIG_8xx 590 li r4, 0 5911: stw r4, 0(r3) 592 stw r4, 4(r3) 593 stw r4, 8(r3) 594 stw r4, 12(r3) 595#else 5961: dcbz 0,r3 597#endif 598 addi r3,r3,L1_CACHE_BYTES 599 bdnz 1b 600 blr 601 602/* 603 * Copy a whole page. We use the dcbz instruction on the destination 604 * to reduce memory traffic (it eliminates the unnecessary reads of 605 * the destination into cache). This requires that the destination 606 * is cacheable. 607 */ 608#define COPY_16_BYTES \ 609 lwz r6,4(r4); \ 610 lwz r7,8(r4); \ 611 lwz r8,12(r4); \ 612 lwzu r9,16(r4); \ 613 stw r6,4(r3); \ 614 stw r7,8(r3); \ 615 stw r8,12(r3); \ 616 stwu r9,16(r3) 617 618_GLOBAL(copy_page) 619 addi r3,r3,-4 620 addi r4,r4,-4 621 622#ifdef CONFIG_8xx 623 /* don't use prefetch on 8xx */ 624 li r0,4096/L1_CACHE_BYTES 625 mtctr r0 6261: COPY_16_BYTES 627 bdnz 1b 628 blr 629 630#else /* not 8xx, we can prefetch */ 631 li r5,4 632 633#if MAX_COPY_PREFETCH > 1 634 li r0,MAX_COPY_PREFETCH 635 li r11,4 636 mtctr r0 63711: dcbt r11,r4 638 addi r11,r11,L1_CACHE_BYTES 639 bdnz 11b 640#else /* MAX_COPY_PREFETCH == 1 */ 641 dcbt r5,r4 642 li r11,L1_CACHE_BYTES+4 643#endif /* MAX_COPY_PREFETCH */ 644 li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH 645 crclr 4*cr0+eq 6462: 647 mtctr r0 6481: 649 dcbt r11,r4 650 dcbz r5,r3 651 COPY_16_BYTES 652#if L1_CACHE_BYTES >= 32 653 COPY_16_BYTES 654#if L1_CACHE_BYTES >= 64 655 COPY_16_BYTES 656 COPY_16_BYTES 657#if L1_CACHE_BYTES >= 128 658 COPY_16_BYTES 659 COPY_16_BYTES 660 COPY_16_BYTES 661 COPY_16_BYTES 662#endif 663#endif 664#endif 665 bdnz 1b 666 beqlr 667 crnot 4*cr0+eq,4*cr0+eq 668 li r0,MAX_COPY_PREFETCH 669 li r11,4 670 b 2b 671#endif /* CONFIG_8xx */ 672 673/* 674 * void atomic_clear_mask(atomic_t mask, atomic_t *addr) 675 * void atomic_set_mask(atomic_t mask, atomic_t *addr); 676 */ 677_GLOBAL(atomic_clear_mask) 67810: lwarx r5,0,r4 679 andc r5,r5,r3 680 PPC405_ERR77(0,r4) 681 stwcx. r5,0,r4 682 bne- 10b 683 blr 684_GLOBAL(atomic_set_mask) 68510: lwarx r5,0,r4 686 or r5,r5,r3 687 PPC405_ERR77(0,r4) 688 stwcx. r5,0,r4 689 bne- 10b 690 blr 691 692/* 693 * Extended precision shifts. 694 * 695 * Updated to be valid for shift counts from 0 to 63 inclusive. 696 * -- Gabriel 697 * 698 * R3/R4 has 64 bit value 699 * R5 has shift count 700 * result in R3/R4 701 * 702 * ashrdi3: arithmetic right shift (sign propagation) 703 * lshrdi3: logical right shift 704 * ashldi3: left shift 705 */ 706_GLOBAL(__ashrdi3) 707 subfic r6,r5,32 708 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 709 addi r7,r5,32 # could be xori, or addi with -32 710 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 711 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 712 sraw r7,r3,r7 # t2 = MSW >> (count-32) 713 or r4,r4,r6 # LSW |= t1 714 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 715 sraw r3,r3,r5 # MSW = MSW >> count 716 or r4,r4,r7 # LSW |= t2 717 blr 718 719_GLOBAL(__ashldi3) 720 subfic r6,r5,32 721 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count 722 addi r7,r5,32 # could be xori, or addi with -32 723 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) 724 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) 725 or r3,r3,r6 # MSW |= t1 726 slw r4,r4,r5 # LSW = LSW << count 727 or r3,r3,r7 # MSW |= t2 728 blr 729 730_GLOBAL(__lshrdi3) 731 subfic r6,r5,32 732 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 733 addi r7,r5,32 # could be xori, or addi with -32 734 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 735 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) 736 or r4,r4,r6 # LSW |= t1 737 srw r3,r3,r5 # MSW = MSW >> count 738 or r4,r4,r7 # LSW |= t2 739 blr 740 741_GLOBAL(abs) 742 srawi r4,r3,31 743 xor r3,r3,r4 744 sub r3,r3,r4 745 blr 746 747/* 748 * Create a kernel thread 749 * kernel_thread(fn, arg, flags) 750 */ 751_GLOBAL(kernel_thread) 752 stwu r1,-16(r1) 753 stw r30,8(r1) 754 stw r31,12(r1) 755 mr r30,r3 /* function */ 756 mr r31,r4 /* argument */ 757 ori r3,r5,CLONE_VM /* flags */ 758 oris r3,r3,CLONE_UNTRACED>>16 759 li r4,0 /* new sp (unused) */ 760 li r0,__NR_clone 761 sc 762 cmpwi 0,r3,0 /* parent or child? */ 763 bne 1f /* return if parent */ 764 li r0,0 /* make top-level stack frame */ 765 stwu r0,-16(r1) 766 mtlr r30 /* fn addr in lr */ 767 mr r3,r31 /* load arg and call fn */ 768 PPC440EP_ERR42 769 blrl 770 li r0,__NR_exit /* exit if function returns */ 771 li r3,0 772 sc 7731: lwz r30,8(r1) 774 lwz r31,12(r1) 775 addi r1,r1,16 776 blr 777 778_GLOBAL(kernel_execve) 779 li r0,__NR_execve 780 sc 781 bnslr 782 neg r3,r3 783 blr 784 785/* 786 * This routine is just here to keep GCC happy - sigh... 787 */ 788_GLOBAL(__main) 789 blr 790 791#ifdef CONFIG_KEXEC 792 /* 793 * Must be relocatable PIC code callable as a C function. 794 */ 795 .globl relocate_new_kernel 796relocate_new_kernel: 797 /* r3 = page_list */ 798 /* r4 = reboot_code_buffer */ 799 /* r5 = start_address */ 800 801 li r0, 0 802 803 /* 804 * Set Machine Status Register to a known status, 805 * switch the MMU off and jump to 1: in a single step. 806 */ 807 808 mr r8, r0 809 ori r8, r8, MSR_RI|MSR_ME 810 mtspr SPRN_SRR1, r8 811 addi r8, r4, 1f - relocate_new_kernel 812 mtspr SPRN_SRR0, r8 813 sync 814 rfi 815 8161: 817 /* from this point address translation is turned off */ 818 /* and interrupts are disabled */ 819 820 /* set a new stack at the bottom of our page... */ 821 /* (not really needed now) */ 822 addi r1, r4, KEXEC_CONTROL_CODE_SIZE - 8 /* for LR Save+Back Chain */ 823 stw r0, 0(r1) 824 825 /* Do the copies */ 826 li r6, 0 /* checksum */ 827 mr r0, r3 828 b 1f 829 8300: /* top, read another word for the indirection page */ 831 lwzu r0, 4(r3) 832 8331: 834 /* is it a destination page? (r8) */ 835 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ 836 beq 2f 837 838 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ 839 b 0b 840 8412: /* is it an indirection page? (r3) */ 842 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ 843 beq 2f 844 845 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ 846 subi r3, r3, 4 847 b 0b 848 8492: /* are we done? */ 850 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ 851 beq 2f 852 b 3f 853 8542: /* is it a source page? (r9) */ 855 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ 856 beq 0b 857 858 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ 859 860 li r7, PAGE_SIZE / 4 861 mtctr r7 862 subi r9, r9, 4 863 subi r8, r8, 4 8649: 865 lwzu r0, 4(r9) /* do the copy */ 866 xor r6, r6, r0 867 stwu r0, 4(r8) 868 dcbst 0, r8 869 sync 870 icbi 0, r8 871 bdnz 9b 872 873 addi r9, r9, 4 874 addi r8, r8, 4 875 b 0b 876 8773: 878 879 /* To be certain of avoiding problems with self-modifying code 880 * execute a serializing instruction here. 881 */ 882 isync 883 sync 884 885 /* jump to the entry point, usually the setup routine */ 886 mtlr r5 887 blrl 888 8891: b 1b 890 891relocate_new_kernel_end: 892 893 .globl relocate_new_kernel_size 894relocate_new_kernel_size: 895 .long relocate_new_kernel_end - relocate_new_kernel 896#endif 897