1/* 2 * This file contains idle entry/exit functions for POWER7, 3 * POWER8 and POWER9 CPUs. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 11#include <linux/threads.h> 12#include <asm/processor.h> 13#include <asm/page.h> 14#include <asm/cputable.h> 15#include <asm/thread_info.h> 16#include <asm/ppc_asm.h> 17#include <asm/asm-offsets.h> 18#include <asm/ppc-opcode.h> 19#include <asm/hw_irq.h> 20#include <asm/kvm_book3s_asm.h> 21#include <asm/opal.h> 22#include <asm/cpuidle.h> 23#include <asm/exception-64s.h> 24#include <asm/book3s/64/mmu-hash.h> 25#include <asm/mmu.h> 26 27#undef DEBUG 28 29/* 30 * Use unused space in the interrupt stack to save and restore 31 * registers for winkle support. 32 */ 33#define _MMCR0 GPR0 34#define _SDR1 GPR3 35#define _PTCR GPR3 36#define _RPR GPR4 37#define _SPURR GPR5 38#define _PURR GPR6 39#define _TSCR GPR7 40#define _DSCR GPR8 41#define _AMOR GPR9 42#define _WORT GPR10 43#define _WORC GPR11 44#define _LPCR GPR12 45 46#define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16 47 48 .text 49 50/* 51 * Used by threads before entering deep idle states. Saves SPRs 52 * in interrupt stack frame 53 */ 54save_sprs_to_stack: 55 /* 56 * Note all register i.e per-core, per-subcore or per-thread is saved 57 * here since any thread in the core might wake up first 58 */ 59BEGIN_FTR_SECTION 60 /* 61 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring 62 * SDR1 here 63 */ 64 mfspr r3,SPRN_PTCR 65 std r3,_PTCR(r1) 66 mfspr r3,SPRN_LPCR 67 std r3,_LPCR(r1) 68FTR_SECTION_ELSE 69 mfspr r3,SPRN_SDR1 70 std r3,_SDR1(r1) 71ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) 72 mfspr r3,SPRN_RPR 73 std r3,_RPR(r1) 74 mfspr r3,SPRN_SPURR 75 std r3,_SPURR(r1) 76 mfspr r3,SPRN_PURR 77 std r3,_PURR(r1) 78 mfspr r3,SPRN_TSCR 79 std r3,_TSCR(r1) 80 mfspr r3,SPRN_DSCR 81 std r3,_DSCR(r1) 82 mfspr r3,SPRN_AMOR 83 std r3,_AMOR(r1) 84 mfspr r3,SPRN_WORT 85 std r3,_WORT(r1) 86 mfspr r3,SPRN_WORC 87 std r3,_WORC(r1) 88/* 89 * On POWER9, there are idle states such as stop4, invoked via cpuidle, 90 * that lose hypervisor resources. In such cases, we need to save 91 * additional SPRs before entering those idle states so that they can 92 * be restored to their older values on wakeup from the idle state. 93 * 94 * On POWER8, the only such deep idle state is winkle which is used 95 * only in the context of CPU-Hotplug, where these additional SPRs are 96 * reinitiazed to a sane value. Hence there is no need to save/restore 97 * these SPRs. 98 */ 99BEGIN_FTR_SECTION 100 blr 101END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) 102 103power9_save_additional_sprs: 104 mfspr r3, SPRN_PID 105 mfspr r4, SPRN_LDBAR 106 std r3, STOP_PID(r13) 107 std r4, STOP_LDBAR(r13) 108 109 mfspr r3, SPRN_FSCR 110 mfspr r4, SPRN_HFSCR 111 std r3, STOP_FSCR(r13) 112 std r4, STOP_HFSCR(r13) 113 114 mfspr r3, SPRN_MMCRA 115 mfspr r4, SPRN_MMCR0 116 std r3, STOP_MMCRA(r13) 117 std r4, _MMCR0(r1) 118 119 mfspr r3, SPRN_MMCR1 120 mfspr r4, SPRN_MMCR2 121 std r3, STOP_MMCR1(r13) 122 std r4, STOP_MMCR2(r13) 123 blr 124 125power9_restore_additional_sprs: 126 ld r3,_LPCR(r1) 127 ld r4, STOP_PID(r13) 128 mtspr SPRN_LPCR,r3 129 mtspr SPRN_PID, r4 130 131 ld r3, STOP_LDBAR(r13) 132 ld r4, STOP_FSCR(r13) 133 mtspr SPRN_LDBAR, r3 134 mtspr SPRN_FSCR, r4 135 136 ld r3, STOP_HFSCR(r13) 137 ld r4, STOP_MMCRA(r13) 138 mtspr SPRN_HFSCR, r3 139 mtspr SPRN_MMCRA, r4 140 141 ld r3, _MMCR0(r1) 142 ld r4, STOP_MMCR1(r13) 143 mtspr SPRN_MMCR0, r3 144 mtspr SPRN_MMCR1, r4 145 146 ld r3, STOP_MMCR2(r13) 147 ld r4, PACA_SPRG_VDSO(r13) 148 mtspr SPRN_MMCR2, r3 149 mtspr SPRN_SPRG3, r4 150 blr 151 152/* 153 * Used by threads when the lock bit of core_idle_state is set. 154 * Threads will spin in HMT_LOW until the lock bit is cleared. 155 * r14 - pointer to core_idle_state 156 * r15 - used to load contents of core_idle_state 157 * r9 - used as a temporary variable 158 */ 159 160core_idle_lock_held: 161 HMT_LOW 1623: lwz r15,0(r14) 163 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 164 bne 3b 165 HMT_MEDIUM 166 lwarx r15,0,r14 167 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 168 bne- core_idle_lock_held 169 blr 170 171/* 172 * Pass requested state in r3: 173 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8 174 * - Requested PSSCR value in POWER9 175 * 176 * Address of idle handler to branch to in realmode in r4 177 */ 178pnv_powersave_common: 179 /* Use r3 to pass state nap/sleep/winkle */ 180 /* NAP is a state loss, we create a regs frame on the 181 * stack, fill it up with the state we care about and 182 * stick a pointer to it in PACAR1. We really only 183 * need to save PC, some CR bits and the NV GPRs, 184 * but for now an interrupt frame will do. 185 */ 186 mtctr r4 187 188 mflr r0 189 std r0,16(r1) 190 stdu r1,-INT_FRAME_SIZE(r1) 191 std r0,_LINK(r1) 192 std r0,_NIP(r1) 193 194 /* We haven't lost state ... yet */ 195 li r0,0 196 stb r0,PACA_NAPSTATELOST(r13) 197 198 /* Continue saving state */ 199 SAVE_GPR(2, r1) 200 SAVE_NVGPRS(r1) 201 mfcr r5 202 std r5,_CCR(r1) 203 std r1,PACAR1(r13) 204 205BEGIN_FTR_SECTION 206 /* 207 * POWER9 does not require real mode to stop, and presently does not 208 * set hwthread_state for KVM (threads don't share MMU context), so 209 * we can remain in virtual mode for this. 210 */ 211 bctr 212END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) 213 /* 214 * POWER8 215 * Go to real mode to do the nap, as required by the architecture. 216 * Also, we need to be in real mode before setting hwthread_state, 217 * because as soon as we do that, another thread can switch 218 * the MMU context to the guest. 219 */ 220 LOAD_REG_IMMEDIATE(r7, MSR_IDLE) 221 mtmsrd r7,0 222 bctr 223 224/* 225 * This is the sequence required to execute idle instructions, as 226 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0. 227 */ 228#define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \ 229 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ 230 std r0,0(r1); \ 231 ptesync; \ 232 ld r0,0(r1); \ 233236: cmpd cr0,r0,r0; \ 234 bne 236b; \ 235 IDLE_INST; 236 237 238 .globl pnv_enter_arch207_idle_mode 239pnv_enter_arch207_idle_mode: 240#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 241 /* Tell KVM we're entering idle */ 242 li r4,KVM_HWTHREAD_IN_IDLE 243 /******************************************************/ 244 /* N O T E W E L L ! ! ! N O T E W E L L */ 245 /* The following store to HSTATE_HWTHREAD_STATE(r13) */ 246 /* MUST occur in real mode, i.e. with the MMU off, */ 247 /* and the MMU must stay off until we clear this flag */ 248 /* and test HSTATE_HWTHREAD_REQ(r13) in */ 249 /* pnv_powersave_wakeup in this file. */ 250 /* The reason is that another thread can switch the */ 251 /* MMU to a guest context whenever this flag is set */ 252 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ 253 /* that would potentially cause this thread to start */ 254 /* executing instructions from guest memory in */ 255 /* hypervisor mode, leading to a host crash or data */ 256 /* corruption, or worse. */ 257 /******************************************************/ 258 stb r4,HSTATE_HWTHREAD_STATE(r13) 259#endif 260 stb r3,PACA_THREAD_IDLE_STATE(r13) 261 cmpwi cr3,r3,PNV_THREAD_SLEEP 262 bge cr3,2f 263 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) 264 /* No return */ 2652: 266 /* Sleep or winkle */ 267 lbz r7,PACA_THREAD_MASK(r13) 268 ld r14,PACA_CORE_IDLE_STATE_PTR(r13) 269 li r5,0 270 beq cr3,3f 271 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h 2723: 273lwarx_loop1: 274 lwarx r15,0,r14 275 276 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 277 bnel- core_idle_lock_held 278 279 add r15,r15,r5 /* Add if winkle */ 280 andc r15,r15,r7 /* Clear thread bit */ 281 282 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS 283 284/* 285 * If cr0 = 0, then current thread is the last thread of the core entering 286 * sleep. Last thread needs to execute the hardware bug workaround code if 287 * required by the platform. 288 * Make the workaround call unconditionally here. The below branch call is 289 * patched out when the idle states are discovered if the platform does not 290 * require it. 291 */ 292.global pnv_fastsleep_workaround_at_entry 293pnv_fastsleep_workaround_at_entry: 294 beq fastsleep_workaround_at_entry 295 296 stwcx. r15,0,r14 297 bne- lwarx_loop1 298 isync 299 300common_enter: /* common code for all the threads entering sleep or winkle */ 301 bgt cr3,enter_winkle 302 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) 303 304fastsleep_workaround_at_entry: 305 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 306 stwcx. r15,0,r14 307 bne- lwarx_loop1 308 isync 309 310 /* Fast sleep workaround */ 311 li r3,1 312 li r4,1 313 bl opal_config_cpu_idle_state 314 315 /* Unlock */ 316 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 317 lwsync 318 stw r15,0(r14) 319 b common_enter 320 321enter_winkle: 322 bl save_sprs_to_stack 323 324 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) 325 326/* 327 * r3 - PSSCR value corresponding to the requested stop state. 328 */ 329power_enter_stop: 330/* 331 * Check if we are executing the lite variant with ESL=EC=0 332 */ 333 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED 334 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */ 335 bne .Lhandle_esl_ec_set 336 PPC_STOP 337 li r3,0 /* Since we didn't lose state, return 0 */ 338 std r3, PACA_REQ_PSSCR(r13) 339 340 /* 341 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so 342 * it can determine if the wakeup reason is an HMI in 343 * CHECK_HMI_INTERRUPT. 344 * 345 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup 346 * reason, so there is no point setting r12 to SRR1. 347 * 348 * Further, we clear r12 here, so that we don't accidentally enter the 349 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI. 350 */ 351 li r12, 0 352 b pnv_wakeup_noloss 353 354.Lhandle_esl_ec_set: 355BEGIN_FTR_SECTION 356 /* 357 * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after 358 * a state-loss idle. Saving and restoring MMCR0 over idle is a 359 * workaround. 360 */ 361 mfspr r4,SPRN_MMCR0 362 std r4,_MMCR0(r1) 363END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1) 364 365/* 366 * Check if the requested state is a deep idle state. 367 */ 368 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) 369 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) 370 cmpd r3,r4 371 bge .Lhandle_deep_stop 372 PPC_STOP /* Does not return (system reset interrupt) */ 373 374.Lhandle_deep_stop: 375/* 376 * Entering deep idle state. 377 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to 378 * stack and enter stop 379 */ 380 lbz r7,PACA_THREAD_MASK(r13) 381 ld r14,PACA_CORE_IDLE_STATE_PTR(r13) 382 383lwarx_loop_stop: 384 lwarx r15,0,r14 385 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 386 bnel- core_idle_lock_held 387 andc r15,r15,r7 /* Clear thread bit */ 388 389 stwcx. r15,0,r14 390 bne- lwarx_loop_stop 391 isync 392 393 bl save_sprs_to_stack 394 395 PPC_STOP /* Does not return (system reset interrupt) */ 396 397/* 398 * Entered with MSR[EE]=0 and no soft-masked interrupts pending. 399 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE). 400 */ 401_GLOBAL(power7_idle_insn) 402 /* Now check if user or arch enabled NAP mode */ 403 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode) 404 b pnv_powersave_common 405 406#define CHECK_HMI_INTERRUPT \ 407BEGIN_FTR_SECTION_NESTED(66); \ 408 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \ 409FTR_SECTION_ELSE_NESTED(66); \ 410 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \ 411ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ 412 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \ 413 bne+ 20f; \ 414 /* Invoke opal call to handle hmi */ \ 415 ld r2,PACATOC(r13); \ 416 ld r1,PACAR1(r13); \ 417 std r3,ORIG_GPR3(r1); /* Save original r3 */ \ 418 li r3,0; /* NULL argument */ \ 419 bl hmi_exception_realmode; \ 420 nop; \ 421 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \ 42220: nop; 423 424/* 425 * Entered with MSR[EE]=0 and no soft-masked interrupts pending. 426 * r3 contains desired PSSCR register value. 427 * 428 * Offline (CPU unplug) case also must notify KVM that the CPU is 429 * idle. 430 */ 431_GLOBAL(power9_offline_stop) 432#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 433 /* 434 * Tell KVM we're entering idle. 435 * This does not have to be done in real mode because the P9 MMU 436 * is independent per-thread. Some steppings share radix/hash mode 437 * between threads, but in that case KVM has a barrier sync in real 438 * mode before and after switching between radix and hash. 439 */ 440 li r4,KVM_HWTHREAD_IN_IDLE 441 stb r4,HSTATE_HWTHREAD_STATE(r13) 442#endif 443 /* fall through */ 444 445_GLOBAL(power9_idle_stop) 446 std r3, PACA_REQ_PSSCR(r13) 447#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 448BEGIN_FTR_SECTION 449 sync 450 lwz r5, PACA_DONT_STOP(r13) 451 cmpwi r5, 0 452 bne 1f 453END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG) 454#endif 455 mtspr SPRN_PSSCR,r3 456 LOAD_REG_ADDR(r4,power_enter_stop) 457 b pnv_powersave_common 458 /* No return */ 459#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 4601: 461 /* 462 * We get here when TM / thread reconfiguration bug workaround 463 * code wants to get the CPU into SMT4 mode, and therefore 464 * we are being asked not to stop. 465 */ 466 li r3, 0 467 std r3, PACA_REQ_PSSCR(r13) 468 blr /* return 0 for wakeup cause / SRR1 value */ 469#endif 470 471/* 472 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1, 473 * HSPRG0 will be set to the HSPRG0 value of one of the 474 * threads in this core. Thus the value we have in r13 475 * may not be this thread's paca pointer. 476 * 477 * Fortunately, the TIR remains invariant. Since this thread's 478 * paca pointer is recorded in all its sibling's paca, we can 479 * correctly recover this thread's paca pointer if we 480 * know the index of this thread in the core. 481 * 482 * This index can be obtained from the TIR. 483 * 484 * i.e, thread's position in the core = TIR. 485 * If this value is i, then this thread's paca is 486 * paca->thread_sibling_pacas[i]. 487 */ 488power9_dd1_recover_paca: 489 mfspr r4, SPRN_TIR 490 /* 491 * Since each entry in thread_sibling_pacas is 8 bytes 492 * we need to left-shift by 3 bits. Thus r4 = i * 8 493 */ 494 sldi r4, r4, 3 495 /* Get &paca->thread_sibling_pacas[0] in r5 */ 496 ld r5, PACA_SIBLING_PACA_PTRS(r13) 497 /* Load paca->thread_sibling_pacas[i] into r13 */ 498 ldx r13, r4, r5 499 SET_PACA(r13) 500 /* 501 * Indicate that we have lost NVGPR state 502 * which needs to be restored from the stack. 503 */ 504 li r3, 1 505 stb r3,PACA_NAPSTATELOST(r13) 506 blr 507 508/* 509 * Called from machine check handler for powersave wakeups. 510 * Low level machine check processing has already been done. Now just 511 * go through the wake up path to get everything in order. 512 * 513 * r3 - The original SRR1 value. 514 * Original SRR[01] have been clobbered. 515 * MSR_RI is clear. 516 */ 517.global pnv_powersave_wakeup_mce 518pnv_powersave_wakeup_mce: 519 /* Set cr3 for pnv_powersave_wakeup */ 520 rlwinm r11,r3,47-31,30,31 521 cmpwi cr3,r11,2 522 523 /* 524 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake 525 * reason into r12, which allows reuse of the system reset wakeup 526 * code without being mistaken for another type of wakeup. 527 */ 528 oris r12,r3,SRR1_WAKEMCE_RESVD@h 529 530 b pnv_powersave_wakeup 531 532/* 533 * Called from reset vector for powersave wakeups. 534 * cr3 - set to gt if waking up with partial/complete hypervisor state loss 535 * r12 - SRR1 536 */ 537.global pnv_powersave_wakeup 538pnv_powersave_wakeup: 539 ld r2, PACATOC(r13) 540 541BEGIN_FTR_SECTION 542BEGIN_FTR_SECTION_NESTED(70) 543 bl power9_dd1_recover_paca 544END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70) 545 bl pnv_restore_hyp_resource_arch300 546FTR_SECTION_ELSE 547 bl pnv_restore_hyp_resource_arch207 548ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) 549 550 li r0,PNV_THREAD_RUNNING 551 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ 552 553 mr r3,r12 554 555#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 556 lbz r0,HSTATE_HWTHREAD_STATE(r13) 557 cmpwi r0,KVM_HWTHREAD_IN_KERNEL 558 beq 0f 559 li r0,KVM_HWTHREAD_IN_KERNEL 560 stb r0,HSTATE_HWTHREAD_STATE(r13) 561 /* Order setting hwthread_state vs. testing hwthread_req */ 562 sync 5630: lbz r0,HSTATE_HWTHREAD_REQ(r13) 564 cmpwi r0,0 565 beq 1f 566 b kvm_start_guest 5671: 568#endif 569 570 /* Return SRR1 from power7_nap() */ 571 blt cr3,pnv_wakeup_noloss 572 b pnv_wakeup_loss 573 574/* 575 * Check whether we have woken up with hypervisor state loss. 576 * If yes, restore hypervisor state and return back to link. 577 * 578 * cr3 - set to gt if waking up with partial/complete hypervisor state loss 579 */ 580pnv_restore_hyp_resource_arch300: 581 /* 582 * Workaround for POWER9, if we lost resources, the ERAT 583 * might have been mixed up and needs flushing. We also need 584 * to reload MMCR0 (see comment above). We also need to set 585 * then clear bit 60 in MMCRA to ensure the PMU starts running. 586 */ 587 blt cr3,1f 588BEGIN_FTR_SECTION 589 PPC_INVALIDATE_ERAT 590 ld r1,PACAR1(r13) 591 ld r4,_MMCR0(r1) 592 mtspr SPRN_MMCR0,r4 593END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1) 594 mfspr r4,SPRN_MMCRA 595 ori r4,r4,(1 << (63-60)) 596 mtspr SPRN_MMCRA,r4 597 xori r4,r4,(1 << (63-60)) 598 mtspr SPRN_MMCRA,r4 5991: 600 /* 601 * POWER ISA 3. Use PSSCR to determine if we 602 * are waking up from deep idle state 603 */ 604 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) 605 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) 606 607BEGIN_FTR_SECTION_NESTED(71) 608 /* 609 * Assume that we are waking up from the state 610 * same as the Requested Level (RL) in the PSSCR 611 * which are Bits 60-63 612 */ 613 ld r5,PACA_REQ_PSSCR(r13) 614 rldicl r5,r5,0,60 615FTR_SECTION_ELSE_NESTED(71) 616 /* 617 * 0-3 bits correspond to Power-Saving Level Status 618 * which indicates the idle state we are waking up from 619 */ 620 mfspr r5, SPRN_PSSCR 621 rldicl r5,r5,4,60 622ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71) 623 li r0, 0 /* clear requested_psscr to say we're awake */ 624 std r0, PACA_REQ_PSSCR(r13) 625 cmpd cr4,r5,r4 626 bge cr4,pnv_wakeup_tb_loss /* returns to caller */ 627 628 blr /* Waking up without hypervisor state loss. */ 629 630/* Same calling convention as arch300 */ 631pnv_restore_hyp_resource_arch207: 632 /* 633 * POWER ISA 2.07 or less. 634 * Check if we slept with sleep or winkle. 635 */ 636 lbz r4,PACA_THREAD_IDLE_STATE(r13) 637 cmpwi cr2,r4,PNV_THREAD_NAP 638 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */ 639 640 /* 641 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking 642 * up from nap. At this stage CR3 shouldn't contains 'gt' since that 643 * indicates we are waking with hypervisor state loss from nap. 644 */ 645 bgt cr3,. 646 647 blr /* Waking up without hypervisor state loss */ 648 649/* 650 * Called if waking up from idle state which can cause either partial or 651 * complete hyp state loss. 652 * In POWER8, called if waking up from fastsleep or winkle 653 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state 654 * 655 * r13 - PACA 656 * cr3 - gt if waking up with partial/complete hypervisor state loss 657 * 658 * If ISA300: 659 * cr4 - gt or eq if waking up from complete hypervisor state loss. 660 * 661 * If ISA207: 662 * r4 - PACA_THREAD_IDLE_STATE 663 */ 664pnv_wakeup_tb_loss: 665 ld r1,PACAR1(r13) 666 /* 667 * Before entering any idle state, the NVGPRs are saved in the stack. 668 * If there was a state loss, or PACA_NAPSTATELOST was set, then the 669 * NVGPRs are restored. If we are here, it is likely that state is lost, 670 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach 671 * here are the same as the test to restore NVGPRS: 672 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300, 673 * and SRR1 test for restoring NVGPRs. 674 * 675 * We are about to clobber NVGPRs now, so set NAPSTATELOST to 676 * guarantee they will always be restored. This might be tightened 677 * with careful reading of specs (particularly for ISA300) but this 678 * is already a slow wakeup path and it's simpler to be safe. 679 */ 680 li r0,1 681 stb r0,PACA_NAPSTATELOST(r13) 682 683 /* 684 * 685 * Save SRR1 and LR in NVGPRs as they might be clobbered in 686 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required 687 * to determine the wakeup reason if we branch to kvm_start_guest. LR 688 * is required to return back to reset vector after hypervisor state 689 * restore is complete. 690 */ 691 mr r19,r12 692 mr r18,r4 693 mflr r17 694BEGIN_FTR_SECTION 695 CHECK_HMI_INTERRUPT 696END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 697 698 ld r14,PACA_CORE_IDLE_STATE_PTR(r13) 699 lbz r7,PACA_THREAD_MASK(r13) 700 701 /* 702 * Take the core lock to synchronize against other threads. 703 * 704 * Lock bit is set in one of the 2 cases- 705 * a. In the sleep/winkle enter path, the last thread is executing 706 * fastsleep workaround code. 707 * b. In the wake up path, another thread is executing fastsleep 708 * workaround undo code or resyncing timebase or restoring context 709 * In either case loop until the lock bit is cleared. 710 */ 7111: 712 lwarx r15,0,r14 713 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 714 bnel- core_idle_lock_held 715 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 716 stwcx. r15,0,r14 717 bne- 1b 718 isync 719 720 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS 721 cmpwi cr2,r9,0 722 723 /* 724 * At this stage 725 * cr2 - eq if first thread to wakeup in core 726 * cr3- gt if waking up with partial/complete hypervisor state loss 727 * ISA300: 728 * cr4 - gt or eq if waking up from complete hypervisor state loss. 729 */ 730 731BEGIN_FTR_SECTION 732 /* 733 * Were we in winkle? 734 * If yes, check if all threads were in winkle, decrement our 735 * winkle count, set all thread winkle bits if all were in winkle. 736 * Check if our thread has a winkle bit set, and set cr4 accordingly 737 * (to match ISA300, above). Pseudo-code for core idle state 738 * transitions for ISA207 is as follows (everything happens atomically 739 * due to store conditional and/or lock bit): 740 * 741 * nap_idle() { } 742 * nap_wake() { } 743 * 744 * sleep_idle() 745 * { 746 * core_idle_state &= ~thread_in_core 747 * } 748 * 749 * sleep_wake() 750 * { 751 * bool first_in_core, first_in_subcore; 752 * 753 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; 754 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; 755 * 756 * core_idle_state |= thread_in_core; 757 * } 758 * 759 * winkle_idle() 760 * { 761 * core_idle_state &= ~thread_in_core; 762 * core_idle_state += 1 << WINKLE_COUNT_SHIFT; 763 * } 764 * 765 * winkle_wake() 766 * { 767 * bool first_in_core, first_in_subcore, winkle_state_lost; 768 * 769 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; 770 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; 771 * 772 * core_idle_state |= thread_in_core; 773 * 774 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT)) 775 * core_idle_state |= THREAD_WINKLE_BITS; 776 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT; 777 * 778 * winkle_state_lost = core_idle_state & 779 * (thread_in_core << WINKLE_THREAD_SHIFT); 780 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT); 781 * } 782 * 783 */ 784 cmpwi r18,PNV_THREAD_WINKLE 785 bne 2f 786 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h 787 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h 788 beq 2f 789 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */ 7902: 791 /* Shift thread bit to winkle mask, then test if this thread is set, 792 * and remove it from the winkle bits */ 793 slwi r8,r7,8 794 and r8,r8,r15 795 andc r15,r15,r8 796 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */ 797 798 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13) 799 and r4,r4,r15 800 cmpwi r4,0 /* Check if first in subcore */ 801 802 or r15,r15,r7 /* Set thread bit */ 803 beq first_thread_in_subcore 804END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) 805 806 or r15,r15,r7 /* Set thread bit */ 807 beq cr2,first_thread_in_core 808 809 /* Not first thread in core or subcore to wake up */ 810 b clear_lock 811 812first_thread_in_subcore: 813 /* 814 * If waking up from sleep, subcore state is not lost. Hence 815 * skip subcore state restore 816 */ 817 blt cr4,subcore_state_restored 818 819 /* Restore per-subcore state */ 820 ld r4,_SDR1(r1) 821 mtspr SPRN_SDR1,r4 822 823 ld r4,_RPR(r1) 824 mtspr SPRN_RPR,r4 825 ld r4,_AMOR(r1) 826 mtspr SPRN_AMOR,r4 827 828subcore_state_restored: 829 /* 830 * Check if the thread is also the first thread in the core. If not, 831 * skip to clear_lock. 832 */ 833 bne cr2,clear_lock 834 835first_thread_in_core: 836 837 /* 838 * First thread in the core waking up from any state which can cause 839 * partial or complete hypervisor state loss. It needs to 840 * call the fastsleep workaround code if the platform requires it. 841 * Call it unconditionally here. The below branch instruction will 842 * be patched out if the platform does not have fastsleep or does not 843 * require the workaround. Patching will be performed during the 844 * discovery of idle-states. 845 */ 846.global pnv_fastsleep_workaround_at_exit 847pnv_fastsleep_workaround_at_exit: 848 b fastsleep_workaround_at_exit 849 850timebase_resync: 851 /* 852 * Use cr3 which indicates that we are waking up with atleast partial 853 * hypervisor state loss to determine if TIMEBASE RESYNC is needed. 854 */ 855 ble cr3,.Ltb_resynced 856 /* Time base re-sync */ 857 bl opal_resync_timebase; 858 /* 859 * If waking up from sleep (POWER8), per core state 860 * is not lost, skip to clear_lock. 861 */ 862.Ltb_resynced: 863 blt cr4,clear_lock 864 865 /* 866 * First thread in the core to wake up and its waking up with 867 * complete hypervisor state loss. Restore per core hypervisor 868 * state. 869 */ 870BEGIN_FTR_SECTION 871 ld r4,_PTCR(r1) 872 mtspr SPRN_PTCR,r4 873 ld r4,_RPR(r1) 874 mtspr SPRN_RPR,r4 875 ld r4,_AMOR(r1) 876 mtspr SPRN_AMOR,r4 877END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) 878 879 ld r4,_TSCR(r1) 880 mtspr SPRN_TSCR,r4 881 ld r4,_WORC(r1) 882 mtspr SPRN_WORC,r4 883 884clear_lock: 885 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 886 lwsync 887 stw r15,0(r14) 888 889common_exit: 890 /* 891 * Common to all threads. 892 * 893 * If waking up from sleep, hypervisor state is not lost. Hence 894 * skip hypervisor state restore. 895 */ 896 blt cr4,hypervisor_state_restored 897 898 /* Waking up from winkle */ 899 900BEGIN_MMU_FTR_SECTION 901 b no_segments 902END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) 903 /* Restore SLB from PACA */ 904 ld r8,PACA_SLBSHADOWPTR(r13) 905 906 .rept SLB_NUM_BOLTED 907 li r3, SLBSHADOW_SAVEAREA 908 LDX_BE r5, r8, r3 909 addi r3, r3, 8 910 LDX_BE r6, r8, r3 911 andis. r7,r5,SLB_ESID_V@h 912 beq 1f 913 slbmte r6,r5 9141: addi r8,r8,16 915 .endr 916no_segments: 917 918 /* Restore per thread state */ 919 920 ld r4,_SPURR(r1) 921 mtspr SPRN_SPURR,r4 922 ld r4,_PURR(r1) 923 mtspr SPRN_PURR,r4 924 ld r4,_DSCR(r1) 925 mtspr SPRN_DSCR,r4 926 ld r4,_WORT(r1) 927 mtspr SPRN_WORT,r4 928 929 /* Call cur_cpu_spec->cpu_restore() */ 930 LOAD_REG_ADDR(r4, cur_cpu_spec) 931 ld r4,0(r4) 932 ld r12,CPU_SPEC_RESTORE(r4) 933#ifdef PPC64_ELF_ABI_v1 934 ld r12,0(r12) 935#endif 936 mtctr r12 937 bctrl 938 939/* 940 * On POWER9, we can come here on wakeup from a cpuidle stop state. 941 * Hence restore the additional SPRs to the saved value. 942 * 943 * On POWER8, we come here only on winkle. Since winkle is used 944 * only in the case of CPU-Hotplug, we don't need to restore 945 * the additional SPRs. 946 */ 947BEGIN_FTR_SECTION 948 bl power9_restore_additional_sprs 949END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) 950hypervisor_state_restored: 951 952 mr r12,r19 953 mtlr r17 954 blr /* return to pnv_powersave_wakeup */ 955 956fastsleep_workaround_at_exit: 957 li r3,1 958 li r4,0 959 bl opal_config_cpu_idle_state 960 b timebase_resync 961 962/* 963 * R3 here contains the value that will be returned to the caller 964 * of power7_nap. 965 * R12 contains SRR1 for CHECK_HMI_INTERRUPT. 966 */ 967.global pnv_wakeup_loss 968pnv_wakeup_loss: 969 ld r1,PACAR1(r13) 970BEGIN_FTR_SECTION 971 CHECK_HMI_INTERRUPT 972END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 973 REST_NVGPRS(r1) 974 REST_GPR(2, r1) 975 ld r4,PACAKMSR(r13) 976 ld r5,_LINK(r1) 977 ld r6,_CCR(r1) 978 addi r1,r1,INT_FRAME_SIZE 979 mtlr r5 980 mtcr r6 981 mtmsrd r4 982 blr 983 984/* 985 * R3 here contains the value that will be returned to the caller 986 * of power7_nap. 987 * R12 contains SRR1 for CHECK_HMI_INTERRUPT. 988 */ 989pnv_wakeup_noloss: 990 lbz r0,PACA_NAPSTATELOST(r13) 991 cmpwi r0,0 992 bne pnv_wakeup_loss 993 ld r1,PACAR1(r13) 994BEGIN_FTR_SECTION 995 CHECK_HMI_INTERRUPT 996END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 997 ld r4,PACAKMSR(r13) 998 ld r5,_NIP(r1) 999 ld r6,_CCR(r1) 1000 addi r1,r1,INT_FRAME_SIZE 1001 mtlr r5 1002 mtcr r6 1003 mtmsrd r4 1004 blr 1005