12874c5fdSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-or-later */ 214cf11afSPaul Mackerras/* 314cf11afSPaul Mackerras * Kernel execution entry point code. 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 614cf11afSPaul Mackerras * Initial PowerPC version. 714cf11afSPaul Mackerras * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 814cf11afSPaul Mackerras * Rewritten for PReP 914cf11afSPaul Mackerras * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 1014cf11afSPaul Mackerras * Low-level exception handers, MMU support, and rewrite. 1114cf11afSPaul Mackerras * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 1214cf11afSPaul Mackerras * PowerPC 8xx modifications. 1314cf11afSPaul Mackerras * Copyright (c) 1998-1999 TiVo, Inc. 1414cf11afSPaul Mackerras * PowerPC 403GCX modifications. 1514cf11afSPaul Mackerras * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 1614cf11afSPaul Mackerras * PowerPC 403GCX/405GP modifications. 1714cf11afSPaul Mackerras * Copyright 2000 MontaVista Software Inc. 1814cf11afSPaul Mackerras * PPC405 modifications 1914cf11afSPaul Mackerras * PowerPC 403GCX/405GP modifications. 2014cf11afSPaul Mackerras * Author: MontaVista Software, Inc. 2114cf11afSPaul Mackerras * frank_rowand@mvista.com or source@mvista.com 2214cf11afSPaul Mackerras * debbie_chu@mvista.com 2314cf11afSPaul Mackerras * Copyright 2002-2005 MontaVista Software, Inc. 2414cf11afSPaul Mackerras * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 2514cf11afSPaul Mackerras */ 2614cf11afSPaul Mackerras 27e7039845STim Abbott#include <linux/init.h> 2865fddcfcSMike Rapoport#include <linux/pgtable.h> 2914cf11afSPaul Mackerras#include <asm/processor.h> 3014cf11afSPaul Mackerras#include <asm/page.h> 3114cf11afSPaul Mackerras#include <asm/mmu.h> 3214cf11afSPaul Mackerras#include <asm/cputable.h> 3314cf11afSPaul Mackerras#include <asm/thread_info.h> 3414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 3514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 3646f52210SStephen Rothwell#include <asm/ptrace.h> 37e7f75ad0SDave Kleikamp#include <asm/synch.h> 389445aa1aSAl Viro#include <asm/export.h> 396c16816bSChristophe Leroy#include <asm/code-patching-asm.h> 4014cf11afSPaul Mackerras#include "head_booke.h" 4114cf11afSPaul Mackerras 4214cf11afSPaul Mackerras 4314cf11afSPaul Mackerras/* As with the other PowerPC ports, it is expected that when code 4414cf11afSPaul Mackerras * execution begins here, the following registers contain valid, yet 4514cf11afSPaul Mackerras * optional, information: 4614cf11afSPaul Mackerras * 4714cf11afSPaul Mackerras * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 4814cf11afSPaul Mackerras * r4 - Starting address of the init RAM disk 4914cf11afSPaul Mackerras * r5 - Ending address of the init RAM disk 5014cf11afSPaul Mackerras * r6 - Start of kernel command line string (e.g. "mem=128") 5114cf11afSPaul Mackerras * r7 - End of kernel command line string 5214cf11afSPaul Mackerras * 5314cf11afSPaul Mackerras */ 54e7039845STim Abbott __HEAD 55748a7683SKumar Gala_ENTRY(_stext); 56748a7683SKumar Gala_ENTRY(_start); 5714cf11afSPaul Mackerras /* 5814cf11afSPaul Mackerras * Reserve a word at a fixed location to store the address 5914cf11afSPaul Mackerras * of abatron_pteptrs 6014cf11afSPaul Mackerras */ 6114cf11afSPaul Mackerras nop 626dece0ebSScott Wood mr r31,r3 /* save device tree ptr */ 6314cf11afSPaul Mackerras li r24,0 /* CPU number */ 6414cf11afSPaul Mackerras 6526ecb6c4SSuzuki Poulose#ifdef CONFIG_RELOCATABLE 6626ecb6c4SSuzuki Poulose/* 6726ecb6c4SSuzuki Poulose * Relocate ourselves to the current runtime address. 6826ecb6c4SSuzuki Poulose * This is called only by the Boot CPU. 6926ecb6c4SSuzuki Poulose * "relocate" is called with our current runtime virutal 7026ecb6c4SSuzuki Poulose * address. 7126ecb6c4SSuzuki Poulose * r21 will be loaded with the physical runtime address of _stext 7226ecb6c4SSuzuki Poulose */ 7326ecb6c4SSuzuki Poulose bl 0f /* Get our runtime address */ 7426ecb6c4SSuzuki Poulose0: mflr r21 /* Make it accessible */ 7526ecb6c4SSuzuki Poulose addis r21,r21,(_stext - 0b)@ha 7626ecb6c4SSuzuki Poulose addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */ 7726ecb6c4SSuzuki Poulose 7826ecb6c4SSuzuki Poulose /* 7926ecb6c4SSuzuki Poulose * We have the runtime (virutal) address of our base. 8026ecb6c4SSuzuki Poulose * We calculate our shift of offset from a 256M page. 8126ecb6c4SSuzuki Poulose * We could map the 256M page we belong to at PAGE_OFFSET and 8226ecb6c4SSuzuki Poulose * get going from there. 8326ecb6c4SSuzuki Poulose */ 8426ecb6c4SSuzuki Poulose lis r4,KERNELBASE@h 8526ecb6c4SSuzuki Poulose ori r4,r4,KERNELBASE@l 8626ecb6c4SSuzuki Poulose rlwinm r6,r21,0,4,31 /* r6 = PHYS_START % 256M */ 8726ecb6c4SSuzuki Poulose rlwinm r5,r4,0,4,31 /* r5 = KERNELBASE % 256M */ 8826ecb6c4SSuzuki Poulose subf r3,r5,r6 /* r3 = r6 - r5 */ 8926ecb6c4SSuzuki Poulose add r3,r4,r3 /* Required Virutal Address */ 9026ecb6c4SSuzuki Poulose 9126ecb6c4SSuzuki Poulose bl relocate 9226ecb6c4SSuzuki Poulose#endif 9326ecb6c4SSuzuki Poulose 94795033c3SDave Kleikamp bl init_cpu_state 9514cf11afSPaul Mackerras 9614cf11afSPaul Mackerras /* 9714cf11afSPaul Mackerras * This is where the main kernel code starts. 9814cf11afSPaul Mackerras */ 9914cf11afSPaul Mackerras 10014cf11afSPaul Mackerras /* ptr to current */ 10114cf11afSPaul Mackerras lis r2,init_task@h 10214cf11afSPaul Mackerras ori r2,r2,init_task@l 10314cf11afSPaul Mackerras 10414cf11afSPaul Mackerras /* ptr to current thread */ 10514cf11afSPaul Mackerras addi r4,r2,THREAD /* init task's THREAD */ 106ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_THREAD,r4 10714cf11afSPaul Mackerras 10814cf11afSPaul Mackerras /* stack */ 10914cf11afSPaul Mackerras lis r1,init_thread_union@h 11014cf11afSPaul Mackerras ori r1,r1,init_thread_union@l 11114cf11afSPaul Mackerras li r0,0 11214cf11afSPaul Mackerras stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 11314cf11afSPaul Mackerras 11414cf11afSPaul Mackerras bl early_init 11514cf11afSPaul Mackerras 11626ecb6c4SSuzuki Poulose#ifdef CONFIG_RELOCATABLE 11726ecb6c4SSuzuki Poulose /* 11826ecb6c4SSuzuki Poulose * Relocatable kernel support based on processing of dynamic 11926ecb6c4SSuzuki Poulose * relocation entries. 12026ecb6c4SSuzuki Poulose * 12126ecb6c4SSuzuki Poulose * r25 will contain RPN/ERPN for the start address of memory 12226ecb6c4SSuzuki Poulose * r21 will contain the current offset of _stext 12326ecb6c4SSuzuki Poulose */ 12426ecb6c4SSuzuki Poulose lis r3,kernstart_addr@ha 12526ecb6c4SSuzuki Poulose la r3,kernstart_addr@l(r3) 12626ecb6c4SSuzuki Poulose 12726ecb6c4SSuzuki Poulose /* 12826ecb6c4SSuzuki Poulose * Compute the kernstart_addr. 12926ecb6c4SSuzuki Poulose * kernstart_addr => (r6,r8) 13026ecb6c4SSuzuki Poulose * kernstart_addr & ~0xfffffff => (r6,r7) 13126ecb6c4SSuzuki Poulose */ 13226ecb6c4SSuzuki Poulose rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */ 13326ecb6c4SSuzuki Poulose rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */ 13426ecb6c4SSuzuki Poulose rlwinm r8,r21,0,4,31 /* r8 = (_stext & 0xfffffff) */ 13526ecb6c4SSuzuki Poulose or r8,r7,r8 /* Compute the lower 32bit of kernstart_addr */ 13626ecb6c4SSuzuki Poulose 13726ecb6c4SSuzuki Poulose /* Store kernstart_addr */ 13826ecb6c4SSuzuki Poulose stw r6,0(r3) /* higher 32bit */ 13926ecb6c4SSuzuki Poulose stw r8,4(r3) /* lower 32bit */ 14026ecb6c4SSuzuki Poulose 14126ecb6c4SSuzuki Poulose /* 14226ecb6c4SSuzuki Poulose * Compute the virt_phys_offset : 14326ecb6c4SSuzuki Poulose * virt_phys_offset = stext.run - kernstart_addr 14426ecb6c4SSuzuki Poulose * 14526ecb6c4SSuzuki Poulose * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff) 14626ecb6c4SSuzuki Poulose * When we relocate, we have : 14726ecb6c4SSuzuki Poulose * 14826ecb6c4SSuzuki Poulose * (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff) 14926ecb6c4SSuzuki Poulose * 15026ecb6c4SSuzuki Poulose * hence: 15126ecb6c4SSuzuki Poulose * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff) 15226ecb6c4SSuzuki Poulose * 15326ecb6c4SSuzuki Poulose */ 15426ecb6c4SSuzuki Poulose 15526ecb6c4SSuzuki Poulose /* KERNELBASE&~0xfffffff => (r4,r5) */ 15626ecb6c4SSuzuki Poulose li r4, 0 /* higer 32bit */ 15726ecb6c4SSuzuki Poulose lis r5,KERNELBASE@h 15826ecb6c4SSuzuki Poulose rlwinm r5,r5,0,0,3 /* Align to 256M, lower 32bit */ 15926ecb6c4SSuzuki Poulose 16026ecb6c4SSuzuki Poulose /* 16126ecb6c4SSuzuki Poulose * 64bit subtraction. 16226ecb6c4SSuzuki Poulose */ 16326ecb6c4SSuzuki Poulose subfc r5,r7,r5 16426ecb6c4SSuzuki Poulose subfe r4,r6,r4 16526ecb6c4SSuzuki Poulose 16626ecb6c4SSuzuki Poulose /* Store virt_phys_offset */ 16726ecb6c4SSuzuki Poulose lis r3,virt_phys_offset@ha 16826ecb6c4SSuzuki Poulose la r3,virt_phys_offset@l(r3) 16926ecb6c4SSuzuki Poulose 17026ecb6c4SSuzuki Poulose stw r4,0(r3) 17126ecb6c4SSuzuki Poulose stw r5,4(r3) 17226ecb6c4SSuzuki Poulose 17326ecb6c4SSuzuki Poulose#elif defined(CONFIG_DYNAMIC_MEMSTART) 1749661534dSDave Kleikamp /* 1750f890c8dSSuzuki Poulose * Mapping based, page aligned dynamic kernel loading. 1760f890c8dSSuzuki Poulose * 1779661534dSDave Kleikamp * r25 will contain RPN/ERPN for the start address of memory 1789661534dSDave Kleikamp * 1799661534dSDave Kleikamp * Add the difference between KERNELBASE and PAGE_OFFSET to the 1809661534dSDave Kleikamp * start of physical memory to get kernstart_addr. 1819661534dSDave Kleikamp */ 1829661534dSDave Kleikamp lis r3,kernstart_addr@ha 1839661534dSDave Kleikamp la r3,kernstart_addr@l(r3) 1849661534dSDave Kleikamp 1859661534dSDave Kleikamp lis r4,KERNELBASE@h 1869661534dSDave Kleikamp ori r4,r4,KERNELBASE@l 1879661534dSDave Kleikamp lis r5,PAGE_OFFSET@h 1889661534dSDave Kleikamp ori r5,r5,PAGE_OFFSET@l 1899661534dSDave Kleikamp subf r4,r5,r4 1909661534dSDave Kleikamp 1919661534dSDave Kleikamp rlwinm r6,r25,0,28,31 /* ERPN */ 1929661534dSDave Kleikamp rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */ 1939661534dSDave Kleikamp add r7,r7,r4 1949661534dSDave Kleikamp 1959661534dSDave Kleikamp stw r6,0(r3) 1969661534dSDave Kleikamp stw r7,4(r3) 1979661534dSDave Kleikamp#endif 1989661534dSDave Kleikamp 19914cf11afSPaul Mackerras/* 20014cf11afSPaul Mackerras * Decide what sort of machine this is and initialize the MMU. 20114cf11afSPaul Mackerras */ 2022edb16efSChristophe Leroy#ifdef CONFIG_KASAN 2032edb16efSChristophe Leroy bl kasan_early_init 2042edb16efSChristophe Leroy#endif 2056dece0ebSScott Wood li r3,0 2066dece0ebSScott Wood mr r4,r31 20714cf11afSPaul Mackerras bl machine_init 20814cf11afSPaul Mackerras bl MMU_init 20914cf11afSPaul Mackerras 21014cf11afSPaul Mackerras /* Setup PTE pointers for the Abatron bdiGDB */ 21114cf11afSPaul Mackerras lis r6, swapper_pg_dir@h 21214cf11afSPaul Mackerras ori r6, r6, swapper_pg_dir@l 21314cf11afSPaul Mackerras lis r5, abatron_pteptrs@h 21414cf11afSPaul Mackerras ori r5, r5, abatron_pteptrs@l 21514cf11afSPaul Mackerras lis r4, KERNELBASE@h 21614cf11afSPaul Mackerras ori r4, r4, KERNELBASE@l 21714cf11afSPaul Mackerras stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ 21814cf11afSPaul Mackerras stw r6, 0(r5) 21914cf11afSPaul Mackerras 220029b8f66SDave Kleikamp /* Clear the Machine Check Syndrome Register */ 221029b8f66SDave Kleikamp li r0,0 222029b8f66SDave Kleikamp mtspr SPRN_MCSR,r0 223029b8f66SDave Kleikamp 22414cf11afSPaul Mackerras /* Let's move on */ 22514cf11afSPaul Mackerras lis r4,start_kernel@h 22614cf11afSPaul Mackerras ori r4,r4,start_kernel@l 22714cf11afSPaul Mackerras lis r3,MSR_KERNEL@h 22814cf11afSPaul Mackerras ori r3,r3,MSR_KERNEL@l 22914cf11afSPaul Mackerras mtspr SPRN_SRR0,r4 23014cf11afSPaul Mackerras mtspr SPRN_SRR1,r3 23114cf11afSPaul Mackerras rfi /* change context and jump to start_kernel */ 23214cf11afSPaul Mackerras 23314cf11afSPaul Mackerras/* 23414cf11afSPaul Mackerras * Interrupt vector entry code 23514cf11afSPaul Mackerras * 23614cf11afSPaul Mackerras * The Book E MMUs are always on so we don't need to handle 23714cf11afSPaul Mackerras * interrupts in real mode as with previous PPC processors. In 23814cf11afSPaul Mackerras * this case we handle interrupts in the kernel virtual address 23914cf11afSPaul Mackerras * space. 24014cf11afSPaul Mackerras * 24114cf11afSPaul Mackerras * Interrupt vectors are dynamically placed relative to the 24214cf11afSPaul Mackerras * interrupt prefix as determined by the address of interrupt_base. 24314cf11afSPaul Mackerras * The interrupt vectors offsets are programmed using the labels 24414cf11afSPaul Mackerras * for each interrupt vector entry. 24514cf11afSPaul Mackerras * 24614cf11afSPaul Mackerras * Interrupt vectors must be aligned on a 16 byte boundary. 24714cf11afSPaul Mackerras * We align on a 32 byte cache line boundary for good measure. 24814cf11afSPaul Mackerras */ 24914cf11afSPaul Mackerras 25014cf11afSPaul Mackerrasinterrupt_base: 25114cf11afSPaul Mackerras /* Critical Input Interrupt */ 252cfac5784SScott Wood CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) 25314cf11afSPaul Mackerras 25414cf11afSPaul Mackerras /* Machine Check Interrupt */ 255cfac5784SScott Wood CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \ 256cfac5784SScott Wood machine_check_exception) 25747c0bd1aSBenjamin Herrenschmidt MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception) 25814cf11afSPaul Mackerras 25914cf11afSPaul Mackerras /* Data Storage Interrupt */ 2601bc54c03SBenjamin Herrenschmidt DATA_STORAGE_EXCEPTION 26114cf11afSPaul Mackerras 26214cf11afSPaul Mackerras /* Instruction Storage Interrupt */ 26314cf11afSPaul Mackerras INSTRUCTION_STORAGE_EXCEPTION 26414cf11afSPaul Mackerras 26514cf11afSPaul Mackerras /* External Input Interrupt */ 266*acc142b6SChristophe Leroy EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTERNAL, ExternalInput, do_IRQ) 26714cf11afSPaul Mackerras 26814cf11afSPaul Mackerras /* Alignment Interrupt */ 26914cf11afSPaul Mackerras ALIGNMENT_EXCEPTION 27014cf11afSPaul Mackerras 27114cf11afSPaul Mackerras /* Program Interrupt */ 27214cf11afSPaul Mackerras PROGRAM_EXCEPTION 27314cf11afSPaul Mackerras 27414cf11afSPaul Mackerras /* Floating Point Unavailable Interrupt */ 27514cf11afSPaul Mackerras#ifdef CONFIG_PPC_FPU 27614cf11afSPaul Mackerras FP_UNAVAILABLE_EXCEPTION 27714cf11afSPaul Mackerras#else 278cfac5784SScott Wood EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_UNAVAIL, \ 279*acc142b6SChristophe Leroy FloatingPointUnavailable, unknown_exception) 28014cf11afSPaul Mackerras#endif 28114cf11afSPaul Mackerras /* System Call Interrupt */ 28214cf11afSPaul Mackerras START_EXCEPTION(SystemCall) 2831a4b739bSChristophe Leroy SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL 28414cf11afSPaul Mackerras 28525985edcSLucas De Marchi /* Auxiliary Processor Unavailable Interrupt */ 286cfac5784SScott Wood EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_UNAVAIL, \ 287*acc142b6SChristophe Leroy AuxillaryProcessorUnavailable, unknown_exception) 28814cf11afSPaul Mackerras 28914cf11afSPaul Mackerras /* Decrementer Interrupt */ 29014cf11afSPaul Mackerras DECREMENTER_EXCEPTION 29114cf11afSPaul Mackerras 29214cf11afSPaul Mackerras /* Fixed Internal Timer Interrupt */ 29314cf11afSPaul Mackerras /* TODO: Add FIT support */ 294*acc142b6SChristophe Leroy EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT, FixedIntervalTimer, unknown_exception) 29514cf11afSPaul Mackerras 29614cf11afSPaul Mackerras /* Watchdog Timer Interrupt */ 29714cf11afSPaul Mackerras /* TODO: Add watchdog support */ 29814cf11afSPaul Mackerras#ifdef CONFIG_BOOKE_WDT 299cfac5784SScott Wood CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, WatchdogException) 30014cf11afSPaul Mackerras#else 301cfac5784SScott Wood CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, unknown_exception) 30214cf11afSPaul Mackerras#endif 30314cf11afSPaul Mackerras 30414cf11afSPaul Mackerras /* Data TLB Error Interrupt */ 305e7f75ad0SDave Kleikamp START_EXCEPTION(DataTLBError44x) 306ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 307ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH1, r11 308ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH2, r12 309ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH3, r13 31014cf11afSPaul Mackerras mfcr r11 311ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH4, r11 31214cf11afSPaul Mackerras mfspr r10, SPRN_DEAR /* Get faulting address */ 31314cf11afSPaul Mackerras 31414cf11afSPaul Mackerras /* If we are faulting a kernel address, we have to use the 31514cf11afSPaul Mackerras * kernel page tables. 31614cf11afSPaul Mackerras */ 3178a13c4f9SKumar Gala lis r11, PAGE_OFFSET@h 31814cf11afSPaul Mackerras cmplw r10, r11 31914cf11afSPaul Mackerras blt+ 3f 32014cf11afSPaul Mackerras lis r11, swapper_pg_dir@h 32114cf11afSPaul Mackerras ori r11, r11, swapper_pg_dir@l 32214cf11afSPaul Mackerras 32314cf11afSPaul Mackerras mfspr r12,SPRN_MMUCR 32414cf11afSPaul Mackerras rlwinm r12,r12,0,0,23 /* Clear TID */ 32514cf11afSPaul Mackerras 32614cf11afSPaul Mackerras b 4f 32714cf11afSPaul Mackerras 32814cf11afSPaul Mackerras /* Get the PGD for the current thread */ 32914cf11afSPaul Mackerras3: 330ee43eb78SBenjamin Herrenschmidt mfspr r11,SPRN_SPRG_THREAD 33114cf11afSPaul Mackerras lwz r11,PGDIR(r11) 33214cf11afSPaul Mackerras 33314cf11afSPaul Mackerras /* Load PID into MMUCR TID */ 33414cf11afSPaul Mackerras mfspr r12,SPRN_MMUCR 33514cf11afSPaul Mackerras mfspr r13,SPRN_PID /* Get PID */ 33614cf11afSPaul Mackerras rlwimi r12,r13,0,24,31 /* Set TID */ 33714cf11afSPaul Mackerras 33814cf11afSPaul Mackerras4: 33914cf11afSPaul Mackerras mtspr SPRN_MMUCR,r12 34014cf11afSPaul Mackerras 3411bc54c03SBenjamin Herrenschmidt /* Mask of required permission bits. Note that while we 3421bc54c03SBenjamin Herrenschmidt * do copy ESR:ST to _PAGE_RW position as trying to write 3431bc54c03SBenjamin Herrenschmidt * to an RO page is pretty common, we don't do it with 3441bc54c03SBenjamin Herrenschmidt * _PAGE_DIRTY. We could do it, but it's a fairly rare 3451bc54c03SBenjamin Herrenschmidt * event so I'd rather take the overhead when it happens 3461bc54c03SBenjamin Herrenschmidt * rather than adding an instruction here. We should measure 3471bc54c03SBenjamin Herrenschmidt * whether the whole thing is worth it in the first place 3481bc54c03SBenjamin Herrenschmidt * as we could avoid loading SPRN_ESR completely in the first 3491bc54c03SBenjamin Herrenschmidt * place... 3501bc54c03SBenjamin Herrenschmidt * 3511bc54c03SBenjamin Herrenschmidt * TODO: Is it worth doing that mfspr & rlwimi in the first 3521bc54c03SBenjamin Herrenschmidt * place or can we save a couple of instructions here ? 3531bc54c03SBenjamin Herrenschmidt */ 3541bc54c03SBenjamin Herrenschmidt mfspr r12,SPRN_ESR 3551bc54c03SBenjamin Herrenschmidt li r13,_PAGE_PRESENT|_PAGE_ACCESSED 3561bc54c03SBenjamin Herrenschmidt rlwimi r13,r12,10,30,30 3571bc54c03SBenjamin Herrenschmidt 3581bc54c03SBenjamin Herrenschmidt /* Load the PTE */ 359ca9153a3SIlya Yanok /* Compute pgdir/pmd offset */ 360ca9153a3SIlya Yanok rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29 36114cf11afSPaul Mackerras lwzx r11, r12, r11 /* Get pgd/pmd entry */ 36214cf11afSPaul Mackerras rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ 36314cf11afSPaul Mackerras beq 2f /* Bail if no table */ 36414cf11afSPaul Mackerras 365ca9153a3SIlya Yanok /* Compute pte address */ 366ca9153a3SIlya Yanok rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28 3671bc54c03SBenjamin Herrenschmidt lwz r11, 0(r12) /* Get high word of pte entry */ 3681bc54c03SBenjamin Herrenschmidt lwz r12, 4(r12) /* Get low word of pte entry */ 36914cf11afSPaul Mackerras 3701bc54c03SBenjamin Herrenschmidt lis r10,tlb_44x_index@ha 3711bc54c03SBenjamin Herrenschmidt 3721bc54c03SBenjamin Herrenschmidt andc. r13,r13,r12 /* Check permission */ 3731bc54c03SBenjamin Herrenschmidt 3741bc54c03SBenjamin Herrenschmidt /* Load the next available TLB index */ 3751bc54c03SBenjamin Herrenschmidt lwz r13,tlb_44x_index@l(r10) 3761bc54c03SBenjamin Herrenschmidt 377ea782658SBhaskar Chowdhury bne 2f /* Bail if permission mismatch */ 3781bc54c03SBenjamin Herrenschmidt 3791bc54c03SBenjamin Herrenschmidt /* Increment, rollover, and store TLB index */ 3801bc54c03SBenjamin Herrenschmidt addi r13,r13,1 3811bc54c03SBenjamin Herrenschmidt 3826c16816bSChristophe Leroy patch_site 0f, patch__tlb_44x_hwater_D 3831bc54c03SBenjamin Herrenschmidt /* Compare with watermark (instruction gets patched) */ 3846c16816bSChristophe Leroy0: cmpwi 0,r13,1 /* reserve entries */ 3851bc54c03SBenjamin Herrenschmidt ble 5f 3861bc54c03SBenjamin Herrenschmidt li r13,0 3871bc54c03SBenjamin Herrenschmidt5: 3881bc54c03SBenjamin Herrenschmidt /* Store the next available TLB index */ 3891bc54c03SBenjamin Herrenschmidt stw r13,tlb_44x_index@l(r10) 3901bc54c03SBenjamin Herrenschmidt 3911bc54c03SBenjamin Herrenschmidt /* Re-load the faulting address */ 3921bc54c03SBenjamin Herrenschmidt mfspr r10,SPRN_DEAR 39314cf11afSPaul Mackerras 39414cf11afSPaul Mackerras /* Jump to common tlb load */ 395e7f75ad0SDave Kleikamp b finish_tlb_load_44x 39614cf11afSPaul Mackerras 39714cf11afSPaul Mackerras2: 39814cf11afSPaul Mackerras /* The bailout. Restore registers to pre-exception conditions 39914cf11afSPaul Mackerras * and call the heavyweights to help us out. 40014cf11afSPaul Mackerras */ 401ee43eb78SBenjamin Herrenschmidt mfspr r11, SPRN_SPRG_RSCRATCH4 40214cf11afSPaul Mackerras mtcr r11 403ee43eb78SBenjamin Herrenschmidt mfspr r13, SPRN_SPRG_RSCRATCH3 404ee43eb78SBenjamin Herrenschmidt mfspr r12, SPRN_SPRG_RSCRATCH2 405ee43eb78SBenjamin Herrenschmidt mfspr r11, SPRN_SPRG_RSCRATCH1 406ee43eb78SBenjamin Herrenschmidt mfspr r10, SPRN_SPRG_RSCRATCH0 4071bc54c03SBenjamin Herrenschmidt b DataStorage 40814cf11afSPaul Mackerras 40914cf11afSPaul Mackerras /* Instruction TLB Error Interrupt */ 41014cf11afSPaul Mackerras /* 41114cf11afSPaul Mackerras * Nearly the same as above, except we get our 41214cf11afSPaul Mackerras * information from different registers and bailout 41314cf11afSPaul Mackerras * to a different point. 41414cf11afSPaul Mackerras */ 415e7f75ad0SDave Kleikamp START_EXCEPTION(InstructionTLBError44x) 416ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 417ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH1, r11 418ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH2, r12 419ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH3, r13 42014cf11afSPaul Mackerras mfcr r11 421ee43eb78SBenjamin Herrenschmidt mtspr SPRN_SPRG_WSCRATCH4, r11 42214cf11afSPaul Mackerras mfspr r10, SPRN_SRR0 /* Get faulting address */ 42314cf11afSPaul Mackerras 42414cf11afSPaul Mackerras /* If we are faulting a kernel address, we have to use the 42514cf11afSPaul Mackerras * kernel page tables. 42614cf11afSPaul Mackerras */ 4278a13c4f9SKumar Gala lis r11, PAGE_OFFSET@h 42814cf11afSPaul Mackerras cmplw r10, r11 42914cf11afSPaul Mackerras blt+ 3f 43014cf11afSPaul Mackerras lis r11, swapper_pg_dir@h 43114cf11afSPaul Mackerras ori r11, r11, swapper_pg_dir@l 43214cf11afSPaul Mackerras 43314cf11afSPaul Mackerras mfspr r12,SPRN_MMUCR 43414cf11afSPaul Mackerras rlwinm r12,r12,0,0,23 /* Clear TID */ 43514cf11afSPaul Mackerras 43614cf11afSPaul Mackerras b 4f 43714cf11afSPaul Mackerras 43814cf11afSPaul Mackerras /* Get the PGD for the current thread */ 43914cf11afSPaul Mackerras3: 440ee43eb78SBenjamin Herrenschmidt mfspr r11,SPRN_SPRG_THREAD 44114cf11afSPaul Mackerras lwz r11,PGDIR(r11) 44214cf11afSPaul Mackerras 44314cf11afSPaul Mackerras /* Load PID into MMUCR TID */ 44414cf11afSPaul Mackerras mfspr r12,SPRN_MMUCR 44514cf11afSPaul Mackerras mfspr r13,SPRN_PID /* Get PID */ 44614cf11afSPaul Mackerras rlwimi r12,r13,0,24,31 /* Set TID */ 44714cf11afSPaul Mackerras 44814cf11afSPaul Mackerras4: 44914cf11afSPaul Mackerras mtspr SPRN_MMUCR,r12 45014cf11afSPaul Mackerras 4511bc54c03SBenjamin Herrenschmidt /* Make up the required permissions */ 452ea3cc330SBenjamin Herrenschmidt li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 4531bc54c03SBenjamin Herrenschmidt 454ca9153a3SIlya Yanok /* Compute pgdir/pmd offset */ 455ca9153a3SIlya Yanok rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29 45614cf11afSPaul Mackerras lwzx r11, r12, r11 /* Get pgd/pmd entry */ 45714cf11afSPaul Mackerras rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ 45814cf11afSPaul Mackerras beq 2f /* Bail if no table */ 45914cf11afSPaul Mackerras 460ca9153a3SIlya Yanok /* Compute pte address */ 461ca9153a3SIlya Yanok rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28 4621bc54c03SBenjamin Herrenschmidt lwz r11, 0(r12) /* Get high word of pte entry */ 4631bc54c03SBenjamin Herrenschmidt lwz r12, 4(r12) /* Get low word of pte entry */ 46414cf11afSPaul Mackerras 4651bc54c03SBenjamin Herrenschmidt lis r10,tlb_44x_index@ha 4661bc54c03SBenjamin Herrenschmidt 4671bc54c03SBenjamin Herrenschmidt andc. r13,r13,r12 /* Check permission */ 4681bc54c03SBenjamin Herrenschmidt 4691bc54c03SBenjamin Herrenschmidt /* Load the next available TLB index */ 4701bc54c03SBenjamin Herrenschmidt lwz r13,tlb_44x_index@l(r10) 4711bc54c03SBenjamin Herrenschmidt 472ea782658SBhaskar Chowdhury bne 2f /* Bail if permission mismatch */ 4731bc54c03SBenjamin Herrenschmidt 4741bc54c03SBenjamin Herrenschmidt /* Increment, rollover, and store TLB index */ 4751bc54c03SBenjamin Herrenschmidt addi r13,r13,1 4761bc54c03SBenjamin Herrenschmidt 4776c16816bSChristophe Leroy patch_site 0f, patch__tlb_44x_hwater_I 4781bc54c03SBenjamin Herrenschmidt /* Compare with watermark (instruction gets patched) */ 4796c16816bSChristophe Leroy0: cmpwi 0,r13,1 /* reserve entries */ 4801bc54c03SBenjamin Herrenschmidt ble 5f 4811bc54c03SBenjamin Herrenschmidt li r13,0 4821bc54c03SBenjamin Herrenschmidt5: 4831bc54c03SBenjamin Herrenschmidt /* Store the next available TLB index */ 4841bc54c03SBenjamin Herrenschmidt stw r13,tlb_44x_index@l(r10) 4851bc54c03SBenjamin Herrenschmidt 4861bc54c03SBenjamin Herrenschmidt /* Re-load the faulting address */ 4871bc54c03SBenjamin Herrenschmidt mfspr r10,SPRN_SRR0 48814cf11afSPaul Mackerras 48914cf11afSPaul Mackerras /* Jump to common TLB load point */ 490e7f75ad0SDave Kleikamp b finish_tlb_load_44x 49114cf11afSPaul Mackerras 49214cf11afSPaul Mackerras2: 49314cf11afSPaul Mackerras /* The bailout. Restore registers to pre-exception conditions 49414cf11afSPaul Mackerras * and call the heavyweights to help us out. 49514cf11afSPaul Mackerras */ 496ee43eb78SBenjamin Herrenschmidt mfspr r11, SPRN_SPRG_RSCRATCH4 49714cf11afSPaul Mackerras mtcr r11 498ee43eb78SBenjamin Herrenschmidt mfspr r13, SPRN_SPRG_RSCRATCH3 499ee43eb78SBenjamin Herrenschmidt mfspr r12, SPRN_SPRG_RSCRATCH2 500ee43eb78SBenjamin Herrenschmidt mfspr r11, SPRN_SPRG_RSCRATCH1 501ee43eb78SBenjamin Herrenschmidt mfspr r10, SPRN_SPRG_RSCRATCH0 50214cf11afSPaul Mackerras b InstructionStorage 50314cf11afSPaul Mackerras 50414cf11afSPaul Mackerras/* 50514cf11afSPaul Mackerras * Both the instruction and data TLB miss get to this 50614cf11afSPaul Mackerras * point to load the TLB. 50714cf11afSPaul Mackerras * r10 - EA of fault 5081bc54c03SBenjamin Herrenschmidt * r11 - PTE high word value 5091bc54c03SBenjamin Herrenschmidt * r12 - PTE low word value 5101bc54c03SBenjamin Herrenschmidt * r13 - TLB index 51114cf11afSPaul Mackerras * MMUCR - loaded with proper value when we get here 51214cf11afSPaul Mackerras * Upon exit, we reload everything and RFI. 51314cf11afSPaul Mackerras */ 514e7f75ad0SDave Kleikampfinish_tlb_load_44x: 5151bc54c03SBenjamin Herrenschmidt /* Combine RPN & ERPN an write WS 0 */ 516ca9153a3SIlya Yanok rlwimi r11,r12,0,0,31-PAGE_SHIFT 5171bc54c03SBenjamin Herrenschmidt tlbwe r11,r13,PPC44x_TLB_XLAT 51814cf11afSPaul Mackerras 51914cf11afSPaul Mackerras /* 5201bc54c03SBenjamin Herrenschmidt * Create WS1. This is the faulting address (EPN), 52114cf11afSPaul Mackerras * page size, and valid flag. 52214cf11afSPaul Mackerras */ 523ca9153a3SIlya Yanok li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE 524ca9153a3SIlya Yanok /* Insert valid and page size */ 525ca9153a3SIlya Yanok rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31 52614cf11afSPaul Mackerras tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */ 52714cf11afSPaul Mackerras 5281bc54c03SBenjamin Herrenschmidt /* And WS 2 */ 5291bc54c03SBenjamin Herrenschmidt li r10,0xf85 /* Mask to apply from PTE */ 5301bc54c03SBenjamin Herrenschmidt rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ 5311bc54c03SBenjamin Herrenschmidt and r11,r12,r10 /* Mask PTE bits to keep */ 5321bc54c03SBenjamin Herrenschmidt andi. r10,r12,_PAGE_USER /* User page ? */ 5331bc54c03SBenjamin Herrenschmidt beq 1f /* nope, leave U bits empty */ 5341bc54c03SBenjamin Herrenschmidt rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ 5351bc54c03SBenjamin Herrenschmidt1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */ 53614cf11afSPaul Mackerras 53714cf11afSPaul Mackerras /* Done...restore registers and get out of here. 53814cf11afSPaul Mackerras */ 539ee43eb78SBenjamin Herrenschmidt mfspr r11, SPRN_SPRG_RSCRATCH4 54014cf11afSPaul Mackerras mtcr r11 541ee43eb78SBenjamin Herrenschmidt mfspr r13, SPRN_SPRG_RSCRATCH3 542ee43eb78SBenjamin Herrenschmidt mfspr r12, SPRN_SPRG_RSCRATCH2 543ee43eb78SBenjamin Herrenschmidt mfspr r11, SPRN_SPRG_RSCRATCH1 544ee43eb78SBenjamin Herrenschmidt mfspr r10, SPRN_SPRG_RSCRATCH0 54514cf11afSPaul Mackerras rfi /* Force context change */ 54614cf11afSPaul Mackerras 547e7f75ad0SDave Kleikamp/* TLB error interrupts for 476 548e7f75ad0SDave Kleikamp */ 549e7f75ad0SDave Kleikamp#ifdef CONFIG_PPC_47x 550e7f75ad0SDave Kleikamp START_EXCEPTION(DataTLBError47x) 551e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */ 552e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH1,r11 553e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH2,r12 554e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH3,r13 555e7f75ad0SDave Kleikamp mfcr r11 556e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH4,r11 557e7f75ad0SDave Kleikamp mfspr r10,SPRN_DEAR /* Get faulting address */ 558e7f75ad0SDave Kleikamp 559e7f75ad0SDave Kleikamp /* If we are faulting a kernel address, we have to use the 560e7f75ad0SDave Kleikamp * kernel page tables. 561e7f75ad0SDave Kleikamp */ 562e7f75ad0SDave Kleikamp lis r11,PAGE_OFFSET@h 563e7f75ad0SDave Kleikamp cmplw cr0,r10,r11 564e7f75ad0SDave Kleikamp blt+ 3f 565e7f75ad0SDave Kleikamp lis r11,swapper_pg_dir@h 566e7f75ad0SDave Kleikamp ori r11,r11, swapper_pg_dir@l 567e7f75ad0SDave Kleikamp li r12,0 /* MMUCR = 0 */ 568e7f75ad0SDave Kleikamp b 4f 569e7f75ad0SDave Kleikamp 570e7f75ad0SDave Kleikamp /* Get the PGD for the current thread and setup MMUCR */ 571e7f75ad0SDave Kleikamp3: mfspr r11,SPRN_SPRG3 572e7f75ad0SDave Kleikamp lwz r11,PGDIR(r11) 573e7f75ad0SDave Kleikamp mfspr r12,SPRN_PID /* Get PID */ 574e7f75ad0SDave Kleikamp4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */ 575e7f75ad0SDave Kleikamp 576e7f75ad0SDave Kleikamp /* Mask of required permission bits. Note that while we 577e7f75ad0SDave Kleikamp * do copy ESR:ST to _PAGE_RW position as trying to write 578e7f75ad0SDave Kleikamp * to an RO page is pretty common, we don't do it with 579e7f75ad0SDave Kleikamp * _PAGE_DIRTY. We could do it, but it's a fairly rare 580e7f75ad0SDave Kleikamp * event so I'd rather take the overhead when it happens 581e7f75ad0SDave Kleikamp * rather than adding an instruction here. We should measure 582e7f75ad0SDave Kleikamp * whether the whole thing is worth it in the first place 583e7f75ad0SDave Kleikamp * as we could avoid loading SPRN_ESR completely in the first 584e7f75ad0SDave Kleikamp * place... 585e7f75ad0SDave Kleikamp * 586e7f75ad0SDave Kleikamp * TODO: Is it worth doing that mfspr & rlwimi in the first 587e7f75ad0SDave Kleikamp * place or can we save a couple of instructions here ? 588e7f75ad0SDave Kleikamp */ 589e7f75ad0SDave Kleikamp mfspr r12,SPRN_ESR 590e7f75ad0SDave Kleikamp li r13,_PAGE_PRESENT|_PAGE_ACCESSED 591e7f75ad0SDave Kleikamp rlwimi r13,r12,10,30,30 592e7f75ad0SDave Kleikamp 593e7f75ad0SDave Kleikamp /* Load the PTE */ 594e7f75ad0SDave Kleikamp /* Compute pgdir/pmd offset */ 595e7f75ad0SDave Kleikamp rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29 596e7f75ad0SDave Kleikamp lwzx r11,r12,r11 /* Get pgd/pmd entry */ 597e7f75ad0SDave Kleikamp 598e7f75ad0SDave Kleikamp /* Word 0 is EPN,V,TS,DSIZ */ 599e7f75ad0SDave Kleikamp li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE 600e7f75ad0SDave Kleikamp rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/ 601e7f75ad0SDave Kleikamp li r12,0 602e7f75ad0SDave Kleikamp tlbwe r10,r12,0 603e7f75ad0SDave Kleikamp 604e7f75ad0SDave Kleikamp /* XXX can we do better ? Need to make sure tlbwe has established 605e7f75ad0SDave Kleikamp * latch V bit in MMUCR0 before the PTE is loaded further down */ 606e7f75ad0SDave Kleikamp#ifdef CONFIG_SMP 607e7f75ad0SDave Kleikamp isync 608e7f75ad0SDave Kleikamp#endif 609e7f75ad0SDave Kleikamp 610e7f75ad0SDave Kleikamp rlwinm. r12,r11,0,0,20 /* Extract pt base address */ 611e7f75ad0SDave Kleikamp /* Compute pte address */ 612e7f75ad0SDave Kleikamp rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28 613e7f75ad0SDave Kleikamp beq 2f /* Bail if no table */ 614e7f75ad0SDave Kleikamp lwz r11,0(r12) /* Get high word of pte entry */ 615e7f75ad0SDave Kleikamp 616e7f75ad0SDave Kleikamp /* XXX can we do better ? maybe insert a known 0 bit from r11 into the 617e7f75ad0SDave Kleikamp * bottom of r12 to create a data dependency... We can also use r10 618e7f75ad0SDave Kleikamp * as destination nowadays 619e7f75ad0SDave Kleikamp */ 620e7f75ad0SDave Kleikamp#ifdef CONFIG_SMP 621e7f75ad0SDave Kleikamp lwsync 622e7f75ad0SDave Kleikamp#endif 623e7f75ad0SDave Kleikamp lwz r12,4(r12) /* Get low word of pte entry */ 624e7f75ad0SDave Kleikamp 625e7f75ad0SDave Kleikamp andc. r13,r13,r12 /* Check permission */ 626e7f75ad0SDave Kleikamp 627e7f75ad0SDave Kleikamp /* Jump to common tlb load */ 628e7f75ad0SDave Kleikamp beq finish_tlb_load_47x 629e7f75ad0SDave Kleikamp 630e7f75ad0SDave Kleikamp2: /* The bailout. Restore registers to pre-exception conditions 631e7f75ad0SDave Kleikamp * and call the heavyweights to help us out. 632e7f75ad0SDave Kleikamp */ 633e7f75ad0SDave Kleikamp mfspr r11,SPRN_SPRG_RSCRATCH4 634e7f75ad0SDave Kleikamp mtcr r11 635e7f75ad0SDave Kleikamp mfspr r13,SPRN_SPRG_RSCRATCH3 636e7f75ad0SDave Kleikamp mfspr r12,SPRN_SPRG_RSCRATCH2 637e7f75ad0SDave Kleikamp mfspr r11,SPRN_SPRG_RSCRATCH1 638e7f75ad0SDave Kleikamp mfspr r10,SPRN_SPRG_RSCRATCH0 639e7f75ad0SDave Kleikamp b DataStorage 640e7f75ad0SDave Kleikamp 641e7f75ad0SDave Kleikamp /* Instruction TLB Error Interrupt */ 642e7f75ad0SDave Kleikamp /* 643e7f75ad0SDave Kleikamp * Nearly the same as above, except we get our 644e7f75ad0SDave Kleikamp * information from different registers and bailout 645e7f75ad0SDave Kleikamp * to a different point. 646e7f75ad0SDave Kleikamp */ 647e7f75ad0SDave Kleikamp START_EXCEPTION(InstructionTLBError47x) 648e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */ 649e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH1,r11 650e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH2,r12 651e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH3,r13 652e7f75ad0SDave Kleikamp mfcr r11 653e7f75ad0SDave Kleikamp mtspr SPRN_SPRG_WSCRATCH4,r11 654e7f75ad0SDave Kleikamp mfspr r10,SPRN_SRR0 /* Get faulting address */ 655e7f75ad0SDave Kleikamp 656e7f75ad0SDave Kleikamp /* If we are faulting a kernel address, we have to use the 657e7f75ad0SDave Kleikamp * kernel page tables. 658e7f75ad0SDave Kleikamp */ 659e7f75ad0SDave Kleikamp lis r11,PAGE_OFFSET@h 660e7f75ad0SDave Kleikamp cmplw cr0,r10,r11 661e7f75ad0SDave Kleikamp blt+ 3f 662e7f75ad0SDave Kleikamp lis r11,swapper_pg_dir@h 663e7f75ad0SDave Kleikamp ori r11,r11, swapper_pg_dir@l 664e7f75ad0SDave Kleikamp li r12,0 /* MMUCR = 0 */ 665e7f75ad0SDave Kleikamp b 4f 666e7f75ad0SDave Kleikamp 667e7f75ad0SDave Kleikamp /* Get the PGD for the current thread and setup MMUCR */ 668e7f75ad0SDave Kleikamp3: mfspr r11,SPRN_SPRG_THREAD 669e7f75ad0SDave Kleikamp lwz r11,PGDIR(r11) 670e7f75ad0SDave Kleikamp mfspr r12,SPRN_PID /* Get PID */ 671e7f75ad0SDave Kleikamp4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */ 672e7f75ad0SDave Kleikamp 673e7f75ad0SDave Kleikamp /* Make up the required permissions */ 674e7f75ad0SDave Kleikamp li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 675e7f75ad0SDave Kleikamp 676e7f75ad0SDave Kleikamp /* Load PTE */ 677e7f75ad0SDave Kleikamp /* Compute pgdir/pmd offset */ 678e7f75ad0SDave Kleikamp rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29 679e7f75ad0SDave Kleikamp lwzx r11,r12,r11 /* Get pgd/pmd entry */ 680e7f75ad0SDave Kleikamp 681e7f75ad0SDave Kleikamp /* Word 0 is EPN,V,TS,DSIZ */ 682e7f75ad0SDave Kleikamp li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE 683e7f75ad0SDave Kleikamp rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/ 684e7f75ad0SDave Kleikamp li r12,0 685e7f75ad0SDave Kleikamp tlbwe r10,r12,0 686e7f75ad0SDave Kleikamp 687e7f75ad0SDave Kleikamp /* XXX can we do better ? Need to make sure tlbwe has established 688e7f75ad0SDave Kleikamp * latch V bit in MMUCR0 before the PTE is loaded further down */ 689e7f75ad0SDave Kleikamp#ifdef CONFIG_SMP 690e7f75ad0SDave Kleikamp isync 691e7f75ad0SDave Kleikamp#endif 692e7f75ad0SDave Kleikamp 693e7f75ad0SDave Kleikamp rlwinm. r12,r11,0,0,20 /* Extract pt base address */ 694e7f75ad0SDave Kleikamp /* Compute pte address */ 695e7f75ad0SDave Kleikamp rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28 696e7f75ad0SDave Kleikamp beq 2f /* Bail if no table */ 697e7f75ad0SDave Kleikamp 698e7f75ad0SDave Kleikamp lwz r11,0(r12) /* Get high word of pte entry */ 699e7f75ad0SDave Kleikamp /* XXX can we do better ? maybe insert a known 0 bit from r11 into the 700e7f75ad0SDave Kleikamp * bottom of r12 to create a data dependency... We can also use r10 701e7f75ad0SDave Kleikamp * as destination nowadays 702e7f75ad0SDave Kleikamp */ 703e7f75ad0SDave Kleikamp#ifdef CONFIG_SMP 704e7f75ad0SDave Kleikamp lwsync 705e7f75ad0SDave Kleikamp#endif 706e7f75ad0SDave Kleikamp lwz r12,4(r12) /* Get low word of pte entry */ 707e7f75ad0SDave Kleikamp 708e7f75ad0SDave Kleikamp andc. r13,r13,r12 /* Check permission */ 709e7f75ad0SDave Kleikamp 710e7f75ad0SDave Kleikamp /* Jump to common TLB load point */ 711e7f75ad0SDave Kleikamp beq finish_tlb_load_47x 712e7f75ad0SDave Kleikamp 713e7f75ad0SDave Kleikamp2: /* The bailout. Restore registers to pre-exception conditions 714e7f75ad0SDave Kleikamp * and call the heavyweights to help us out. 715e7f75ad0SDave Kleikamp */ 716e7f75ad0SDave Kleikamp mfspr r11, SPRN_SPRG_RSCRATCH4 717e7f75ad0SDave Kleikamp mtcr r11 718e7f75ad0SDave Kleikamp mfspr r13, SPRN_SPRG_RSCRATCH3 719e7f75ad0SDave Kleikamp mfspr r12, SPRN_SPRG_RSCRATCH2 720e7f75ad0SDave Kleikamp mfspr r11, SPRN_SPRG_RSCRATCH1 721e7f75ad0SDave Kleikamp mfspr r10, SPRN_SPRG_RSCRATCH0 722e7f75ad0SDave Kleikamp b InstructionStorage 723e7f75ad0SDave Kleikamp 724e7f75ad0SDave Kleikamp/* 725e7f75ad0SDave Kleikamp * Both the instruction and data TLB miss get to this 726e7f75ad0SDave Kleikamp * point to load the TLB. 727e7f75ad0SDave Kleikamp * r10 - free to use 728e7f75ad0SDave Kleikamp * r11 - PTE high word value 729e7f75ad0SDave Kleikamp * r12 - PTE low word value 730e7f75ad0SDave Kleikamp * r13 - free to use 731e7f75ad0SDave Kleikamp * MMUCR - loaded with proper value when we get here 732e7f75ad0SDave Kleikamp * Upon exit, we reload everything and RFI. 733e7f75ad0SDave Kleikamp */ 734e7f75ad0SDave Kleikampfinish_tlb_load_47x: 735e7f75ad0SDave Kleikamp /* Combine RPN & ERPN an write WS 1 */ 736e7f75ad0SDave Kleikamp rlwimi r11,r12,0,0,31-PAGE_SHIFT 737e7f75ad0SDave Kleikamp tlbwe r11,r13,1 738e7f75ad0SDave Kleikamp 739e7f75ad0SDave Kleikamp /* And make up word 2 */ 740e7f75ad0SDave Kleikamp li r10,0xf85 /* Mask to apply from PTE */ 741e7f75ad0SDave Kleikamp rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ 742e7f75ad0SDave Kleikamp and r11,r12,r10 /* Mask PTE bits to keep */ 743e7f75ad0SDave Kleikamp andi. r10,r12,_PAGE_USER /* User page ? */ 744e7f75ad0SDave Kleikamp beq 1f /* nope, leave U bits empty */ 745e7f75ad0SDave Kleikamp rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ 746e7f75ad0SDave Kleikamp1: tlbwe r11,r13,2 747e7f75ad0SDave Kleikamp 748e7f75ad0SDave Kleikamp /* Done...restore registers and get out of here. 749e7f75ad0SDave Kleikamp */ 750e7f75ad0SDave Kleikamp mfspr r11, SPRN_SPRG_RSCRATCH4 751e7f75ad0SDave Kleikamp mtcr r11 752e7f75ad0SDave Kleikamp mfspr r13, SPRN_SPRG_RSCRATCH3 753e7f75ad0SDave Kleikamp mfspr r12, SPRN_SPRG_RSCRATCH2 754e7f75ad0SDave Kleikamp mfspr r11, SPRN_SPRG_RSCRATCH1 755e7f75ad0SDave Kleikamp mfspr r10, SPRN_SPRG_RSCRATCH0 756e7f75ad0SDave Kleikamp rfi 757e7f75ad0SDave Kleikamp 758e7f75ad0SDave Kleikamp#endif /* CONFIG_PPC_47x */ 759e7f75ad0SDave Kleikamp 760e7f75ad0SDave Kleikamp /* Debug Interrupt */ 761e7f75ad0SDave Kleikamp /* 762e7f75ad0SDave Kleikamp * This statement needs to exist at the end of the IVPR 763e7f75ad0SDave Kleikamp * definition just in case you end up taking a debug 764e7f75ad0SDave Kleikamp * exception within another exception. 765e7f75ad0SDave Kleikamp */ 766e7f75ad0SDave Kleikamp DEBUG_CRIT_EXCEPTION 767e7f75ad0SDave Kleikamp 768fc2a6cfeSBharat Bhushaninterrupt_end: 769fc2a6cfeSBharat Bhushan 77014cf11afSPaul Mackerras/* 77114cf11afSPaul Mackerras * Global functions 77214cf11afSPaul Mackerras */ 77314cf11afSPaul Mackerras 77414cf11afSPaul Mackerras/* 77547c0bd1aSBenjamin Herrenschmidt * Adjust the machine check IVOR on 440A cores 77647c0bd1aSBenjamin Herrenschmidt */ 77747c0bd1aSBenjamin Herrenschmidt_GLOBAL(__fixup_440A_mcheck) 77847c0bd1aSBenjamin Herrenschmidt li r3,MachineCheckA@l 77947c0bd1aSBenjamin Herrenschmidt mtspr SPRN_IVOR1,r3 78047c0bd1aSBenjamin Herrenschmidt sync 78147c0bd1aSBenjamin Herrenschmidt blr 78247c0bd1aSBenjamin Herrenschmidt 78314cf11afSPaul Mackerras_GLOBAL(set_context) 78414cf11afSPaul Mackerras 78514cf11afSPaul Mackerras#ifdef CONFIG_BDI_SWITCH 78614cf11afSPaul Mackerras /* Context switch the PTE pointer for the Abatron BDI2000. 78714cf11afSPaul Mackerras * The PGDIR is the second parameter. 78814cf11afSPaul Mackerras */ 78914cf11afSPaul Mackerras lis r5, abatron_pteptrs@h 79014cf11afSPaul Mackerras ori r5, r5, abatron_pteptrs@l 79114cf11afSPaul Mackerras stw r4, 0x4(r5) 79214cf11afSPaul Mackerras#endif 79314cf11afSPaul Mackerras mtspr SPRN_PID,r3 79414cf11afSPaul Mackerras isync /* Force context change */ 79514cf11afSPaul Mackerras blr 79614cf11afSPaul Mackerras 79714cf11afSPaul Mackerras/* 798795033c3SDave Kleikamp * Init CPU state. This is called at boot time or for secondary CPUs 799795033c3SDave Kleikamp * to setup initial TLB entries, setup IVORs, etc... 800e7f75ad0SDave Kleikamp * 801795033c3SDave Kleikamp */ 802795033c3SDave Kleikamp_GLOBAL(init_cpu_state) 803795033c3SDave Kleikamp mflr r22 804e7f75ad0SDave Kleikamp#ifdef CONFIG_PPC_47x 805446957baSAdam Buchbinder /* We use the PVR to differentiate 44x cores from 476 */ 806e7f75ad0SDave Kleikamp mfspr r3,SPRN_PVR 807e7f75ad0SDave Kleikamp srwi r3,r3,16 808df777bd3STony Breeds cmplwi cr0,r3,PVR_476FPE@h 809df777bd3STony Breeds beq head_start_47x 810e7f75ad0SDave Kleikamp cmplwi cr0,r3,PVR_476@h 811e7f75ad0SDave Kleikamp beq head_start_47x 812b4e8c8ddSTorez Smith cmplwi cr0,r3,PVR_476_ISS@h 813b4e8c8ddSTorez Smith beq head_start_47x 814e7f75ad0SDave Kleikamp#endif /* CONFIG_PPC_47x */ 815e7f75ad0SDave Kleikamp 816795033c3SDave Kleikamp/* 817795033c3SDave Kleikamp * In case the firmware didn't do it, we apply some workarounds 818795033c3SDave Kleikamp * that are good for all 440 core variants here 819795033c3SDave Kleikamp */ 820795033c3SDave Kleikamp mfspr r3,SPRN_CCR0 821795033c3SDave Kleikamp rlwinm r3,r3,0,0,27 /* disable icache prefetch */ 822795033c3SDave Kleikamp isync 823795033c3SDave Kleikamp mtspr SPRN_CCR0,r3 824795033c3SDave Kleikamp isync 825795033c3SDave Kleikamp sync 826795033c3SDave Kleikamp 827795033c3SDave Kleikamp/* 828e7f75ad0SDave Kleikamp * Set up the initial MMU state for 44x 829795033c3SDave Kleikamp * 830795033c3SDave Kleikamp * We are still executing code at the virtual address 831795033c3SDave Kleikamp * mappings set by the firmware for the base of RAM. 832795033c3SDave Kleikamp * 833795033c3SDave Kleikamp * We first invalidate all TLB entries but the one 834795033c3SDave Kleikamp * we are running from. We then load the KERNELBASE 835795033c3SDave Kleikamp * mappings so we can begin to use kernel addresses 836795033c3SDave Kleikamp * natively and so the interrupt vector locations are 837795033c3SDave Kleikamp * permanently pinned (necessary since Book E 838795033c3SDave Kleikamp * implementations always have translation enabled). 839795033c3SDave Kleikamp * 840795033c3SDave Kleikamp * TODO: Use the known TLB entry we are running from to 841795033c3SDave Kleikamp * determine which physical region we are located 842795033c3SDave Kleikamp * in. This can be used to determine where in RAM 843795033c3SDave Kleikamp * (on a shared CPU system) or PCI memory space 844795033c3SDave Kleikamp * (on a DRAMless system) we are located. 845795033c3SDave Kleikamp * For now, we assume a perfect world which means 846795033c3SDave Kleikamp * we are located at the base of DRAM (physical 0). 847795033c3SDave Kleikamp */ 848795033c3SDave Kleikamp 849795033c3SDave Kleikamp/* 850795033c3SDave Kleikamp * Search TLB for entry that we are currently using. 851795033c3SDave Kleikamp * Invalidate all entries but the one we are using. 852795033c3SDave Kleikamp */ 853795033c3SDave Kleikamp /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ 854795033c3SDave Kleikamp mfspr r3,SPRN_PID /* Get PID */ 855795033c3SDave Kleikamp mfmsr r4 /* Get MSR */ 856795033c3SDave Kleikamp andi. r4,r4,MSR_IS@l /* TS=1? */ 857795033c3SDave Kleikamp beq wmmucr /* If not, leave STS=0 */ 858795033c3SDave Kleikamp oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */ 859795033c3SDave Kleikampwmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ 860795033c3SDave Kleikamp sync 861795033c3SDave Kleikamp 862795033c3SDave Kleikamp bl invstr /* Find our address */ 863795033c3SDave Kleikampinvstr: mflr r5 /* Make it accessible */ 864795033c3SDave Kleikamp tlbsx r23,0,r5 /* Find entry we are in */ 865795033c3SDave Kleikamp li r4,0 /* Start at TLB entry 0 */ 866795033c3SDave Kleikamp li r3,0 /* Set PAGEID inval value */ 867795033c3SDave Kleikamp1: cmpw r23,r4 /* Is this our entry? */ 868795033c3SDave Kleikamp beq skpinv /* If so, skip the inval */ 869795033c3SDave Kleikamp tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ 870795033c3SDave Kleikampskpinv: addi r4,r4,1 /* Increment */ 871795033c3SDave Kleikamp cmpwi r4,64 /* Are we done? */ 872795033c3SDave Kleikamp bne 1b /* If not, repeat */ 873795033c3SDave Kleikamp isync /* If so, context change */ 874795033c3SDave Kleikamp 875795033c3SDave Kleikamp/* 876795033c3SDave Kleikamp * Configure and load pinned entry into TLB slot 63. 877795033c3SDave Kleikamp */ 87826ecb6c4SSuzuki Poulose#ifdef CONFIG_NONSTATIC_KERNEL 87926ecb6c4SSuzuki Poulose /* 88026ecb6c4SSuzuki Poulose * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT 88126ecb6c4SSuzuki Poulose * entries of the initial mapping set by the boot loader. 88226ecb6c4SSuzuki Poulose * The XLAT entry is stored in r25 88326ecb6c4SSuzuki Poulose */ 88423913245SSuzuki Poulose 88523913245SSuzuki Poulose /* Read the XLAT entry for our current mapping */ 88623913245SSuzuki Poulose tlbre r25,r23,PPC44x_TLB_XLAT 88723913245SSuzuki Poulose 88823913245SSuzuki Poulose lis r3,KERNELBASE@h 88923913245SSuzuki Poulose ori r3,r3,KERNELBASE@l 89023913245SSuzuki Poulose 89123913245SSuzuki Poulose /* Use our current RPN entry */ 89223913245SSuzuki Poulose mr r4,r25 89323913245SSuzuki Poulose#else 894795033c3SDave Kleikamp 895795033c3SDave Kleikamp lis r3,PAGE_OFFSET@h 896795033c3SDave Kleikamp ori r3,r3,PAGE_OFFSET@l 897795033c3SDave Kleikamp 898795033c3SDave Kleikamp /* Kernel is at the base of RAM */ 899795033c3SDave Kleikamp li r4, 0 /* Load the kernel physical address */ 90023913245SSuzuki Poulose#endif 901795033c3SDave Kleikamp 902795033c3SDave Kleikamp /* Load the kernel PID = 0 */ 903795033c3SDave Kleikamp li r0,0 904795033c3SDave Kleikamp mtspr SPRN_PID,r0 905795033c3SDave Kleikamp sync 906795033c3SDave Kleikamp 907795033c3SDave Kleikamp /* Initialize MMUCR */ 908795033c3SDave Kleikamp li r5,0 909795033c3SDave Kleikamp mtspr SPRN_MMUCR,r5 910795033c3SDave Kleikamp sync 911795033c3SDave Kleikamp 912795033c3SDave Kleikamp /* pageid fields */ 913795033c3SDave Kleikamp clrrwi r3,r3,10 /* Mask off the effective page number */ 914795033c3SDave Kleikamp ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M 915795033c3SDave Kleikamp 916795033c3SDave Kleikamp /* xlat fields */ 917795033c3SDave Kleikamp clrrwi r4,r4,10 /* Mask off the real page number */ 918795033c3SDave Kleikamp /* ERPN is 0 for first 4GB page */ 919795033c3SDave Kleikamp 920795033c3SDave Kleikamp /* attrib fields */ 921795033c3SDave Kleikamp /* Added guarded bit to protect against speculative loads/stores */ 922795033c3SDave Kleikamp li r5,0 923795033c3SDave Kleikamp ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) 924795033c3SDave Kleikamp 925795033c3SDave Kleikamp li r0,63 /* TLB slot 63 */ 926795033c3SDave Kleikamp 927795033c3SDave Kleikamp tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ 928795033c3SDave Kleikamp tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ 929795033c3SDave Kleikamp tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ 930795033c3SDave Kleikamp 931795033c3SDave Kleikamp /* Force context change */ 932795033c3SDave Kleikamp mfmsr r0 933795033c3SDave Kleikamp mtspr SPRN_SRR1, r0 934795033c3SDave Kleikamp lis r0,3f@h 935795033c3SDave Kleikamp ori r0,r0,3f@l 936795033c3SDave Kleikamp mtspr SPRN_SRR0,r0 937795033c3SDave Kleikamp sync 938795033c3SDave Kleikamp rfi 939795033c3SDave Kleikamp 940795033c3SDave Kleikamp /* If necessary, invalidate original entry we used */ 941795033c3SDave Kleikamp3: cmpwi r23,63 942795033c3SDave Kleikamp beq 4f 943795033c3SDave Kleikamp li r6,0 944795033c3SDave Kleikamp tlbwe r6,r23,PPC44x_TLB_PAGEID 945795033c3SDave Kleikamp isync 946795033c3SDave Kleikamp 947795033c3SDave Kleikamp4: 948795033c3SDave Kleikamp#ifdef CONFIG_PPC_EARLY_DEBUG_44x 949795033c3SDave Kleikamp /* Add UART mapping for early debug. */ 950795033c3SDave Kleikamp 951795033c3SDave Kleikamp /* pageid fields */ 952795033c3SDave Kleikamp lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h 953795033c3SDave Kleikamp ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K 954795033c3SDave Kleikamp 955795033c3SDave Kleikamp /* xlat fields */ 956795033c3SDave Kleikamp lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h 957795033c3SDave Kleikamp ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH 958795033c3SDave Kleikamp 959795033c3SDave Kleikamp /* attrib fields */ 960795033c3SDave Kleikamp li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G) 961795033c3SDave Kleikamp li r0,62 /* TLB slot 0 */ 962795033c3SDave Kleikamp 963795033c3SDave Kleikamp tlbwe r3,r0,PPC44x_TLB_PAGEID 964795033c3SDave Kleikamp tlbwe r4,r0,PPC44x_TLB_XLAT 965795033c3SDave Kleikamp tlbwe r5,r0,PPC44x_TLB_ATTRIB 966795033c3SDave Kleikamp 967795033c3SDave Kleikamp /* Force context change */ 968795033c3SDave Kleikamp isync 969795033c3SDave Kleikamp#endif /* CONFIG_PPC_EARLY_DEBUG_44x */ 970795033c3SDave Kleikamp 971795033c3SDave Kleikamp /* Establish the interrupt vector offsets */ 972795033c3SDave Kleikamp SET_IVOR(0, CriticalInput); 973795033c3SDave Kleikamp SET_IVOR(1, MachineCheck); 974795033c3SDave Kleikamp SET_IVOR(2, DataStorage); 975795033c3SDave Kleikamp SET_IVOR(3, InstructionStorage); 976795033c3SDave Kleikamp SET_IVOR(4, ExternalInput); 977795033c3SDave Kleikamp SET_IVOR(5, Alignment); 978795033c3SDave Kleikamp SET_IVOR(6, Program); 979795033c3SDave Kleikamp SET_IVOR(7, FloatingPointUnavailable); 980795033c3SDave Kleikamp SET_IVOR(8, SystemCall); 981795033c3SDave Kleikamp SET_IVOR(9, AuxillaryProcessorUnavailable); 982795033c3SDave Kleikamp SET_IVOR(10, Decrementer); 983795033c3SDave Kleikamp SET_IVOR(11, FixedIntervalTimer); 984795033c3SDave Kleikamp SET_IVOR(12, WatchdogTimer); 985e7f75ad0SDave Kleikamp SET_IVOR(13, DataTLBError44x); 986e7f75ad0SDave Kleikamp SET_IVOR(14, InstructionTLBError44x); 987795033c3SDave Kleikamp SET_IVOR(15, DebugCrit); 988795033c3SDave Kleikamp 989e7f75ad0SDave Kleikamp b head_start_common 990e7f75ad0SDave Kleikamp 991e7f75ad0SDave Kleikamp 992e7f75ad0SDave Kleikamp#ifdef CONFIG_PPC_47x 993e7f75ad0SDave Kleikamp 994e7f75ad0SDave Kleikamp#ifdef CONFIG_SMP 995e7f75ad0SDave Kleikamp 996e7f75ad0SDave Kleikamp/* Entry point for secondary 47x processors */ 997e7f75ad0SDave Kleikamp_GLOBAL(start_secondary_47x) 998e7f75ad0SDave Kleikamp mr r24,r3 /* CPU number */ 999e7f75ad0SDave Kleikamp 1000e7f75ad0SDave Kleikamp bl init_cpu_state 1001e7f75ad0SDave Kleikamp 1002e7f75ad0SDave Kleikamp /* Now we need to bolt the rest of kernel memory which 1003e7f75ad0SDave Kleikamp * is done in C code. We must be careful because our task 1004e7f75ad0SDave Kleikamp * struct or our stack can (and will probably) be out 1005e7f75ad0SDave Kleikamp * of reach of the initial 256M TLB entry, so we use a 1006e7f75ad0SDave Kleikamp * small temporary stack in .bss for that. This works 1007e7f75ad0SDave Kleikamp * because only one CPU at a time can be in this code 1008e7f75ad0SDave Kleikamp */ 1009e7f75ad0SDave Kleikamp lis r1,temp_boot_stack@h 1010e7f75ad0SDave Kleikamp ori r1,r1,temp_boot_stack@l 1011e7f75ad0SDave Kleikamp addi r1,r1,1024-STACK_FRAME_OVERHEAD 1012e7f75ad0SDave Kleikamp li r0,0 1013e7f75ad0SDave Kleikamp stw r0,0(r1) 1014e7f75ad0SDave Kleikamp bl mmu_init_secondary 1015e7f75ad0SDave Kleikamp 1016e7f75ad0SDave Kleikamp /* Now we can get our task struct and real stack pointer */ 1017e7f75ad0SDave Kleikamp 10184e67bfd7SChristophe Leroy /* Get current's stack and current */ 10197c19c2e5SChristophe Leroy lis r2,secondary_current@ha 10207c19c2e5SChristophe Leroy lwz r2,secondary_current@l(r2) 1021ed1cd6deSChristophe Leroy lwz r1,TASK_STACK(r2) 1022e7f75ad0SDave Kleikamp 1023e7f75ad0SDave Kleikamp /* Current stack pointer */ 1024e7f75ad0SDave Kleikamp addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1025e7f75ad0SDave Kleikamp li r0,0 1026e7f75ad0SDave Kleikamp stw r0,0(r1) 1027e7f75ad0SDave Kleikamp 1028e7f75ad0SDave Kleikamp /* Kernel stack for exception entry in SPRG3 */ 1029e7f75ad0SDave Kleikamp addi r4,r2,THREAD /* init task's THREAD */ 1030e7f75ad0SDave Kleikamp mtspr SPRN_SPRG3,r4 1031e7f75ad0SDave Kleikamp 1032e7f75ad0SDave Kleikamp b start_secondary 1033e7f75ad0SDave Kleikamp 1034e7f75ad0SDave Kleikamp#endif /* CONFIG_SMP */ 1035e7f75ad0SDave Kleikamp 1036e7f75ad0SDave Kleikamp/* 1037e7f75ad0SDave Kleikamp * Set up the initial MMU state for 44x 1038e7f75ad0SDave Kleikamp * 1039e7f75ad0SDave Kleikamp * We are still executing code at the virtual address 1040e7f75ad0SDave Kleikamp * mappings set by the firmware for the base of RAM. 1041e7f75ad0SDave Kleikamp */ 1042e7f75ad0SDave Kleikamp 1043e7f75ad0SDave Kleikamphead_start_47x: 1044e7f75ad0SDave Kleikamp /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ 1045e7f75ad0SDave Kleikamp mfspr r3,SPRN_PID /* Get PID */ 1046e7f75ad0SDave Kleikamp mfmsr r4 /* Get MSR */ 1047e7f75ad0SDave Kleikamp andi. r4,r4,MSR_IS@l /* TS=1? */ 1048e7f75ad0SDave Kleikamp beq 1f /* If not, leave STS=0 */ 1049e7f75ad0SDave Kleikamp oris r3,r3,PPC47x_MMUCR_STS@h /* Set STS=1 */ 1050e7f75ad0SDave Kleikamp1: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ 1051e7f75ad0SDave Kleikamp sync 1052e7f75ad0SDave Kleikamp 1053e7f75ad0SDave Kleikamp /* Find the entry we are running from */ 1054e7f75ad0SDave Kleikamp bl 1f 1055e7f75ad0SDave Kleikamp1: mflr r23 1056e7f75ad0SDave Kleikamp tlbsx r23,0,r23 1057e7f75ad0SDave Kleikamp tlbre r24,r23,0 1058e7f75ad0SDave Kleikamp tlbre r25,r23,1 1059e7f75ad0SDave Kleikamp tlbre r26,r23,2 1060e7f75ad0SDave Kleikamp 1061e7f75ad0SDave Kleikamp/* 1062e7f75ad0SDave Kleikamp * Cleanup time 1063e7f75ad0SDave Kleikamp */ 1064e7f75ad0SDave Kleikamp 1065e7f75ad0SDave Kleikamp /* Initialize MMUCR */ 1066e7f75ad0SDave Kleikamp li r5,0 1067e7f75ad0SDave Kleikamp mtspr SPRN_MMUCR,r5 1068e7f75ad0SDave Kleikamp sync 1069e7f75ad0SDave Kleikamp 1070e7f75ad0SDave Kleikampclear_all_utlb_entries: 1071e7f75ad0SDave Kleikamp 1072e7f75ad0SDave Kleikamp #; Set initial values. 1073e7f75ad0SDave Kleikamp 1074e7f75ad0SDave Kleikamp addis r3,0,0x8000 1075e7f75ad0SDave Kleikamp addi r4,0,0 1076e7f75ad0SDave Kleikamp addi r5,0,0 1077e7f75ad0SDave Kleikamp b clear_utlb_entry 1078e7f75ad0SDave Kleikamp 1079e7f75ad0SDave Kleikamp #; Align the loop to speed things up. 1080e7f75ad0SDave Kleikamp 1081e7f75ad0SDave Kleikamp .align 6 1082e7f75ad0SDave Kleikamp 1083e7f75ad0SDave Kleikampclear_utlb_entry: 1084e7f75ad0SDave Kleikamp 1085e7f75ad0SDave Kleikamp tlbwe r4,r3,0 1086e7f75ad0SDave Kleikamp tlbwe r5,r3,1 1087e7f75ad0SDave Kleikamp tlbwe r5,r3,2 1088e7f75ad0SDave Kleikamp addis r3,r3,0x2000 1089e7f75ad0SDave Kleikamp cmpwi r3,0 1090e7f75ad0SDave Kleikamp bne clear_utlb_entry 1091e7f75ad0SDave Kleikamp addis r3,0,0x8000 1092e7f75ad0SDave Kleikamp addis r4,r4,0x100 1093e7f75ad0SDave Kleikamp cmpwi r4,0 1094e7f75ad0SDave Kleikamp bne clear_utlb_entry 1095e7f75ad0SDave Kleikamp 1096e7f75ad0SDave Kleikamp #; Restore original entry. 1097e7f75ad0SDave Kleikamp 1098e7f75ad0SDave Kleikamp oris r23,r23,0x8000 /* specify the way */ 1099e7f75ad0SDave Kleikamp tlbwe r24,r23,0 1100e7f75ad0SDave Kleikamp tlbwe r25,r23,1 1101e7f75ad0SDave Kleikamp tlbwe r26,r23,2 1102e7f75ad0SDave Kleikamp 1103e7f75ad0SDave Kleikamp/* 1104e7f75ad0SDave Kleikamp * Configure and load pinned entry into TLB for the kernel core 1105e7f75ad0SDave Kleikamp */ 1106e7f75ad0SDave Kleikamp 1107e7f75ad0SDave Kleikamp lis r3,PAGE_OFFSET@h 1108e7f75ad0SDave Kleikamp ori r3,r3,PAGE_OFFSET@l 1109e7f75ad0SDave Kleikamp 1110e7f75ad0SDave Kleikamp /* Load the kernel PID = 0 */ 1111e7f75ad0SDave Kleikamp li r0,0 1112e7f75ad0SDave Kleikamp mtspr SPRN_PID,r0 1113e7f75ad0SDave Kleikamp sync 1114e7f75ad0SDave Kleikamp 1115e7f75ad0SDave Kleikamp /* Word 0 */ 1116e7f75ad0SDave Kleikamp clrrwi r3,r3,12 /* Mask off the effective page number */ 1117e7f75ad0SDave Kleikamp ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M 1118e7f75ad0SDave Kleikamp 11199661534dSDave Kleikamp /* Word 1 - use r25. RPN is the same as the original entry */ 11209661534dSDave Kleikamp 1121e7f75ad0SDave Kleikamp /* Word 2 */ 1122e7f75ad0SDave Kleikamp li r5,0 1123e7f75ad0SDave Kleikamp ori r5,r5,PPC47x_TLB2_S_RWX 1124e7f75ad0SDave Kleikamp#ifdef CONFIG_SMP 1125e7f75ad0SDave Kleikamp ori r5,r5,PPC47x_TLB2_M 1126e7f75ad0SDave Kleikamp#endif 1127e7f75ad0SDave Kleikamp 1128e7f75ad0SDave Kleikamp /* We write to way 0 and bolted 0 */ 1129e7f75ad0SDave Kleikamp lis r0,0x8800 1130e7f75ad0SDave Kleikamp tlbwe r3,r0,0 11319661534dSDave Kleikamp tlbwe r25,r0,1 1132e7f75ad0SDave Kleikamp tlbwe r5,r0,2 1133e7f75ad0SDave Kleikamp 1134e7f75ad0SDave Kleikamp/* 1135e7f75ad0SDave Kleikamp * Configure SSPCR, ISPCR and USPCR for now to search everything, we can fix 1136e7f75ad0SDave Kleikamp * them up later 1137e7f75ad0SDave Kleikamp */ 1138e7f75ad0SDave Kleikamp LOAD_REG_IMMEDIATE(r3, 0x9abcdef0) 1139e7f75ad0SDave Kleikamp mtspr SPRN_SSPCR,r3 1140e7f75ad0SDave Kleikamp mtspr SPRN_USPCR,r3 1141e7f75ad0SDave Kleikamp LOAD_REG_IMMEDIATE(r3, 0x12345670) 1142e7f75ad0SDave Kleikamp mtspr SPRN_ISPCR,r3 1143e7f75ad0SDave Kleikamp 1144e7f75ad0SDave Kleikamp /* Force context change */ 1145e7f75ad0SDave Kleikamp mfmsr r0 1146e7f75ad0SDave Kleikamp mtspr SPRN_SRR1, r0 1147e7f75ad0SDave Kleikamp lis r0,3f@h 1148e7f75ad0SDave Kleikamp ori r0,r0,3f@l 1149e7f75ad0SDave Kleikamp mtspr SPRN_SRR0,r0 1150e7f75ad0SDave Kleikamp sync 1151e7f75ad0SDave Kleikamp rfi 1152e7f75ad0SDave Kleikamp 1153e7f75ad0SDave Kleikamp /* Invalidate original entry we used */ 1154e7f75ad0SDave Kleikamp3: 1155e7f75ad0SDave Kleikamp rlwinm r24,r24,0,21,19 /* clear the "valid" bit */ 1156e7f75ad0SDave Kleikamp tlbwe r24,r23,0 1157e7f75ad0SDave Kleikamp addi r24,0,0 1158e7f75ad0SDave Kleikamp tlbwe r24,r23,1 1159e7f75ad0SDave Kleikamp tlbwe r24,r23,2 1160e7f75ad0SDave Kleikamp isync /* Clear out the shadow TLB entries */ 1161e7f75ad0SDave Kleikamp 1162e7f75ad0SDave Kleikamp#ifdef CONFIG_PPC_EARLY_DEBUG_44x 1163e7f75ad0SDave Kleikamp /* Add UART mapping for early debug. */ 1164e7f75ad0SDave Kleikamp 1165e7f75ad0SDave Kleikamp /* Word 0 */ 1166e7f75ad0SDave Kleikamp lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h 1167e7f75ad0SDave Kleikamp ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M 1168e7f75ad0SDave Kleikamp 1169e7f75ad0SDave Kleikamp /* Word 1 */ 1170e7f75ad0SDave Kleikamp lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h 1171e7f75ad0SDave Kleikamp ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH 1172e7f75ad0SDave Kleikamp 1173e7f75ad0SDave Kleikamp /* Word 2 */ 1174e7f75ad0SDave Kleikamp li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG) 1175e7f75ad0SDave Kleikamp 1176e7f75ad0SDave Kleikamp /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same 1177e7f75ad0SDave Kleikamp * congruence class as the kernel, we need to make sure of it at 1178e7f75ad0SDave Kleikamp * some point 1179e7f75ad0SDave Kleikamp */ 1180e7f75ad0SDave Kleikamp lis r0,0x8d00 1181e7f75ad0SDave Kleikamp tlbwe r3,r0,0 1182e7f75ad0SDave Kleikamp tlbwe r4,r0,1 1183e7f75ad0SDave Kleikamp tlbwe r5,r0,2 1184e7f75ad0SDave Kleikamp 1185e7f75ad0SDave Kleikamp /* Force context change */ 1186e7f75ad0SDave Kleikamp isync 1187e7f75ad0SDave Kleikamp#endif /* CONFIG_PPC_EARLY_DEBUG_44x */ 1188e7f75ad0SDave Kleikamp 1189e7f75ad0SDave Kleikamp /* Establish the interrupt vector offsets */ 1190e7f75ad0SDave Kleikamp SET_IVOR(0, CriticalInput); 1191e7f75ad0SDave Kleikamp SET_IVOR(1, MachineCheckA); 1192e7f75ad0SDave Kleikamp SET_IVOR(2, DataStorage); 1193e7f75ad0SDave Kleikamp SET_IVOR(3, InstructionStorage); 1194e7f75ad0SDave Kleikamp SET_IVOR(4, ExternalInput); 1195e7f75ad0SDave Kleikamp SET_IVOR(5, Alignment); 1196e7f75ad0SDave Kleikamp SET_IVOR(6, Program); 1197e7f75ad0SDave Kleikamp SET_IVOR(7, FloatingPointUnavailable); 1198e7f75ad0SDave Kleikamp SET_IVOR(8, SystemCall); 1199e7f75ad0SDave Kleikamp SET_IVOR(9, AuxillaryProcessorUnavailable); 1200e7f75ad0SDave Kleikamp SET_IVOR(10, Decrementer); 1201e7f75ad0SDave Kleikamp SET_IVOR(11, FixedIntervalTimer); 1202e7f75ad0SDave Kleikamp SET_IVOR(12, WatchdogTimer); 1203e7f75ad0SDave Kleikamp SET_IVOR(13, DataTLBError47x); 1204e7f75ad0SDave Kleikamp SET_IVOR(14, InstructionTLBError47x); 1205e7f75ad0SDave Kleikamp SET_IVOR(15, DebugCrit); 1206e7f75ad0SDave Kleikamp 1207e7f75ad0SDave Kleikamp /* We configure icbi to invalidate 128 bytes at a time since the 1208e7f75ad0SDave Kleikamp * current 32-bit kernel code isn't too happy with icache != dcache 120997b3be1eSAlistair Popple * block size. We also disable the BTAC as this can cause errors 121097b3be1eSAlistair Popple * in some circumstances (see IBM Erratum 47). 1211e7f75ad0SDave Kleikamp */ 1212e7f75ad0SDave Kleikamp mfspr r3,SPRN_CCR0 1213e7f75ad0SDave Kleikamp oris r3,r3,0x0020 121497b3be1eSAlistair Popple ori r3,r3,0x0040 1215e7f75ad0SDave Kleikamp mtspr SPRN_CCR0,r3 1216e7f75ad0SDave Kleikamp isync 1217e7f75ad0SDave Kleikamp 1218e7f75ad0SDave Kleikamp#endif /* CONFIG_PPC_47x */ 1219e7f75ad0SDave Kleikamp 1220e7f75ad0SDave Kleikamp/* 1221e7f75ad0SDave Kleikamp * Here we are back to code that is common between 44x and 47x 1222e7f75ad0SDave Kleikamp * 1223e7f75ad0SDave Kleikamp * We proceed to further kernel initialization and return to the 1224e7f75ad0SDave Kleikamp * main kernel entry 1225e7f75ad0SDave Kleikamp */ 1226e7f75ad0SDave Kleikamphead_start_common: 1227795033c3SDave Kleikamp /* Establish the interrupt vector base */ 1228795033c3SDave Kleikamp lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 1229795033c3SDave Kleikamp mtspr SPRN_IVPR,r4 1230795033c3SDave Kleikamp 12319661534dSDave Kleikamp /* 12329661534dSDave Kleikamp * If the kernel was loaded at a non-zero 256 MB page, we need to 12339661534dSDave Kleikamp * mask off the most significant 4 bits to get the relative address 12349661534dSDave Kleikamp * from the start of physical memory 12359661534dSDave Kleikamp */ 12369661534dSDave Kleikamp rlwinm r22,r22,0,4,31 12379661534dSDave Kleikamp addis r22,r22,PAGE_OFFSET@h 1238795033c3SDave Kleikamp mtlr r22 1239e7f75ad0SDave Kleikamp isync 1240795033c3SDave Kleikamp blr 1241795033c3SDave Kleikamp 1242795033c3SDave Kleikamp/* 124314cf11afSPaul Mackerras * We put a few things here that have to be page-aligned. This stuff 124414cf11afSPaul Mackerras * goes at the beginning of the data segment, which is page-aligned. 124514cf11afSPaul Mackerras */ 124614cf11afSPaul Mackerras .data 1247ca9153a3SIlya Yanok .align PAGE_SHIFT 1248ea703ce2SKumar Gala .globl sdata 1249ea703ce2SKumar Galasdata: 1250ea703ce2SKumar Gala .globl empty_zero_page 1251ea703ce2SKumar Galaempty_zero_page: 1252ca9153a3SIlya Yanok .space PAGE_SIZE 12539445aa1aSAl ViroEXPORT_SYMBOL(empty_zero_page) 125414cf11afSPaul Mackerras 125514cf11afSPaul Mackerras/* 125614cf11afSPaul Mackerras * To support >32-bit physical addresses, we use an 8KB pgdir. 125714cf11afSPaul Mackerras */ 1258ea703ce2SKumar Gala .globl swapper_pg_dir 1259ea703ce2SKumar Galaswapper_pg_dir: 1260bee86f14SKumar Gala .space PGD_TABLE_SIZE 126114cf11afSPaul Mackerras 126214cf11afSPaul Mackerras/* 126314cf11afSPaul Mackerras * Room for two PTE pointers, usually the kernel and current user pointers 126414cf11afSPaul Mackerras * to their respective root page table. 126514cf11afSPaul Mackerras */ 126614cf11afSPaul Mackerrasabatron_pteptrs: 126714cf11afSPaul Mackerras .space 8 1268e7f75ad0SDave Kleikamp 1269e7f75ad0SDave Kleikamp#ifdef CONFIG_SMP 1270e7f75ad0SDave Kleikamp .align 12 1271e7f75ad0SDave Kleikamptemp_boot_stack: 1272e7f75ad0SDave Kleikamp .space 1024 1273e7f75ad0SDave Kleikamp#endif /* CONFIG_SMP */ 1274