18a23fdecSChristophe Leroy /* SPDX-License-Identifier: GPL-2.0 */ 28a23fdecSChristophe Leroy #ifndef __HEAD_32_H__ 38a23fdecSChristophe Leroy #define __HEAD_32_H__ 48a23fdecSChristophe Leroy 58a23fdecSChristophe Leroy #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */ 68a23fdecSChristophe Leroy 78a23fdecSChristophe Leroy /* 88a23fdecSChristophe Leroy * Exception entry code. This code runs with address translation 98a23fdecSChristophe Leroy * turned off, i.e. using physical addresses. 108a23fdecSChristophe Leroy * We assume sprg3 has the physical address of the current 118a23fdecSChristophe Leroy * task's thread_struct. 128a23fdecSChristophe Leroy */ 1302847487SChristophe Leroy .macro EXCEPTION_PROLOG handle_dar_dsisr=0 1402847487SChristophe Leroy EXCEPTION_PROLOG_0 handle_dar_dsisr=\handle_dar_dsisr 151f1c4d01SChristophe Leroy EXCEPTION_PROLOG_1 1602847487SChristophe Leroy EXCEPTION_PROLOG_2 handle_dar_dsisr=\handle_dar_dsisr 171f1c4d01SChristophe Leroy .endm 181f1c4d01SChristophe Leroy 1902847487SChristophe Leroy .macro EXCEPTION_PROLOG_0 handle_dar_dsisr=0 208a23fdecSChristophe Leroy mtspr SPRN_SPRG_SCRATCH0,r10 218a23fdecSChristophe Leroy mtspr SPRN_SPRG_SCRATCH1,r11 2202847487SChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 2302847487SChristophe Leroy .if \handle_dar_dsisr 240512aaddSChristophe Leroy #ifdef CONFIG_40x 250512aaddSChristophe Leroy mfspr r11, SPRN_DEAR 260512aaddSChristophe Leroy #else 2702847487SChristophe Leroy mfspr r11, SPRN_DAR 280512aaddSChristophe Leroy #endif 2902847487SChristophe Leroy stw r11, DAR(r10) 300512aaddSChristophe Leroy #ifdef CONFIG_40x 310512aaddSChristophe Leroy mfspr r11, SPRN_ESR 320512aaddSChristophe Leroy #else 3302847487SChristophe Leroy mfspr r11, SPRN_DSISR 340512aaddSChristophe Leroy #endif 3502847487SChristophe Leroy stw r11, DSISR(r10) 3602847487SChristophe Leroy .endif 3702847487SChristophe Leroy mfspr r11, SPRN_SRR0 3802847487SChristophe Leroy stw r11, SRR0(r10) 395ae8fabcSChristophe Leroy mfspr r11, SPRN_SRR1 /* check whether user or kernel */ 4002847487SChristophe Leroy stw r11, SRR1(r10) 418a23fdecSChristophe Leroy mfcr r10 425ae8fabcSChristophe Leroy andi. r11, r11, MSR_PR 438a23fdecSChristophe Leroy .endm 448a23fdecSChristophe Leroy 457aa8dd67SChristophe Leroy .macro EXCEPTION_PROLOG_1 46d2e00603SChristophe Leroy mtspr SPRN_SPRG_SCRATCH2,r1 47da7bb43aSChristophe Leroy subi r1, r1, INT_FRAME_SIZE /* use r1 if kernel */ 48da7bb43aSChristophe Leroy beq 1f 49da7bb43aSChristophe Leroy mfspr r1,SPRN_SPRG_THREAD 50da7bb43aSChristophe Leroy lwz r1,TASK_STACK-THREAD(r1) 51da7bb43aSChristophe Leroy addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE 526285f9cfSChristophe Leroy 1: 537aa8dd67SChristophe Leroy #ifdef CONFIG_VMAP_STACK 543642eb21SChristophe Leroy mtcrf 0x3f, r1 556285f9cfSChristophe Leroy bt 32 - THREAD_ALIGN_SHIFT, stack_overflow 563978eb78SChristophe Leroy #endif 578a23fdecSChristophe Leroy .endm 588a23fdecSChristophe Leroy 5902847487SChristophe Leroy .macro EXCEPTION_PROLOG_2 handle_dar_dsisr=0 605b1c9a0dSChristophe Leroy #ifdef CONFIG_PPC_8xx 615b1c9a0dSChristophe Leroy .if \handle_dar_dsisr 625b1c9a0dSChristophe Leroy li r11, RPN_PATTERN 635b1c9a0dSChristophe Leroy mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */ 645b1c9a0dSChristophe Leroy .endif 655b1c9a0dSChristophe Leroy #endif 66*9b6150fbSChristophe Leroy LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~MSR_RI) /* re-enable MMU */ 67*9b6150fbSChristophe Leroy mtspr SPRN_SRR1, r11 68*9b6150fbSChristophe Leroy lis r11, 1f@h 69*9b6150fbSChristophe Leroy ori r11, r11, 1f@l 70*9b6150fbSChristophe Leroy mtspr SPRN_SRR0, r11 71d2e00603SChristophe Leroy mfspr r11, SPRN_SPRG_SCRATCH2 72*9b6150fbSChristophe Leroy rfi 73*9b6150fbSChristophe Leroy 1: 74da7bb43aSChristophe Leroy stw r11,GPR1(r1) 75da7bb43aSChristophe Leroy stw r11,0(r1) 76da7bb43aSChristophe Leroy mr r11, r1 77d2e00603SChristophe Leroy stw r10,_CCR(r11) /* save registers */ 788a23fdecSChristophe Leroy stw r12,GPR12(r11) 798a23fdecSChristophe Leroy stw r9,GPR9(r11) 80d2e00603SChristophe Leroy mfspr r10,SPRN_SPRG_SCRATCH0 818a23fdecSChristophe Leroy mfspr r12,SPRN_SPRG_SCRATCH1 82d2e00603SChristophe Leroy stw r10,GPR10(r11) 838a23fdecSChristophe Leroy stw r12,GPR11(r11) 848a23fdecSChristophe Leroy mflr r10 858a23fdecSChristophe Leroy stw r10,_LINK(r11) 8602847487SChristophe Leroy mfspr r12, SPRN_SPRG_THREAD 8702847487SChristophe Leroy tovirt(r12, r12) 8802847487SChristophe Leroy .if \handle_dar_dsisr 8902847487SChristophe Leroy lwz r10, DAR(r12) 9002847487SChristophe Leroy stw r10, _DAR(r11) 9102847487SChristophe Leroy lwz r10, DSISR(r12) 9202847487SChristophe Leroy stw r10, _DSISR(r11) 9302847487SChristophe Leroy .endif 9402847487SChristophe Leroy lwz r9, SRR1(r12) 9502847487SChristophe Leroy lwz r12, SRR0(r12) 9690f204b9SChristophe Leroy #ifdef CONFIG_40x 9790f204b9SChristophe Leroy rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ 98e464d92bSChristophe Leroy #elif defined(CONFIG_PPC_8xx) 99e464d92bSChristophe Leroy mtspr SPRN_EID, r2 /* Set MSR_RI */ 10090f204b9SChristophe Leroy #else 101*9b6150fbSChristophe Leroy li r10, MSR_KERNEL /* can take exceptions */ 10239bccfd1SChristophe Leroy mtmsr r10 /* (except for mach check in rtas) */ 10390f204b9SChristophe Leroy #endif 1048a23fdecSChristophe Leroy stw r0,GPR0(r11) 1058a23fdecSChristophe Leroy lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ 1068a23fdecSChristophe Leroy addi r10,r10,STACK_FRAME_REGS_MARKER@l 1078a23fdecSChristophe Leroy stw r10,8(r11) 1088a23fdecSChristophe Leroy SAVE_4GPRS(3, r11) 1098a23fdecSChristophe Leroy SAVE_2GPRS(7, r11) 1108a23fdecSChristophe Leroy .endm 1118a23fdecSChristophe Leroy 112b86fb888SChristophe Leroy .macro SYSCALL_ENTRY trapno 1139e270862SChristophe Leroy mfspr r9, SPRN_SRR1 1142c59e510SChristophe Leroy mfspr r10, SPRN_SRR0 1152c59e510SChristophe Leroy LOAD_REG_IMMEDIATE(r11, MSR_KERNEL) /* can take exceptions */ 1162c59e510SChristophe Leroy lis r12, 1f@h 1172c59e510SChristophe Leroy ori r12, r12, 1f@l 1182c59e510SChristophe Leroy mtspr SPRN_SRR1, r11 1192c59e510SChristophe Leroy mtspr SPRN_SRR0, r12 1202c59e510SChristophe Leroy mfspr r12,SPRN_SPRG_THREAD 121d5c24398SChristophe Leroy mr r11, r1 122d5c24398SChristophe Leroy lwz r1,TASK_STACK-THREAD(r12) 1232c59e510SChristophe Leroy tovirt(r12, r12) 124d5c24398SChristophe Leroy addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE 12576249ddcSChristophe Leroy rfi 12676249ddcSChristophe Leroy 1: 127d5c24398SChristophe Leroy stw r11,GPR1(r1) 128d5c24398SChristophe Leroy stw r11,0(r1) 129d5c24398SChristophe Leroy mr r11, r1 1302c59e510SChristophe Leroy stw r10,_NIP(r11) 1319e270862SChristophe Leroy mflr r10 1329e270862SChristophe Leroy stw r10, _LINK(r11) 133c06f0affSChristophe Leroy mfcr r10 134c06f0affSChristophe Leroy rlwinm r10,r10,0,4,2 /* Clear SO bit in CR */ 135c06f0affSChristophe Leroy stw r10,_CCR(r11) /* save registers */ 136b86fb888SChristophe Leroy #ifdef CONFIG_40x 137b86fb888SChristophe Leroy rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ 138b86fb888SChristophe Leroy #endif 139b86fb888SChristophe Leroy lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ 140b86fb888SChristophe Leroy stw r2,GPR2(r11) 141b86fb888SChristophe Leroy addi r10,r10,STACK_FRAME_REGS_MARKER@l 142b86fb888SChristophe Leroy stw r9,_MSR(r11) 143fbcee2ebSChristophe Leroy li r2, \trapno 144b86fb888SChristophe Leroy stw r10,8(r11) 145b86fb888SChristophe Leroy stw r2,_TRAP(r11) 146b86fb888SChristophe Leroy SAVE_GPR(0, r11) 147b86fb888SChristophe Leroy SAVE_4GPRS(3, r11) 148b86fb888SChristophe Leroy SAVE_2GPRS(7, r11) 149b86fb888SChristophe Leroy addi r2,r12,-THREAD 15076249ddcSChristophe Leroy b transfer_to_syscall /* jump to handler */ 151b86fb888SChristophe Leroy .endm 152b86fb888SChristophe Leroy 1538a23fdecSChristophe Leroy /* 1548a23fdecSChristophe Leroy * Note: code which follows this uses cr0.eq (set if from kernel), 1558a23fdecSChristophe Leroy * r11, r12 (SRR0), and r9 (SRR1). 1568a23fdecSChristophe Leroy * 1578a23fdecSChristophe Leroy * Note2: once we have set r1 we are in a position to take exceptions 1588a23fdecSChristophe Leroy * again, and we could thus set MSR:RI at that point. 1598a23fdecSChristophe Leroy */ 1608a23fdecSChristophe Leroy 1618a23fdecSChristophe Leroy /* 1628a23fdecSChristophe Leroy * Exception vectors. 1638a23fdecSChristophe Leroy */ 1648a23fdecSChristophe Leroy #ifdef CONFIG_PPC_BOOK3S 1658a23fdecSChristophe Leroy #define START_EXCEPTION(n, label) \ 1668a23fdecSChristophe Leroy . = n; \ 1678a23fdecSChristophe Leroy DO_KVM n; \ 1688a23fdecSChristophe Leroy label: 1698a23fdecSChristophe Leroy 1708a23fdecSChristophe Leroy #else 1718a23fdecSChristophe Leroy #define START_EXCEPTION(n, label) \ 1728a23fdecSChristophe Leroy . = n; \ 1738a23fdecSChristophe Leroy label: 1748a23fdecSChristophe Leroy 1758a23fdecSChristophe Leroy #endif 1768a23fdecSChristophe Leroy 1778a23fdecSChristophe Leroy #define EXCEPTION(n, label, hdlr, xfer) \ 1788a23fdecSChristophe Leroy START_EXCEPTION(n, label) \ 1798a23fdecSChristophe Leroy EXCEPTION_PROLOG; \ 1808a23fdecSChristophe Leroy addi r3,r1,STACK_FRAME_OVERHEAD; \ 1818a23fdecSChristophe Leroy xfer(n, hdlr) 1828a23fdecSChristophe Leroy 1831ae99b4bSChristophe Leroy #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \ 1848a23fdecSChristophe Leroy li r10,trap; \ 1858a23fdecSChristophe Leroy stw r10,_TRAP(r11); \ 1868a23fdecSChristophe Leroy bl tfer; \ 1878a23fdecSChristophe Leroy .long hdlr; \ 1888a23fdecSChristophe Leroy .long ret 1898a23fdecSChristophe Leroy 1908a23fdecSChristophe Leroy #define EXC_XFER_STD(n, hdlr) \ 1911ae99b4bSChristophe Leroy EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \ 1928a23fdecSChristophe Leroy ret_from_except_full) 1938a23fdecSChristophe Leroy 1948a23fdecSChristophe Leroy #define EXC_XFER_LITE(n, hdlr) \ 1951ae99b4bSChristophe Leroy EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \ 1968a23fdecSChristophe Leroy ret_from_except) 1978a23fdecSChristophe Leroy 1983978eb78SChristophe Leroy .macro vmap_stack_overflow_exception 1993978eb78SChristophe Leroy #ifdef CONFIG_SMP 200da7bb43aSChristophe Leroy mfspr r1, SPRN_SPRG_THREAD 201da7bb43aSChristophe Leroy lwz r1, TASK_CPU - THREAD(r1) 202da7bb43aSChristophe Leroy slwi r1, r1, 3 203da7bb43aSChristophe Leroy addis r1, r1, emergency_ctx@ha 2043978eb78SChristophe Leroy #else 205da7bb43aSChristophe Leroy lis r1, emergency_ctx@ha 2063978eb78SChristophe Leroy #endif 207da7bb43aSChristophe Leroy lwz r1, emergency_ctx@l(r1) 208da7bb43aSChristophe Leroy cmpwi cr1, r1, 0 2093978eb78SChristophe Leroy bne cr1, 1f 210da7bb43aSChristophe Leroy lis r1, init_thread_union@ha 211da7bb43aSChristophe Leroy addi r1, r1, init_thread_union@l 212da7bb43aSChristophe Leroy 1: addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE 2133978eb78SChristophe Leroy EXCEPTION_PROLOG_2 2143978eb78SChristophe Leroy SAVE_NVGPRS(r11) 2153978eb78SChristophe Leroy addi r3, r1, STACK_FRAME_OVERHEAD 2163978eb78SChristophe Leroy EXC_XFER_STD(0, stack_overflow_exception) 2173978eb78SChristophe Leroy .endm 2183978eb78SChristophe Leroy 2198a23fdecSChristophe Leroy #endif /* __HEAD_32_H__ */ 220