18a23fdecSChristophe Leroy /* SPDX-License-Identifier: GPL-2.0 */ 28a23fdecSChristophe Leroy #ifndef __HEAD_32_H__ 38a23fdecSChristophe Leroy #define __HEAD_32_H__ 48a23fdecSChristophe Leroy 58a23fdecSChristophe Leroy #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */ 68a23fdecSChristophe Leroy 78a23fdecSChristophe Leroy /* 88a23fdecSChristophe Leroy * Exception entry code. This code runs with address translation 98a23fdecSChristophe Leroy * turned off, i.e. using physical addresses. 108a23fdecSChristophe Leroy * We assume sprg3 has the physical address of the current 118a23fdecSChristophe Leroy * task's thread_struct. 128a23fdecSChristophe Leroy */ 138a23fdecSChristophe Leroy 148a23fdecSChristophe Leroy .macro EXCEPTION_PROLOG 158a23fdecSChristophe Leroy mtspr SPRN_SPRG_SCRATCH0,r10 168a23fdecSChristophe Leroy mtspr SPRN_SPRG_SCRATCH1,r11 178a23fdecSChristophe Leroy mfcr r10 188a23fdecSChristophe Leroy EXCEPTION_PROLOG_1 198a23fdecSChristophe Leroy EXCEPTION_PROLOG_2 208a23fdecSChristophe Leroy .endm 218a23fdecSChristophe Leroy 228a23fdecSChristophe Leroy .macro EXCEPTION_PROLOG_1 238a23fdecSChristophe Leroy mfspr r11,SPRN_SRR1 /* check whether user or kernel */ 248a23fdecSChristophe Leroy andi. r11,r11,MSR_PR 258a23fdecSChristophe Leroy tophys(r11,r1) /* use tophys(r1) if kernel */ 268a23fdecSChristophe Leroy beq 1f 278a23fdecSChristophe Leroy mfspr r11,SPRN_SPRG_THREAD 288a23fdecSChristophe Leroy lwz r11,TASK_STACK-THREAD(r11) 298a23fdecSChristophe Leroy addi r11,r11,THREAD_SIZE 308a23fdecSChristophe Leroy tophys(r11,r11) 318a23fdecSChristophe Leroy 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 328a23fdecSChristophe Leroy .endm 338a23fdecSChristophe Leroy 348a23fdecSChristophe Leroy .macro EXCEPTION_PROLOG_2 358a23fdecSChristophe Leroy stw r10,_CCR(r11) /* save registers */ 368a23fdecSChristophe Leroy stw r12,GPR12(r11) 378a23fdecSChristophe Leroy stw r9,GPR9(r11) 388a23fdecSChristophe Leroy mfspr r10,SPRN_SPRG_SCRATCH0 398a23fdecSChristophe Leroy stw r10,GPR10(r11) 408a23fdecSChristophe Leroy mfspr r12,SPRN_SPRG_SCRATCH1 418a23fdecSChristophe Leroy stw r12,GPR11(r11) 428a23fdecSChristophe Leroy mflr r10 438a23fdecSChristophe Leroy stw r10,_LINK(r11) 448a23fdecSChristophe Leroy mfspr r12,SPRN_SRR0 458a23fdecSChristophe Leroy mfspr r9,SPRN_SRR1 468a23fdecSChristophe Leroy stw r1,GPR1(r11) 478a23fdecSChristophe Leroy stw r1,0(r11) 488a23fdecSChristophe Leroy tovirt(r1,r11) /* set new kernel sp */ 4990f204b9SChristophe Leroy #ifdef CONFIG_40x 5090f204b9SChristophe Leroy rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ 5190f204b9SChristophe Leroy #else 528a23fdecSChristophe Leroy li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR) /* can take exceptions */ 53*39bccfd1SChristophe Leroy mtmsr r10 /* (except for mach check in rtas) */ 5490f204b9SChristophe Leroy #endif 558a23fdecSChristophe Leroy stw r0,GPR0(r11) 568a23fdecSChristophe Leroy lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ 578a23fdecSChristophe Leroy addi r10,r10,STACK_FRAME_REGS_MARKER@l 588a23fdecSChristophe Leroy stw r10,8(r11) 598a23fdecSChristophe Leroy SAVE_4GPRS(3, r11) 608a23fdecSChristophe Leroy SAVE_2GPRS(7, r11) 618a23fdecSChristophe Leroy .endm 628a23fdecSChristophe Leroy 63b86fb888SChristophe Leroy .macro SYSCALL_ENTRY trapno 64b86fb888SChristophe Leroy mfspr r12,SPRN_SPRG_THREAD 65b86fb888SChristophe Leroy mfcr r10 66b86fb888SChristophe Leroy lwz r11,TASK_STACK-THREAD(r12) 67b86fb888SChristophe Leroy mflr r9 68b86fb888SChristophe Leroy addi r11,r11,THREAD_SIZE - INT_FRAME_SIZE 69b86fb888SChristophe Leroy rlwinm r10,r10,0,4,2 /* Clear SO bit in CR */ 70b86fb888SChristophe Leroy tophys(r11,r11) 71b86fb888SChristophe Leroy stw r10,_CCR(r11) /* save registers */ 72b86fb888SChristophe Leroy mfspr r10,SPRN_SRR0 73b86fb888SChristophe Leroy stw r9,_LINK(r11) 74b86fb888SChristophe Leroy mfspr r9,SPRN_SRR1 75b86fb888SChristophe Leroy stw r1,GPR1(r11) 76b86fb888SChristophe Leroy stw r1,0(r11) 77b86fb888SChristophe Leroy tovirt(r1,r11) /* set new kernel sp */ 78b86fb888SChristophe Leroy stw r10,_NIP(r11) 79b86fb888SChristophe Leroy #ifdef CONFIG_40x 80b86fb888SChristophe Leroy rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ 81b86fb888SChristophe Leroy #else 82ba18025fSChristophe Leroy LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */ 83*39bccfd1SChristophe Leroy mtmsr r10 /* (except for mach check in rtas) */ 84b86fb888SChristophe Leroy #endif 85b86fb888SChristophe Leroy lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ 86b86fb888SChristophe Leroy stw r2,GPR2(r11) 87b86fb888SChristophe Leroy addi r10,r10,STACK_FRAME_REGS_MARKER@l 88b86fb888SChristophe Leroy stw r9,_MSR(r11) 89b86fb888SChristophe Leroy li r2, \trapno + 1 90b86fb888SChristophe Leroy stw r10,8(r11) 91b86fb888SChristophe Leroy stw r2,_TRAP(r11) 92b86fb888SChristophe Leroy SAVE_GPR(0, r11) 93b86fb888SChristophe Leroy SAVE_4GPRS(3, r11) 94b86fb888SChristophe Leroy SAVE_2GPRS(7, r11) 95b86fb888SChristophe Leroy addi r11,r1,STACK_FRAME_OVERHEAD 96b86fb888SChristophe Leroy addi r2,r12,-THREAD 97b86fb888SChristophe Leroy stw r11,PT_REGS(r12) 98b86fb888SChristophe Leroy #if defined(CONFIG_40x) 99b86fb888SChristophe Leroy /* Check to see if the dbcr0 register is set up to debug. Use the 100b86fb888SChristophe Leroy internal debug mode bit to do this. */ 101b86fb888SChristophe Leroy lwz r12,THREAD_DBCR0(r12) 102b86fb888SChristophe Leroy andis. r12,r12,DBCR0_IDM@h 103b86fb888SChristophe Leroy #endif 104b86fb888SChristophe Leroy ACCOUNT_CPU_USER_ENTRY(r2, r11, r12) 105b86fb888SChristophe Leroy #if defined(CONFIG_40x) 106b86fb888SChristophe Leroy beq+ 3f 107b86fb888SChristophe Leroy /* From user and task is ptraced - load up global dbcr0 */ 108b86fb888SChristophe Leroy li r12,-1 /* clear all pending debug events */ 109b86fb888SChristophe Leroy mtspr SPRN_DBSR,r12 110b86fb888SChristophe Leroy lis r11,global_dbcr0@ha 111b86fb888SChristophe Leroy tophys(r11,r11) 112b86fb888SChristophe Leroy addi r11,r11,global_dbcr0@l 113b86fb888SChristophe Leroy lwz r12,0(r11) 114b86fb888SChristophe Leroy mtspr SPRN_DBCR0,r12 115b86fb888SChristophe Leroy lwz r12,4(r11) 116b86fb888SChristophe Leroy addi r12,r12,-1 117b86fb888SChristophe Leroy stw r12,4(r11) 118b86fb888SChristophe Leroy #endif 119b86fb888SChristophe Leroy 120b86fb888SChristophe Leroy 3: 121b86fb888SChristophe Leroy tovirt(r2, r2) /* set r2 to current */ 122b86fb888SChristophe Leroy lis r11, transfer_to_syscall@h 123b86fb888SChristophe Leroy ori r11, r11, transfer_to_syscall@l 124b86fb888SChristophe Leroy #ifdef CONFIG_TRACE_IRQFLAGS 125b86fb888SChristophe Leroy /* 126b86fb888SChristophe Leroy * If MSR is changing we need to keep interrupts disabled at this point 127b86fb888SChristophe Leroy * otherwise we might risk taking an interrupt before we tell lockdep 128b86fb888SChristophe Leroy * they are enabled. 129b86fb888SChristophe Leroy */ 130ba18025fSChristophe Leroy LOAD_REG_IMMEDIATE(r10, MSR_KERNEL) 131b86fb888SChristophe Leroy rlwimi r10, r9, 0, MSR_EE 132b86fb888SChristophe Leroy #else 133ba18025fSChristophe Leroy LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE) 134b86fb888SChristophe Leroy #endif 135b86fb888SChristophe Leroy #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 136b86fb888SChristophe Leroy mtspr SPRN_NRI, r0 137b86fb888SChristophe Leroy #endif 138b86fb888SChristophe Leroy mtspr SPRN_SRR1,r10 139b86fb888SChristophe Leroy mtspr SPRN_SRR0,r11 140b86fb888SChristophe Leroy SYNC 141b86fb888SChristophe Leroy RFI /* jump to handler, enable MMU */ 142b86fb888SChristophe Leroy .endm 143b86fb888SChristophe Leroy 1448a23fdecSChristophe Leroy /* 1458a23fdecSChristophe Leroy * Note: code which follows this uses cr0.eq (set if from kernel), 1468a23fdecSChristophe Leroy * r11, r12 (SRR0), and r9 (SRR1). 1478a23fdecSChristophe Leroy * 1488a23fdecSChristophe Leroy * Note2: once we have set r1 we are in a position to take exceptions 1498a23fdecSChristophe Leroy * again, and we could thus set MSR:RI at that point. 1508a23fdecSChristophe Leroy */ 1518a23fdecSChristophe Leroy 1528a23fdecSChristophe Leroy /* 1538a23fdecSChristophe Leroy * Exception vectors. 1548a23fdecSChristophe Leroy */ 1558a23fdecSChristophe Leroy #ifdef CONFIG_PPC_BOOK3S 1568a23fdecSChristophe Leroy #define START_EXCEPTION(n, label) \ 1578a23fdecSChristophe Leroy . = n; \ 1588a23fdecSChristophe Leroy DO_KVM n; \ 1598a23fdecSChristophe Leroy label: 1608a23fdecSChristophe Leroy 1618a23fdecSChristophe Leroy #else 1628a23fdecSChristophe Leroy #define START_EXCEPTION(n, label) \ 1638a23fdecSChristophe Leroy . = n; \ 1648a23fdecSChristophe Leroy label: 1658a23fdecSChristophe Leroy 1668a23fdecSChristophe Leroy #endif 1678a23fdecSChristophe Leroy 1688a23fdecSChristophe Leroy #define EXCEPTION(n, label, hdlr, xfer) \ 1698a23fdecSChristophe Leroy START_EXCEPTION(n, label) \ 1708a23fdecSChristophe Leroy EXCEPTION_PROLOG; \ 1718a23fdecSChristophe Leroy addi r3,r1,STACK_FRAME_OVERHEAD; \ 1728a23fdecSChristophe Leroy xfer(n, hdlr) 1738a23fdecSChristophe Leroy 1741ae99b4bSChristophe Leroy #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \ 1758a23fdecSChristophe Leroy li r10,trap; \ 1768a23fdecSChristophe Leroy stw r10,_TRAP(r11); \ 177ba18025fSChristophe Leroy LOAD_REG_IMMEDIATE(r10, msr); \ 1788a23fdecSChristophe Leroy bl tfer; \ 1798a23fdecSChristophe Leroy .long hdlr; \ 1808a23fdecSChristophe Leroy .long ret 1818a23fdecSChristophe Leroy 1828a23fdecSChristophe Leroy #define EXC_XFER_STD(n, hdlr) \ 1831ae99b4bSChristophe Leroy EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \ 1848a23fdecSChristophe Leroy ret_from_except_full) 1858a23fdecSChristophe Leroy 1868a23fdecSChristophe Leroy #define EXC_XFER_LITE(n, hdlr) \ 1871ae99b4bSChristophe Leroy EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \ 1888a23fdecSChristophe Leroy ret_from_except) 1898a23fdecSChristophe Leroy 1908a23fdecSChristophe Leroy #endif /* __HEAD_32_H__ */ 191