1/* 2 * Boot code and exception vectors for Book3E processors 3 * 4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <asm/reg.h> 14#include <asm/page.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cputable.h> 18#include <asm/setup.h> 19#include <asm/thread_info.h> 20#include <asm/reg_a2.h> 21#include <asm/exception-64e.h> 22#include <asm/bug.h> 23#include <asm/irqflags.h> 24#include <asm/ptrace.h> 25#include <asm/ppc-opcode.h> 26#include <asm/mmu.h> 27#include <asm/hw_irq.h> 28#include <asm/kvm_asm.h> 29#include <asm/kvm_booke_hv_asm.h> 30#include <asm/feature-fixups.h> 31 32/* XXX This will ultimately add space for a special exception save 33 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 34 * when taking special interrupts. For now we don't support that, 35 * special interrupts from within a non-standard level will probably 36 * blow you up 37 */ 38#define SPECIAL_EXC_SRR0 0 39#define SPECIAL_EXC_SRR1 1 40#define SPECIAL_EXC_SPRG_GEN 2 41#define SPECIAL_EXC_SPRG_TLB 3 42#define SPECIAL_EXC_MAS0 4 43#define SPECIAL_EXC_MAS1 5 44#define SPECIAL_EXC_MAS2 6 45#define SPECIAL_EXC_MAS3 7 46#define SPECIAL_EXC_MAS6 8 47#define SPECIAL_EXC_MAS7 9 48#define SPECIAL_EXC_MAS5 10 /* E.HV only */ 49#define SPECIAL_EXC_MAS8 11 /* E.HV only */ 50#define SPECIAL_EXC_IRQHAPPENED 12 51#define SPECIAL_EXC_DEAR 13 52#define SPECIAL_EXC_ESR 14 53#define SPECIAL_EXC_SOFTE 15 54#define SPECIAL_EXC_CSRR0 16 55#define SPECIAL_EXC_CSRR1 17 56/* must be even to keep 16-byte stack alignment */ 57#define SPECIAL_EXC_END 18 58 59#define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8) 60#define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288) 61 62#define SPECIAL_EXC_STORE(reg, name) \ 63 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 64 65#define SPECIAL_EXC_LOAD(reg, name) \ 66 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 67 68special_reg_save: 69 lbz r9,PACAIRQHAPPENED(r13) 70 RECONCILE_IRQ_STATE(r3,r4) 71 72 /* 73 * We only need (or have stack space) to save this stuff if 74 * we interrupted the kernel. 75 */ 76 ld r3,_MSR(r1) 77 andi. r3,r3,MSR_PR 78 bnelr 79 80 /* 81 * Advance to the next TLB exception frame for handler 82 * types that don't do it automatically. 83 */ 84 LOAD_REG_ADDR(r11,extlb_level_exc) 85 lwz r12,0(r11) 86 mfspr r10,SPRN_SPRG_TLB_EXFRAME 87 add r10,r10,r12 88 mtspr SPRN_SPRG_TLB_EXFRAME,r10 89 90 /* 91 * Save registers needed to allow nesting of certain exceptions 92 * (such as TLB misses) inside special exception levels 93 */ 94 mfspr r10,SPRN_SRR0 95 SPECIAL_EXC_STORE(r10,SRR0) 96 mfspr r10,SPRN_SRR1 97 SPECIAL_EXC_STORE(r10,SRR1) 98 mfspr r10,SPRN_SPRG_GEN_SCRATCH 99 SPECIAL_EXC_STORE(r10,SPRG_GEN) 100 mfspr r10,SPRN_SPRG_TLB_SCRATCH 101 SPECIAL_EXC_STORE(r10,SPRG_TLB) 102 mfspr r10,SPRN_MAS0 103 SPECIAL_EXC_STORE(r10,MAS0) 104 mfspr r10,SPRN_MAS1 105 SPECIAL_EXC_STORE(r10,MAS1) 106 mfspr r10,SPRN_MAS2 107 SPECIAL_EXC_STORE(r10,MAS2) 108 mfspr r10,SPRN_MAS3 109 SPECIAL_EXC_STORE(r10,MAS3) 110 mfspr r10,SPRN_MAS6 111 SPECIAL_EXC_STORE(r10,MAS6) 112 mfspr r10,SPRN_MAS7 113 SPECIAL_EXC_STORE(r10,MAS7) 114BEGIN_FTR_SECTION 115 mfspr r10,SPRN_MAS5 116 SPECIAL_EXC_STORE(r10,MAS5) 117 mfspr r10,SPRN_MAS8 118 SPECIAL_EXC_STORE(r10,MAS8) 119 120 /* MAS5/8 could have inappropriate values if we interrupted KVM code */ 121 li r10,0 122 mtspr SPRN_MAS5,r10 123 mtspr SPRN_MAS8,r10 124END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 125 SPECIAL_EXC_STORE(r9,IRQHAPPENED) 126 127 mfspr r10,SPRN_DEAR 128 SPECIAL_EXC_STORE(r10,DEAR) 129 mfspr r10,SPRN_ESR 130 SPECIAL_EXC_STORE(r10,ESR) 131 132 lbz r10,PACAIRQSOFTMASK(r13) 133 SPECIAL_EXC_STORE(r10,SOFTE) 134 ld r10,_NIP(r1) 135 SPECIAL_EXC_STORE(r10,CSRR0) 136 ld r10,_MSR(r1) 137 SPECIAL_EXC_STORE(r10,CSRR1) 138 139 blr 140 141ret_from_level_except: 142 ld r3,_MSR(r1) 143 andi. r3,r3,MSR_PR 144 beq 1f 145 b ret_from_except 1461: 147 148 LOAD_REG_ADDR(r11,extlb_level_exc) 149 lwz r12,0(r11) 150 mfspr r10,SPRN_SPRG_TLB_EXFRAME 151 sub r10,r10,r12 152 mtspr SPRN_SPRG_TLB_EXFRAME,r10 153 154 /* 155 * It's possible that the special level exception interrupted a 156 * TLB miss handler, and inserted the same entry that the 157 * interrupted handler was about to insert. On CPUs without TLB 158 * write conditional, this can result in a duplicate TLB entry. 159 * Wipe all non-bolted entries to be safe. 160 * 161 * Note that this doesn't protect against any TLB misses 162 * we may take accessing the stack from here to the end of 163 * the special level exception. It's not clear how we can 164 * reasonably protect against that, but only CPUs with 165 * neither TLB write conditional nor bolted kernel memory 166 * are affected. Do any such CPUs even exist? 167 */ 168 PPC_TLBILX_ALL(0,R0) 169 170 REST_NVGPRS(r1) 171 172 SPECIAL_EXC_LOAD(r10,SRR0) 173 mtspr SPRN_SRR0,r10 174 SPECIAL_EXC_LOAD(r10,SRR1) 175 mtspr SPRN_SRR1,r10 176 SPECIAL_EXC_LOAD(r10,SPRG_GEN) 177 mtspr SPRN_SPRG_GEN_SCRATCH,r10 178 SPECIAL_EXC_LOAD(r10,SPRG_TLB) 179 mtspr SPRN_SPRG_TLB_SCRATCH,r10 180 SPECIAL_EXC_LOAD(r10,MAS0) 181 mtspr SPRN_MAS0,r10 182 SPECIAL_EXC_LOAD(r10,MAS1) 183 mtspr SPRN_MAS1,r10 184 SPECIAL_EXC_LOAD(r10,MAS2) 185 mtspr SPRN_MAS2,r10 186 SPECIAL_EXC_LOAD(r10,MAS3) 187 mtspr SPRN_MAS3,r10 188 SPECIAL_EXC_LOAD(r10,MAS6) 189 mtspr SPRN_MAS6,r10 190 SPECIAL_EXC_LOAD(r10,MAS7) 191 mtspr SPRN_MAS7,r10 192BEGIN_FTR_SECTION 193 SPECIAL_EXC_LOAD(r10,MAS5) 194 mtspr SPRN_MAS5,r10 195 SPECIAL_EXC_LOAD(r10,MAS8) 196 mtspr SPRN_MAS8,r10 197END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 198 199 lbz r6,PACAIRQSOFTMASK(r13) 200 ld r5,SOFTE(r1) 201 202 /* Interrupts had better not already be enabled... */ 203 tweqi r6,IRQS_ENABLED 204 205 andi. r6,r5,IRQS_DISABLED 206 bne 1f 207 208 TRACE_ENABLE_INTS 209 stb r5,PACAIRQSOFTMASK(r13) 2101: 211 /* 212 * Restore PACAIRQHAPPENED rather than setting it based on 213 * the return MSR[EE], since we could have interrupted 214 * __check_irq_replay() or other inconsistent transitory 215 * states that must remain that way. 216 */ 217 SPECIAL_EXC_LOAD(r10,IRQHAPPENED) 218 stb r10,PACAIRQHAPPENED(r13) 219 220 SPECIAL_EXC_LOAD(r10,DEAR) 221 mtspr SPRN_DEAR,r10 222 SPECIAL_EXC_LOAD(r10,ESR) 223 mtspr SPRN_ESR,r10 224 225 stdcx. r0,0,r1 /* to clear the reservation */ 226 227 REST_4GPRS(2, r1) 228 REST_4GPRS(6, r1) 229 230 ld r10,_CTR(r1) 231 ld r11,_XER(r1) 232 mtctr r10 233 mtxer r11 234 235 blr 236 237.macro ret_from_level srr0 srr1 paca_ex scratch 238 bl ret_from_level_except 239 240 ld r10,_LINK(r1) 241 ld r11,_CCR(r1) 242 ld r0,GPR13(r1) 243 mtlr r10 244 mtcr r11 245 246 ld r10,GPR10(r1) 247 ld r11,GPR11(r1) 248 ld r12,GPR12(r1) 249 mtspr \scratch,r0 250 251 std r10,\paca_ex+EX_R10(r13); 252 std r11,\paca_ex+EX_R11(r13); 253 ld r10,_NIP(r1) 254 ld r11,_MSR(r1) 255 ld r0,GPR0(r1) 256 ld r1,GPR1(r1) 257 mtspr \srr0,r10 258 mtspr \srr1,r11 259 ld r10,\paca_ex+EX_R10(r13) 260 ld r11,\paca_ex+EX_R11(r13) 261 mfspr r13,\scratch 262.endm 263 264ret_from_crit_except: 265 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH 266 rfci 267 268ret_from_mc_except: 269 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH 270 rfmci 271 272/* Exception prolog code for all exceptions */ 273#define EXCEPTION_PROLOG(n, intnum, type, addition) \ 274 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 275 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 276 std r10,PACA_EX##type+EX_R10(r13); \ 277 std r11,PACA_EX##type+EX_R11(r13); \ 278 mfcr r10; /* save CR */ \ 279 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 280 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ 281 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 282 addition; /* additional code for that exc. */ \ 283 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 284 type##_SET_KSTACK; /* get special stack if necessary */\ 285 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 286 beq 1f; /* branch around if supervisor */ \ 287 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 2881: type##_BTB_FLUSH \ 289 cmpdi cr1,r1,0; /* check if SP makes sense */ \ 290 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 291 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 292 293/* Exception type-specific macros */ 294#define GEN_SET_KSTACK \ 295 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 296#define SPRN_GEN_SRR0 SPRN_SRR0 297#define SPRN_GEN_SRR1 SPRN_SRR1 298 299#define GDBELL_SET_KSTACK GEN_SET_KSTACK 300#define SPRN_GDBELL_SRR0 SPRN_GSRR0 301#define SPRN_GDBELL_SRR1 SPRN_GSRR1 302 303#define CRIT_SET_KSTACK \ 304 ld r1,PACA_CRIT_STACK(r13); \ 305 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 306#define SPRN_CRIT_SRR0 SPRN_CSRR0 307#define SPRN_CRIT_SRR1 SPRN_CSRR1 308 309#define DBG_SET_KSTACK \ 310 ld r1,PACA_DBG_STACK(r13); \ 311 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 312#define SPRN_DBG_SRR0 SPRN_DSRR0 313#define SPRN_DBG_SRR1 SPRN_DSRR1 314 315#define MC_SET_KSTACK \ 316 ld r1,PACA_MC_STACK(r13); \ 317 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 318#define SPRN_MC_SRR0 SPRN_MCSRR0 319#define SPRN_MC_SRR1 SPRN_MCSRR1 320 321#ifdef CONFIG_PPC_FSL_BOOK3E 322#define GEN_BTB_FLUSH \ 323 START_BTB_FLUSH_SECTION \ 324 beq 1f; \ 325 BTB_FLUSH(r10) \ 326 1: \ 327 END_BTB_FLUSH_SECTION 328 329#define CRIT_BTB_FLUSH \ 330 START_BTB_FLUSH_SECTION \ 331 BTB_FLUSH(r10) \ 332 END_BTB_FLUSH_SECTION 333 334#define DBG_BTB_FLUSH CRIT_BTB_FLUSH 335#define MC_BTB_FLUSH CRIT_BTB_FLUSH 336#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH 337#else 338#define GEN_BTB_FLUSH 339#define CRIT_BTB_FLUSH 340#define DBG_BTB_FLUSH 341#define GDBELL_BTB_FLUSH 342#endif 343 344#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 345 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) 346 347#define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ 348 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) 349 350#define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ 351 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) 352 353#define MC_EXCEPTION_PROLOG(n, intnum, addition) \ 354 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) 355 356#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ 357 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) 358 359/* Variants of the "addition" argument for the prolog 360 */ 361#define PROLOG_ADDITION_NONE_GEN(n) 362#define PROLOG_ADDITION_NONE_GDBELL(n) 363#define PROLOG_ADDITION_NONE_CRIT(n) 364#define PROLOG_ADDITION_NONE_DBG(n) 365#define PROLOG_ADDITION_NONE_MC(n) 366 367#define PROLOG_ADDITION_MASKABLE_GEN(n) \ 368 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \ 369 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \ 370 bne masked_interrupt_book3e_##n 371 372#define PROLOG_ADDITION_2REGS_GEN(n) \ 373 std r14,PACA_EXGEN+EX_R14(r13); \ 374 std r15,PACA_EXGEN+EX_R15(r13) 375 376#define PROLOG_ADDITION_1REG_GEN(n) \ 377 std r14,PACA_EXGEN+EX_R14(r13); 378 379#define PROLOG_ADDITION_2REGS_CRIT(n) \ 380 std r14,PACA_EXCRIT+EX_R14(r13); \ 381 std r15,PACA_EXCRIT+EX_R15(r13) 382 383#define PROLOG_ADDITION_2REGS_DBG(n) \ 384 std r14,PACA_EXDBG+EX_R14(r13); \ 385 std r15,PACA_EXDBG+EX_R15(r13) 386 387#define PROLOG_ADDITION_2REGS_MC(n) \ 388 std r14,PACA_EXMC+EX_R14(r13); \ 389 std r15,PACA_EXMC+EX_R15(r13) 390 391 392/* Core exception code for all exceptions except TLB misses. */ 393#define EXCEPTION_COMMON_LVL(n, scratch, excf) \ 394exc_##n##_common: \ 395 std r0,GPR0(r1); /* save r0 in stackframe */ \ 396 std r2,GPR2(r1); /* save r2 in stackframe */ \ 397 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 398 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 399 std r9,GPR9(r1); /* save r9 in stackframe */ \ 400 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 401 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 402 beq 2f; /* if from kernel mode */ \ 403 ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */ \ 4042: ld r3,excf+EX_R10(r13); /* get back r10 */ \ 405 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 406 mfspr r5,scratch; /* get back r13 */ \ 407 std r12,GPR12(r1); /* save r12 in stackframe */ \ 408 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 409 mflr r6; /* save LR in stackframe */ \ 410 mfctr r7; /* save CTR in stackframe */ \ 411 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 412 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 413 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 414 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \ 415 ld r12,exception_marker@toc(r2); \ 416 li r0,0; \ 417 std r3,GPR10(r1); /* save r10 to stackframe */ \ 418 std r4,GPR11(r1); /* save r11 to stackframe */ \ 419 std r5,GPR13(r1); /* save it to stackframe */ \ 420 std r6,_LINK(r1); \ 421 std r7,_CTR(r1); \ 422 std r8,_XER(r1); \ 423 li r3,(n)+1; /* indicate partial regs in trap */ \ 424 std r9,0(r1); /* store stack frame back link */ \ 425 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 426 std r9,GPR1(r1); /* store stack frame back link */ \ 427 std r11,SOFTE(r1); /* and save it to stackframe */ \ 428 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 429 std r3,_TRAP(r1); /* set trap number */ \ 430 std r0,RESULT(r1); /* clear regs->result */ 431 432#define EXCEPTION_COMMON(n) \ 433 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN) 434#define EXCEPTION_COMMON_CRIT(n) \ 435 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT) 436#define EXCEPTION_COMMON_MC(n) \ 437 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC) 438#define EXCEPTION_COMMON_DBG(n) \ 439 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG) 440 441/* 442 * This is meant for exceptions that don't immediately hard-enable. We 443 * set a bit in paca->irq_happened to ensure that a subsequent call to 444 * arch_local_irq_restore() will properly hard-enable and avoid the 445 * fast-path, and then reconcile irq state. 446 */ 447#define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4) 448 449/* 450 * This is called by exceptions that don't use INTS_DISABLE (that did not 451 * touch irq indicators in the PACA). This will restore MSR:EE to it's 452 * previous value 453 * 454 * XXX In the long run, we may want to open-code it in order to separate the 455 * load from the wrtee, thus limiting the latency caused by the dependency 456 * but at this point, I'll favor code clarity until we have a near to final 457 * implementation 458 */ 459#define INTS_RESTORE_HARD \ 460 ld r11,_MSR(r1); \ 461 wrtee r11; 462 463/* XXX FIXME: Restore r14/r15 when necessary */ 464#define BAD_STACK_TRAMPOLINE(n) \ 465exc_##n##_bad_stack: \ 466 li r1,(n); /* get exception number */ \ 467 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 468 b bad_stack_book3e; /* bad stack error */ 469 470/* WARNING: If you change the layout of this stub, make sure you check 471 * the debug exception handler which handles single stepping 472 * into exceptions from userspace, and the MM code in 473 * arch/powerpc/mm/tlb_nohash.c which patches the branch here 474 * and would need to be updated if that branch is moved 475 */ 476#define EXCEPTION_STUB(loc, label) \ 477 . = interrupt_base_book3e + loc; \ 478 nop; /* To make debug interrupts happy */ \ 479 b exc_##label##_book3e; 480 481#define ACK_NONE(r) 482#define ACK_DEC(r) \ 483 lis r,TSR_DIS@h; \ 484 mtspr SPRN_TSR,r 485#define ACK_FIT(r) \ 486 lis r,TSR_FIS@h; \ 487 mtspr SPRN_TSR,r 488 489/* Used by asynchronous interrupt that may happen in the idle loop. 490 * 491 * This check if the thread was in the idle loop, and if yes, returns 492 * to the caller rather than the PC. This is to avoid a race if 493 * interrupts happen before the wait instruction. 494 */ 495#define CHECK_NAPPING() \ 496 CURRENT_THREAD_INFO(r11, r1); \ 497 ld r10,TI_LOCAL_FLAGS(r11); \ 498 andi. r9,r10,_TLF_NAPPING; \ 499 beq+ 1f; \ 500 ld r8,_LINK(r1); \ 501 rlwinm r7,r10,0,~_TLF_NAPPING; \ 502 std r8,_NIP(r1); \ 503 std r7,TI_LOCAL_FLAGS(r11); \ 5041: 505 506 507#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ 508 START_EXCEPTION(label); \ 509 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ 510 EXCEPTION_COMMON(trapnum) \ 511 INTS_DISABLE; \ 512 ack(r8); \ 513 CHECK_NAPPING(); \ 514 addi r3,r1,STACK_FRAME_OVERHEAD; \ 515 bl hdlr; \ 516 b ret_from_except_lite; 517 518/* This value is used to mark exception frames on the stack. */ 519 .section ".toc","aw" 520exception_marker: 521 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 522 523 524/* 525 * And here we have the exception vectors ! 526 */ 527 528 .text 529 .balign 0x1000 530 .globl interrupt_base_book3e 531interrupt_base_book3e: /* fake trap */ 532 EXCEPTION_STUB(0x000, machine_check) 533 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */ 534 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 535 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 536 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 537 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 538 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 539 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 540 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 541 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 542 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 543 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 544 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 545 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 546 EXCEPTION_STUB(0x1c0, data_tlb_miss) 547 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 548 EXCEPTION_STUB(0x200, altivec_unavailable) 549 EXCEPTION_STUB(0x220, altivec_assist) 550 EXCEPTION_STUB(0x260, perfmon) 551 EXCEPTION_STUB(0x280, doorbell) 552 EXCEPTION_STUB(0x2a0, doorbell_crit) 553 EXCEPTION_STUB(0x2c0, guest_doorbell) 554 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 555 EXCEPTION_STUB(0x300, hypercall) 556 EXCEPTION_STUB(0x320, ehpriv) 557 EXCEPTION_STUB(0x340, lrat_error) 558 559 .globl __end_interrupts 560__end_interrupts: 561 562/* Critical Input Interrupt */ 563 START_EXCEPTION(critical_input); 564 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, 565 PROLOG_ADDITION_NONE) 566 EXCEPTION_COMMON_CRIT(0x100) 567 bl save_nvgprs 568 bl special_reg_save 569 CHECK_NAPPING(); 570 addi r3,r1,STACK_FRAME_OVERHEAD 571 bl unknown_exception 572 b ret_from_crit_except 573 574/* Machine Check Interrupt */ 575 START_EXCEPTION(machine_check); 576 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK, 577 PROLOG_ADDITION_NONE) 578 EXCEPTION_COMMON_MC(0x000) 579 bl save_nvgprs 580 bl special_reg_save 581 CHECK_NAPPING(); 582 addi r3,r1,STACK_FRAME_OVERHEAD 583 bl machine_check_exception 584 b ret_from_mc_except 585 586/* Data Storage Interrupt */ 587 START_EXCEPTION(data_storage) 588 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, 589 PROLOG_ADDITION_2REGS) 590 mfspr r14,SPRN_DEAR 591 mfspr r15,SPRN_ESR 592 EXCEPTION_COMMON(0x300) 593 INTS_DISABLE 594 b storage_fault_common 595 596/* Instruction Storage Interrupt */ 597 START_EXCEPTION(instruction_storage); 598 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, 599 PROLOG_ADDITION_2REGS) 600 li r15,0 601 mr r14,r10 602 EXCEPTION_COMMON(0x400) 603 INTS_DISABLE 604 b storage_fault_common 605 606/* External Input Interrupt */ 607 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, 608 external_input, do_IRQ, ACK_NONE) 609 610/* Alignment */ 611 START_EXCEPTION(alignment); 612 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, 613 PROLOG_ADDITION_2REGS) 614 mfspr r14,SPRN_DEAR 615 mfspr r15,SPRN_ESR 616 EXCEPTION_COMMON(0x600) 617 b alignment_more /* no room, go out of line */ 618 619/* Program Interrupt */ 620 START_EXCEPTION(program); 621 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, 622 PROLOG_ADDITION_1REG) 623 mfspr r14,SPRN_ESR 624 EXCEPTION_COMMON(0x700) 625 INTS_DISABLE 626 std r14,_DSISR(r1) 627 addi r3,r1,STACK_FRAME_OVERHEAD 628 ld r14,PACA_EXGEN+EX_R14(r13) 629 bl save_nvgprs 630 bl program_check_exception 631 b ret_from_except 632 633/* Floating Point Unavailable Interrupt */ 634 START_EXCEPTION(fp_unavailable); 635 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, 636 PROLOG_ADDITION_NONE) 637 /* we can probably do a shorter exception entry for that one... */ 638 EXCEPTION_COMMON(0x800) 639 ld r12,_MSR(r1) 640 andi. r0,r12,MSR_PR; 641 beq- 1f 642 bl load_up_fpu 643 b fast_exception_return 6441: INTS_DISABLE 645 bl save_nvgprs 646 addi r3,r1,STACK_FRAME_OVERHEAD 647 bl kernel_fp_unavailable_exception 648 b ret_from_except 649 650/* Altivec Unavailable Interrupt */ 651 START_EXCEPTION(altivec_unavailable); 652 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, 653 PROLOG_ADDITION_NONE) 654 /* we can probably do a shorter exception entry for that one... */ 655 EXCEPTION_COMMON(0x200) 656#ifdef CONFIG_ALTIVEC 657BEGIN_FTR_SECTION 658 ld r12,_MSR(r1) 659 andi. r0,r12,MSR_PR; 660 beq- 1f 661 bl load_up_altivec 662 b fast_exception_return 6631: 664END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 665#endif 666 INTS_DISABLE 667 bl save_nvgprs 668 addi r3,r1,STACK_FRAME_OVERHEAD 669 bl altivec_unavailable_exception 670 b ret_from_except 671 672/* AltiVec Assist */ 673 START_EXCEPTION(altivec_assist); 674 NORMAL_EXCEPTION_PROLOG(0x220, 675 BOOKE_INTERRUPT_ALTIVEC_ASSIST, 676 PROLOG_ADDITION_NONE) 677 EXCEPTION_COMMON(0x220) 678 INTS_DISABLE 679 bl save_nvgprs 680 addi r3,r1,STACK_FRAME_OVERHEAD 681#ifdef CONFIG_ALTIVEC 682BEGIN_FTR_SECTION 683 bl altivec_assist_exception 684END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 685#else 686 bl unknown_exception 687#endif 688 b ret_from_except 689 690 691/* Decrementer Interrupt */ 692 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 693 decrementer, timer_interrupt, ACK_DEC) 694 695/* Fixed Interval Timer Interrupt */ 696 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, 697 fixed_interval, unknown_exception, ACK_FIT) 698 699/* Watchdog Timer Interrupt */ 700 START_EXCEPTION(watchdog); 701 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, 702 PROLOG_ADDITION_NONE) 703 EXCEPTION_COMMON_CRIT(0x9f0) 704 bl save_nvgprs 705 bl special_reg_save 706 CHECK_NAPPING(); 707 addi r3,r1,STACK_FRAME_OVERHEAD 708#ifdef CONFIG_BOOKE_WDT 709 bl WatchdogException 710#else 711 bl unknown_exception 712#endif 713 b ret_from_crit_except 714 715/* System Call Interrupt */ 716 START_EXCEPTION(system_call) 717 mr r9,r13 /* keep a copy of userland r13 */ 718 mfspr r11,SPRN_SRR0 /* get return address */ 719 mfspr r12,SPRN_SRR1 /* get previous MSR */ 720 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 721 b system_call_common 722 723/* Auxiliary Processor Unavailable Interrupt */ 724 START_EXCEPTION(ap_unavailable); 725 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, 726 PROLOG_ADDITION_NONE) 727 EXCEPTION_COMMON(0xf20) 728 INTS_DISABLE 729 bl save_nvgprs 730 addi r3,r1,STACK_FRAME_OVERHEAD 731 bl unknown_exception 732 b ret_from_except 733 734/* Debug exception as a critical interrupt*/ 735 START_EXCEPTION(debug_crit); 736 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 737 PROLOG_ADDITION_2REGS) 738 739 /* 740 * If there is a single step or branch-taken exception in an 741 * exception entry sequence, it was probably meant to apply to 742 * the code where the exception occurred (since exception entry 743 * doesn't turn off DE automatically). We simulate the effect 744 * of turning off DE on entry to an exception handler by turning 745 * off DE in the CSRR1 value and clearing the debug status. 746 */ 747 748 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 749 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 750 beq+ 1f 751 752#ifdef CONFIG_RELOCATABLE 753 ld r15,PACATOC(r13) 754 ld r14,interrupt_base_book3e@got(r15) 755 ld r15,__end_interrupts@got(r15) 756#else 757 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 758 LOAD_REG_IMMEDIATE(r15,__end_interrupts) 759#endif 760 cmpld cr0,r10,r14 761 cmpld cr1,r10,r15 762 blt+ cr0,1f 763 bge+ cr1,1f 764 765 /* here it looks like we got an inappropriate debug exception. */ 766 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 767 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 768 mtspr SPRN_DBSR,r14 769 mtspr SPRN_CSRR1,r11 770 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 771 ld r1,PACA_EXCRIT+EX_R1(r13) 772 ld r14,PACA_EXCRIT+EX_R14(r13) 773 ld r15,PACA_EXCRIT+EX_R15(r13) 774 mtcr r10 775 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 776 ld r11,PACA_EXCRIT+EX_R11(r13) 777 mfspr r13,SPRN_SPRG_CRIT_SCRATCH 778 rfci 779 780 /* Normal debug exception */ 781 /* XXX We only handle coming from userspace for now since we can't 782 * quite save properly an interrupted kernel state yet 783 */ 7841: andi. r14,r11,MSR_PR; /* check for userspace again */ 785 beq kernel_dbg_exc; /* if from kernel mode */ 786 787 /* Now we mash up things to make it look like we are coming on a 788 * normal exception 789 */ 790 mfspr r14,SPRN_DBSR 791 EXCEPTION_COMMON_CRIT(0xd00) 792 std r14,_DSISR(r1) 793 addi r3,r1,STACK_FRAME_OVERHEAD 794 mr r4,r14 795 ld r14,PACA_EXCRIT+EX_R14(r13) 796 ld r15,PACA_EXCRIT+EX_R15(r13) 797 bl save_nvgprs 798 bl DebugException 799 b ret_from_except 800 801kernel_dbg_exc: 802 b . /* NYI */ 803 804/* Debug exception as a debug interrupt*/ 805 START_EXCEPTION(debug_debug); 806 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 807 PROLOG_ADDITION_2REGS) 808 809 /* 810 * If there is a single step or branch-taken exception in an 811 * exception entry sequence, it was probably meant to apply to 812 * the code where the exception occurred (since exception entry 813 * doesn't turn off DE automatically). We simulate the effect 814 * of turning off DE on entry to an exception handler by turning 815 * off DE in the DSRR1 value and clearing the debug status. 816 */ 817 818 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 819 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 820 beq+ 1f 821 822#ifdef CONFIG_RELOCATABLE 823 ld r15,PACATOC(r13) 824 ld r14,interrupt_base_book3e@got(r15) 825 ld r15,__end_interrupts@got(r15) 826#else 827 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 828 LOAD_REG_IMMEDIATE(r15,__end_interrupts) 829#endif 830 cmpld cr0,r10,r14 831 cmpld cr1,r10,r15 832 blt+ cr0,1f 833 bge+ cr1,1f 834 835 /* here it looks like we got an inappropriate debug exception. */ 836 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 837 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ 838 mtspr SPRN_DBSR,r14 839 mtspr SPRN_DSRR1,r11 840 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ 841 ld r1,PACA_EXDBG+EX_R1(r13) 842 ld r14,PACA_EXDBG+EX_R14(r13) 843 ld r15,PACA_EXDBG+EX_R15(r13) 844 mtcr r10 845 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ 846 ld r11,PACA_EXDBG+EX_R11(r13) 847 mfspr r13,SPRN_SPRG_DBG_SCRATCH 848 rfdi 849 850 /* Normal debug exception */ 851 /* XXX We only handle coming from userspace for now since we can't 852 * quite save properly an interrupted kernel state yet 853 */ 8541: andi. r14,r11,MSR_PR; /* check for userspace again */ 855 beq kernel_dbg_exc; /* if from kernel mode */ 856 857 /* Now we mash up things to make it look like we are coming on a 858 * normal exception 859 */ 860 mfspr r14,SPRN_DBSR 861 EXCEPTION_COMMON_DBG(0xd08) 862 INTS_DISABLE 863 std r14,_DSISR(r1) 864 addi r3,r1,STACK_FRAME_OVERHEAD 865 mr r4,r14 866 ld r14,PACA_EXDBG+EX_R14(r13) 867 ld r15,PACA_EXDBG+EX_R15(r13) 868 bl save_nvgprs 869 bl DebugException 870 b ret_from_except 871 872 START_EXCEPTION(perfmon); 873 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, 874 PROLOG_ADDITION_NONE) 875 EXCEPTION_COMMON(0x260) 876 INTS_DISABLE 877 CHECK_NAPPING() 878 addi r3,r1,STACK_FRAME_OVERHEAD 879 bl performance_monitor_exception 880 b ret_from_except_lite 881 882/* Doorbell interrupt */ 883 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, 884 doorbell, doorbell_exception, ACK_NONE) 885 886/* Doorbell critical Interrupt */ 887 START_EXCEPTION(doorbell_crit); 888 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, 889 PROLOG_ADDITION_NONE) 890 EXCEPTION_COMMON_CRIT(0x2a0) 891 bl save_nvgprs 892 bl special_reg_save 893 CHECK_NAPPING(); 894 addi r3,r1,STACK_FRAME_OVERHEAD 895 bl unknown_exception 896 b ret_from_crit_except 897 898/* 899 * Guest doorbell interrupt 900 * This general exception use GSRRx save/restore registers 901 */ 902 START_EXCEPTION(guest_doorbell); 903 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, 904 PROLOG_ADDITION_NONE) 905 EXCEPTION_COMMON(0x2c0) 906 addi r3,r1,STACK_FRAME_OVERHEAD 907 bl save_nvgprs 908 INTS_RESTORE_HARD 909 bl unknown_exception 910 b ret_from_except 911 912/* Guest Doorbell critical Interrupt */ 913 START_EXCEPTION(guest_doorbell_crit); 914 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, 915 PROLOG_ADDITION_NONE) 916 EXCEPTION_COMMON_CRIT(0x2e0) 917 bl save_nvgprs 918 bl special_reg_save 919 CHECK_NAPPING(); 920 addi r3,r1,STACK_FRAME_OVERHEAD 921 bl unknown_exception 922 b ret_from_crit_except 923 924/* Hypervisor call */ 925 START_EXCEPTION(hypercall); 926 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, 927 PROLOG_ADDITION_NONE) 928 EXCEPTION_COMMON(0x310) 929 addi r3,r1,STACK_FRAME_OVERHEAD 930 bl save_nvgprs 931 INTS_RESTORE_HARD 932 bl unknown_exception 933 b ret_from_except 934 935/* Embedded Hypervisor priviledged */ 936 START_EXCEPTION(ehpriv); 937 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, 938 PROLOG_ADDITION_NONE) 939 EXCEPTION_COMMON(0x320) 940 addi r3,r1,STACK_FRAME_OVERHEAD 941 bl save_nvgprs 942 INTS_RESTORE_HARD 943 bl unknown_exception 944 b ret_from_except 945 946/* LRAT Error interrupt */ 947 START_EXCEPTION(lrat_error); 948 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, 949 PROLOG_ADDITION_NONE) 950 EXCEPTION_COMMON(0x340) 951 addi r3,r1,STACK_FRAME_OVERHEAD 952 bl save_nvgprs 953 INTS_RESTORE_HARD 954 bl unknown_exception 955 b ret_from_except 956 957/* 958 * An interrupt came in while soft-disabled; We mark paca->irq_happened 959 * accordingly and if the interrupt is level sensitive, we hard disable 960 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so 961 * keep these in synch. 962 */ 963 964.macro masked_interrupt_book3e paca_irq full_mask 965 lbz r10,PACAIRQHAPPENED(r13) 966 .if \full_mask == 1 967 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS 968 .else 969 ori r10,r10,\paca_irq 970 .endif 971 stb r10,PACAIRQHAPPENED(r13) 972 973 .if \full_mask == 1 974 rldicl r10,r11,48,1 /* clear MSR_EE */ 975 rotldi r11,r10,16 976 mtspr SPRN_SRR1,r11 977 .endif 978 979 lwz r11,PACA_EXGEN+EX_CR(r13) 980 mtcr r11 981 ld r10,PACA_EXGEN+EX_R10(r13) 982 ld r11,PACA_EXGEN+EX_R11(r13) 983 mfspr r13,SPRN_SPRG_GEN_SCRATCH 984 rfi 985 b . 986.endm 987 988masked_interrupt_book3e_0x500: 989 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE 990 masked_interrupt_book3e PACA_IRQ_EE 1 991 992masked_interrupt_book3e_0x900: 993 ACK_DEC(r10); 994 masked_interrupt_book3e PACA_IRQ_DEC 0 995 996masked_interrupt_book3e_0x980: 997 ACK_FIT(r10); 998 masked_interrupt_book3e PACA_IRQ_DEC 0 999 1000masked_interrupt_book3e_0x280: 1001masked_interrupt_book3e_0x2c0: 1002 masked_interrupt_book3e PACA_IRQ_DBELL 0 1003 1004/* 1005 * Called from arch_local_irq_enable when an interrupt needs 1006 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280 1007 * to indicate the kind of interrupt. MSR:EE is already off. 1008 * We generate a stackframe like if a real interrupt had happened. 1009 * 1010 * Note: While MSR:EE is off, we need to make sure that _MSR 1011 * in the generated frame has EE set to 1 or the exception 1012 * handler will not properly re-enable them. 1013 */ 1014_GLOBAL(__replay_interrupt) 1015 /* We are going to jump to the exception common code which 1016 * will retrieve various register values from the PACA which 1017 * we don't give a damn about. 1018 */ 1019 mflr r10 1020 mfmsr r11 1021 mfcr r4 1022 mtspr SPRN_SPRG_GEN_SCRATCH,r13; 1023 std r1,PACA_EXGEN+EX_R1(r13); 1024 stw r4,PACA_EXGEN+EX_CR(r13); 1025 ori r11,r11,MSR_EE 1026 subi r1,r1,INT_FRAME_SIZE; 1027 cmpwi cr0,r3,0x500 1028 beq exc_0x500_common 1029 cmpwi cr0,r3,0x900 1030 beq exc_0x900_common 1031 cmpwi cr0,r3,0x280 1032 beq exc_0x280_common 1033 blr 1034 1035 1036/* 1037 * This is called from 0x300 and 0x400 handlers after the prologs with 1038 * r14 and r15 containing the fault address and error code, with the 1039 * original values stashed away in the PACA 1040 */ 1041storage_fault_common: 1042 std r14,_DAR(r1) 1043 std r15,_DSISR(r1) 1044 addi r3,r1,STACK_FRAME_OVERHEAD 1045 mr r4,r14 1046 mr r5,r15 1047 ld r14,PACA_EXGEN+EX_R14(r13) 1048 ld r15,PACA_EXGEN+EX_R15(r13) 1049 bl do_page_fault 1050 cmpdi r3,0 1051 bne- 1f 1052 b ret_from_except_lite 10531: bl save_nvgprs 1054 mr r5,r3 1055 addi r3,r1,STACK_FRAME_OVERHEAD 1056 ld r4,_DAR(r1) 1057 bl bad_page_fault 1058 b ret_from_except 1059 1060/* 1061 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 1062 * continues here. 1063 */ 1064alignment_more: 1065 std r14,_DAR(r1) 1066 std r15,_DSISR(r1) 1067 addi r3,r1,STACK_FRAME_OVERHEAD 1068 ld r14,PACA_EXGEN+EX_R14(r13) 1069 ld r15,PACA_EXGEN+EX_R15(r13) 1070 bl save_nvgprs 1071 INTS_RESTORE_HARD 1072 bl alignment_exception 1073 b ret_from_except 1074 1075/* 1076 * We branch here from entry_64.S for the last stage of the exception 1077 * return code path. MSR:EE is expected to be off at that point 1078 */ 1079_GLOBAL(exception_return_book3e) 1080 b 1f 1081 1082/* This is the return from load_up_fpu fast path which could do with 1083 * less GPR restores in fact, but for now we have a single return path 1084 */ 1085 .globl fast_exception_return 1086fast_exception_return: 1087 wrteei 0 10881: mr r0,r13 1089 ld r10,_MSR(r1) 1090 REST_4GPRS(2, r1) 1091 andi. r6,r10,MSR_PR 1092 REST_2GPRS(6, r1) 1093 beq 1f 1094 ACCOUNT_CPU_USER_EXIT(r13, r10, r11) 1095 ld r0,GPR13(r1) 1096 10971: stdcx. r0,0,r1 /* to clear the reservation */ 1098 1099 ld r8,_CCR(r1) 1100 ld r9,_LINK(r1) 1101 ld r10,_CTR(r1) 1102 ld r11,_XER(r1) 1103 mtcr r8 1104 mtlr r9 1105 mtctr r10 1106 mtxer r11 1107 REST_2GPRS(8, r1) 1108 ld r10,GPR10(r1) 1109 ld r11,GPR11(r1) 1110 ld r12,GPR12(r1) 1111 mtspr SPRN_SPRG_GEN_SCRATCH,r0 1112 1113 std r10,PACA_EXGEN+EX_R10(r13); 1114 std r11,PACA_EXGEN+EX_R11(r13); 1115 ld r10,_NIP(r1) 1116 ld r11,_MSR(r1) 1117 ld r0,GPR0(r1) 1118 ld r1,GPR1(r1) 1119 mtspr SPRN_SRR0,r10 1120 mtspr SPRN_SRR1,r11 1121 ld r10,PACA_EXGEN+EX_R10(r13) 1122 ld r11,PACA_EXGEN+EX_R11(r13) 1123 mfspr r13,SPRN_SPRG_GEN_SCRATCH 1124 rfi 1125 1126/* 1127 * Trampolines used when spotting a bad kernel stack pointer in 1128 * the exception entry code. 1129 * 1130 * TODO: move some bits like SRR0 read to trampoline, pass PACA 1131 * index around, etc... to handle crit & mcheck 1132 */ 1133BAD_STACK_TRAMPOLINE(0x000) 1134BAD_STACK_TRAMPOLINE(0x100) 1135BAD_STACK_TRAMPOLINE(0x200) 1136BAD_STACK_TRAMPOLINE(0x220) 1137BAD_STACK_TRAMPOLINE(0x260) 1138BAD_STACK_TRAMPOLINE(0x280) 1139BAD_STACK_TRAMPOLINE(0x2a0) 1140BAD_STACK_TRAMPOLINE(0x2c0) 1141BAD_STACK_TRAMPOLINE(0x2e0) 1142BAD_STACK_TRAMPOLINE(0x300) 1143BAD_STACK_TRAMPOLINE(0x310) 1144BAD_STACK_TRAMPOLINE(0x320) 1145BAD_STACK_TRAMPOLINE(0x340) 1146BAD_STACK_TRAMPOLINE(0x400) 1147BAD_STACK_TRAMPOLINE(0x500) 1148BAD_STACK_TRAMPOLINE(0x600) 1149BAD_STACK_TRAMPOLINE(0x700) 1150BAD_STACK_TRAMPOLINE(0x800) 1151BAD_STACK_TRAMPOLINE(0x900) 1152BAD_STACK_TRAMPOLINE(0x980) 1153BAD_STACK_TRAMPOLINE(0x9f0) 1154BAD_STACK_TRAMPOLINE(0xa00) 1155BAD_STACK_TRAMPOLINE(0xb00) 1156BAD_STACK_TRAMPOLINE(0xc00) 1157BAD_STACK_TRAMPOLINE(0xd00) 1158BAD_STACK_TRAMPOLINE(0xd08) 1159BAD_STACK_TRAMPOLINE(0xe00) 1160BAD_STACK_TRAMPOLINE(0xf00) 1161BAD_STACK_TRAMPOLINE(0xf20) 1162 1163 .globl bad_stack_book3e 1164bad_stack_book3e: 1165 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 1166 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 1167 ld r1,PACAEMERGSP(r13) 1168 subi r1,r1,64+INT_FRAME_SIZE 1169 std r10,_NIP(r1) 1170 std r11,_MSR(r1) 1171 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 1172 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 1173 std r10,GPR1(r1) 1174 std r11,_CCR(r1) 1175 mfspr r10,SPRN_DEAR 1176 mfspr r11,SPRN_ESR 1177 std r10,_DAR(r1) 1178 std r11,_DSISR(r1) 1179 std r0,GPR0(r1); /* save r0 in stackframe */ \ 1180 std r2,GPR2(r1); /* save r2 in stackframe */ \ 1181 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 1182 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 1183 std r9,GPR9(r1); /* save r9 in stackframe */ \ 1184 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 1185 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 1186 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 1187 std r3,GPR10(r1); /* save r10 to stackframe */ \ 1188 std r4,GPR11(r1); /* save r11 to stackframe */ \ 1189 std r12,GPR12(r1); /* save r12 in stackframe */ \ 1190 std r5,GPR13(r1); /* save it to stackframe */ \ 1191 mflr r10 1192 mfctr r11 1193 mfxer r12 1194 std r10,_LINK(r1) 1195 std r11,_CTR(r1) 1196 std r12,_XER(r1) 1197 SAVE_10GPRS(14,r1) 1198 SAVE_8GPRS(24,r1) 1199 lhz r12,PACA_TRAP_SAVE(r13) 1200 std r12,_TRAP(r1) 1201 addi r11,r1,INT_FRAME_SIZE 1202 std r11,0(r1) 1203 li r12,0 1204 std r12,0(r11) 1205 ld r2,PACATOC(r13) 12061: addi r3,r1,STACK_FRAME_OVERHEAD 1207 bl kernel_bad_stack 1208 b 1b 1209 1210/* 1211 * Setup the initial TLB for a core. This current implementation 1212 * assume that whatever we are running off will not conflict with 1213 * the new mapping at PAGE_OFFSET. 1214 */ 1215_GLOBAL(initial_tlb_book3e) 1216 1217 /* Look for the first TLB with IPROT set */ 1218 mfspr r4,SPRN_TLB0CFG 1219 andi. r3,r4,TLBnCFG_IPROT 1220 lis r3,MAS0_TLBSEL(0)@h 1221 bne found_iprot 1222 1223 mfspr r4,SPRN_TLB1CFG 1224 andi. r3,r4,TLBnCFG_IPROT 1225 lis r3,MAS0_TLBSEL(1)@h 1226 bne found_iprot 1227 1228 mfspr r4,SPRN_TLB2CFG 1229 andi. r3,r4,TLBnCFG_IPROT 1230 lis r3,MAS0_TLBSEL(2)@h 1231 bne found_iprot 1232 1233 lis r3,MAS0_TLBSEL(3)@h 1234 mfspr r4,SPRN_TLB3CFG 1235 /* fall through */ 1236 1237found_iprot: 1238 andi. r5,r4,TLBnCFG_HES 1239 bne have_hes 1240 1241 mflr r8 /* save LR */ 1242/* 1. Find the index of the entry we're executing in 1243 * 1244 * r3 = MAS0_TLBSEL (for the iprot array) 1245 * r4 = SPRN_TLBnCFG 1246 */ 1247 bl invstr /* Find our address */ 1248invstr: mflr r6 /* Make it accessible */ 1249 mfmsr r7 1250 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 1251 mfspr r7,SPRN_PID 1252 slwi r7,r7,16 1253 or r7,r7,r5 1254 mtspr SPRN_MAS6,r7 1255 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 1256 1257 mfspr r3,SPRN_MAS0 1258 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 1259 1260 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 1261 oris r7,r7,MAS1_IPROT@h 1262 mtspr SPRN_MAS1,r7 1263 tlbwe 1264 1265/* 2. Invalidate all entries except the entry we're executing in 1266 * 1267 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1268 * r4 = SPRN_TLBnCFG 1269 * r5 = ESEL of entry we are running in 1270 */ 1271 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 1272 li r6,0 /* Set Entry counter to 0 */ 12731: mr r7,r3 /* Set MAS0(TLBSEL) */ 1274 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1275 mtspr SPRN_MAS0,r7 1276 tlbre 1277 mfspr r7,SPRN_MAS1 1278 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 1279 cmpw r5,r6 1280 beq skpinv /* Dont update the current execution TLB */ 1281 mtspr SPRN_MAS1,r7 1282 tlbwe 1283 isync 1284skpinv: addi r6,r6,1 /* Increment */ 1285 cmpw r6,r4 /* Are we done? */ 1286 bne 1b /* If not, repeat */ 1287 1288 /* Invalidate all TLBs */ 1289 PPC_TLBILX_ALL(0,R0) 1290 sync 1291 isync 1292 1293/* 3. Setup a temp mapping and jump to it 1294 * 1295 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1296 * r5 = ESEL of entry we are running in 1297 */ 1298 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 1299 addi r7,r7,0x1 1300 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 1301 mtspr SPRN_MAS0,r4 1302 tlbre 1303 1304 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 1305 mtspr SPRN_MAS0,r4 1306 1307 mfspr r7,SPRN_MAS1 1308 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 1309 mtspr SPRN_MAS1,r6 1310 1311 tlbwe 1312 1313 mfmsr r6 1314 xori r6,r6,MSR_IS 1315 mtspr SPRN_SRR1,r6 1316 bl 1f /* Find our address */ 13171: mflr r6 1318 addi r6,r6,(2f - 1b) 1319 mtspr SPRN_SRR0,r6 1320 rfi 13212: 1322 1323/* 4. Clear out PIDs & Search info 1324 * 1325 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1326 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1327 * r5 = MAS3 1328 */ 1329 li r6,0 1330 mtspr SPRN_MAS6,r6 1331 mtspr SPRN_PID,r6 1332 1333/* 5. Invalidate mapping we started in 1334 * 1335 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1336 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1337 * r5 = MAS3 1338 */ 1339 mtspr SPRN_MAS0,r3 1340 tlbre 1341 mfspr r6,SPRN_MAS1 1342 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */ 1343 mtspr SPRN_MAS1,r6 1344 tlbwe 1345 sync 1346 isync 1347 1348/* 1349 * The mapping only needs to be cache-coherent on SMP, except on 1350 * Freescale e500mc derivatives where it's also needed for coherent DMA. 1351 */ 1352#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 1353#define M_IF_NEEDED MAS2_M 1354#else 1355#define M_IF_NEEDED 0 1356#endif 1357 1358/* 6. Setup KERNELBASE mapping in TLB[0] 1359 * 1360 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1361 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1362 * r5 = MAS3 1363 */ 1364 rlwinm r3,r3,0,16,3 /* clear ESEL */ 1365 mtspr SPRN_MAS0,r3 1366 lis r6,(MAS1_VALID|MAS1_IPROT)@h 1367 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1368 mtspr SPRN_MAS1,r6 1369 1370 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED) 1371 mtspr SPRN_MAS2,r6 1372 1373 rlwinm r5,r5,0,0,25 1374 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 1375 mtspr SPRN_MAS3,r5 1376 li r5,-1 1377 rlwinm r5,r5,0,0,25 1378 1379 tlbwe 1380 1381/* 7. Jump to KERNELBASE mapping 1382 * 1383 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1384 */ 1385 /* Now we branch the new virtual address mapped by this entry */ 1386 bl 1f /* Find our address */ 13871: mflr r6 1388 addi r6,r6,(2f - 1b) 1389 tovirt(r6,r6) 1390 lis r7,MSR_KERNEL@h 1391 ori r7,r7,MSR_KERNEL@l 1392 mtspr SPRN_SRR0,r6 1393 mtspr SPRN_SRR1,r7 1394 rfi /* start execution out of TLB1[0] entry */ 13952: 1396 1397/* 8. Clear out the temp mapping 1398 * 1399 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1400 */ 1401 mtspr SPRN_MAS0,r4 1402 tlbre 1403 mfspr r5,SPRN_MAS1 1404 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */ 1405 mtspr SPRN_MAS1,r5 1406 tlbwe 1407 sync 1408 isync 1409 1410 /* We translate LR and return */ 1411 tovirt(r8,r8) 1412 mtlr r8 1413 blr 1414 1415have_hes: 1416 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 1417 * kernel linear mapping. We also set MAS8 once for all here though 1418 * that will have to be made dependent on whether we are running under 1419 * a hypervisor I suppose. 1420 */ 1421 1422 /* BEWARE, MAGIC 1423 * This code is called as an ordinary function on the boot CPU. But to 1424 * avoid duplication, this code is also used in SCOM bringup of 1425 * secondary CPUs. We read the code between the initial_tlb_code_start 1426 * and initial_tlb_code_end labels one instruction at a time and RAM it 1427 * into the new core via SCOM. That doesn't process branches, so there 1428 * must be none between those two labels. It also means if this code 1429 * ever takes any parameters, the SCOM code must also be updated to 1430 * provide them. 1431 */ 1432 .globl a2_tlbinit_code_start 1433a2_tlbinit_code_start: 1434 1435 ori r11,r3,MAS0_WQ_ALLWAYS 1436 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ 1437 mtspr SPRN_MAS0,r11 1438 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1439 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 1440 mtspr SPRN_MAS1,r3 1441 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 1442 mtspr SPRN_MAS2,r3 1443 li r3,MAS3_SR | MAS3_SW | MAS3_SX 1444 mtspr SPRN_MAS7_MAS3,r3 1445 li r3,0 1446 mtspr SPRN_MAS8,r3 1447 1448 /* Write the TLB entry */ 1449 tlbwe 1450 1451 .globl a2_tlbinit_after_linear_map 1452a2_tlbinit_after_linear_map: 1453 1454 /* Now we branch the new virtual address mapped by this entry */ 1455 LOAD_REG_IMMEDIATE(r3,1f) 1456 mtctr r3 1457 bctr 1458 14591: /* We are now running at PAGE_OFFSET, clean the TLB of everything 1460 * else (including IPROTed things left by firmware) 1461 * r4 = TLBnCFG 1462 * r3 = current address (more or less) 1463 */ 1464 1465 li r5,0 1466 mtspr SPRN_MAS6,r5 1467 tlbsx 0,r3 1468 1469 rlwinm r9,r4,0,TLBnCFG_N_ENTRY 1470 rlwinm r10,r4,8,0xff 1471 addi r10,r10,-1 /* Get inner loop mask */ 1472 1473 li r3,1 1474 1475 mfspr r5,SPRN_MAS1 1476 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) 1477 1478 mfspr r6,SPRN_MAS2 1479 rldicr r6,r6,0,51 /* Extract EPN */ 1480 1481 mfspr r7,SPRN_MAS0 1482 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ 1483 1484 rlwinm r8,r7,16,0xfff /* Extract ESEL */ 1485 14862: add r4,r3,r8 1487 and r4,r4,r10 1488 1489 rlwimi r7,r4,16,MAS0_ESEL_MASK 1490 1491 mtspr SPRN_MAS0,r7 1492 mtspr SPRN_MAS1,r5 1493 mtspr SPRN_MAS2,r6 1494 tlbwe 1495 1496 addi r3,r3,1 1497 and. r4,r3,r10 1498 1499 bne 3f 1500 addis r6,r6,(1<<30)@h 15013: 1502 cmpw r3,r9 1503 blt 2b 1504 1505 .globl a2_tlbinit_after_iprot_flush 1506a2_tlbinit_after_iprot_flush: 1507 1508 PPC_TLBILX(0,0,R0) 1509 sync 1510 isync 1511 1512 .globl a2_tlbinit_code_end 1513a2_tlbinit_code_end: 1514 1515 /* We translate LR and return */ 1516 mflr r3 1517 tovirt(r3,r3) 1518 mtlr r3 1519 blr 1520 1521/* 1522 * Main entry (boot CPU, thread 0) 1523 * 1524 * We enter here from head_64.S, possibly after the prom_init trampoline 1525 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 1526 * mode. Anything else is as it was left by the bootloader 1527 * 1528 * Initial requirements of this port: 1529 * 1530 * - Kernel loaded at 0 physical 1531 * - A good lump of memory mapped 0:0 by UTLB entry 0 1532 * - MSR:IS & MSR:DS set to 0 1533 * 1534 * Note that some of the above requirements will be relaxed in the future 1535 * as the kernel becomes smarter at dealing with different initial conditions 1536 * but for now you have to be careful 1537 */ 1538_GLOBAL(start_initialization_book3e) 1539 mflr r28 1540 1541 /* First, we need to setup some initial TLBs to map the kernel 1542 * text, data and bss at PAGE_OFFSET. We don't have a real mode 1543 * and always use AS 0, so we just set it up to match our link 1544 * address and never use 0 based addresses. 1545 */ 1546 bl initial_tlb_book3e 1547 1548 /* Init global core bits */ 1549 bl init_core_book3e 1550 1551 /* Init per-thread bits */ 1552 bl init_thread_book3e 1553 1554 /* Return to common init code */ 1555 tovirt(r28,r28) 1556 mtlr r28 1557 blr 1558 1559 1560/* 1561 * Secondary core/processor entry 1562 * 1563 * This is entered for thread 0 of a secondary core, all other threads 1564 * are expected to be stopped. It's similar to start_initialization_book3e 1565 * except that it's generally entered from the holding loop in head_64.S 1566 * after CPUs have been gathered by Open Firmware. 1567 * 1568 * We assume we are in 32 bits mode running with whatever TLB entry was 1569 * set for us by the firmware or POR engine. 1570 */ 1571_GLOBAL(book3e_secondary_core_init_tlb_set) 1572 li r4,1 1573 b generic_secondary_smp_init 1574 1575_GLOBAL(book3e_secondary_core_init) 1576 mflr r28 1577 1578 /* Do we need to setup initial TLB entry ? */ 1579 cmplwi r4,0 1580 bne 2f 1581 1582 /* Setup TLB for this core */ 1583 bl initial_tlb_book3e 1584 1585 /* We can return from the above running at a different 1586 * address, so recalculate r2 (TOC) 1587 */ 1588 bl relative_toc 1589 1590 /* Init global core bits */ 15912: bl init_core_book3e 1592 1593 /* Init per-thread bits */ 15943: bl init_thread_book3e 1595 1596 /* Return to common init code at proper virtual address. 1597 * 1598 * Due to various previous assumptions, we know we entered this 1599 * function at either the final PAGE_OFFSET mapping or using a 1600 * 1:1 mapping at 0, so we don't bother doing a complicated check 1601 * here, we just ensure the return address has the right top bits. 1602 * 1603 * Note that if we ever want to be smarter about where we can be 1604 * started from, we have to be careful that by the time we reach 1605 * the code below we may already be running at a different location 1606 * than the one we were called from since initial_tlb_book3e can 1607 * have moved us already. 1608 */ 1609 cmpdi cr0,r28,0 1610 blt 1f 1611 lis r3,PAGE_OFFSET@highest 1612 sldi r3,r3,32 1613 or r28,r28,r3 16141: mtlr r28 1615 blr 1616 1617_GLOBAL(book3e_secondary_thread_init) 1618 mflr r28 1619 b 3b 1620 1621 .globl init_core_book3e 1622init_core_book3e: 1623 /* Establish the interrupt vector base */ 1624 tovirt(r2,r2) 1625 LOAD_REG_ADDR(r3, interrupt_base_book3e) 1626 mtspr SPRN_IVPR,r3 1627 sync 1628 blr 1629 1630init_thread_book3e: 1631 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 1632 mtspr SPRN_EPCR,r3 1633 1634 /* Make sure interrupts are off */ 1635 wrteei 0 1636 1637 /* disable all timers and clear out status */ 1638 li r3,0 1639 mtspr SPRN_TCR,r3 1640 mfspr r3,SPRN_TSR 1641 mtspr SPRN_TSR,r3 1642 1643 blr 1644 1645_GLOBAL(__setup_base_ivors) 1646 SET_IVOR(0, 0x020) /* Critical Input */ 1647 SET_IVOR(1, 0x000) /* Machine Check */ 1648 SET_IVOR(2, 0x060) /* Data Storage */ 1649 SET_IVOR(3, 0x080) /* Instruction Storage */ 1650 SET_IVOR(4, 0x0a0) /* External Input */ 1651 SET_IVOR(5, 0x0c0) /* Alignment */ 1652 SET_IVOR(6, 0x0e0) /* Program */ 1653 SET_IVOR(7, 0x100) /* FP Unavailable */ 1654 SET_IVOR(8, 0x120) /* System Call */ 1655 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1656 SET_IVOR(10, 0x160) /* Decrementer */ 1657 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1658 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1659 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1660 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1661 SET_IVOR(15, 0x040) /* Debug */ 1662 1663 sync 1664 1665 blr 1666 1667_GLOBAL(setup_altivec_ivors) 1668 SET_IVOR(32, 0x200) /* AltiVec Unavailable */ 1669 SET_IVOR(33, 0x220) /* AltiVec Assist */ 1670 blr 1671 1672_GLOBAL(setup_perfmon_ivor) 1673 SET_IVOR(35, 0x260) /* Performance Monitor */ 1674 blr 1675 1676_GLOBAL(setup_doorbell_ivors) 1677 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1678 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1679 blr 1680 1681_GLOBAL(setup_ehv_ivors) 1682 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1683 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1684 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1685 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1686 blr 1687 1688_GLOBAL(setup_lrat_ivor) 1689 SET_IVOR(42, 0x340) /* LRAT Error */ 1690 blr 1691