1/* 2 * This file contains low level CPU setup functions. 3 * Valentine Barshak <vbarshak@ru.mvista.com> 4 * MontaVista Software, Inc (c) 2007 5 * 6 * Based on cpu_setup_6xx code by 7 * Benjamin Herrenschmidt <benh@kernel.crashing.org> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 */ 15 16#include <asm/processor.h> 17#include <asm/cputable.h> 18#include <asm/ppc_asm.h> 19 20_GLOBAL(__setup_cpu_440ep) 21 b __init_fpu_44x 22_GLOBAL(__setup_cpu_440epx) 23 mflr r4 24 bl __init_fpu_44x 25 bl __plb_disable_wrp 26 mtlr r4 27 blr 28_GLOBAL(__setup_cpu_440grx) 29 b __plb_disable_wrp 30 31 32/* enable APU between CPU and FPU */ 33_GLOBAL(__init_fpu_44x) 34 mfspr r3,SPRN_CCR0 35 /* Clear DAPUIB flag in CCR0 */ 36 rlwinm r3,r3,0,12,10 37 mtspr SPRN_CCR0,r3 38 isync 39 blr 40 41/* 42 * Workaround for the incorrect write to DDR SDRAM errata. 43 * The write address can be corrupted during writes to 44 * DDR SDRAM when write pipelining is enabled on PLB0. 45 * Disable write pipelining here. 46 */ 47#define DCRN_PLB4A0_ACR 0x81 48 49_GLOBAL(__plb_disable_wrp) 50 mfdcr r3,DCRN_PLB4A0_ACR 51 /* clear WRP bit in PLB4A0_ACR */ 52 rlwinm r3,r3,0,8,6 53 mtdcr DCRN_PLB4A0_ACR,r3 54 isync 55 blr 56 57