1 /* 2 * This program is used to generate definitions needed by 3 * assembly language modules. 4 * 5 * We use the technique used in the OSF Mach kernel code: 6 * generate asm statements containing #defines, 7 * compile this file to assembler, and then extract the 8 * #defines from the assembly-language output. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 */ 15 16 #define GENERATING_ASM_OFFSETS /* asm/smp.h */ 17 18 #include <linux/compat.h> 19 #include <linux/signal.h> 20 #include <linux/sched.h> 21 #include <linux/kernel.h> 22 #include <linux/errno.h> 23 #include <linux/string.h> 24 #include <linux/types.h> 25 #include <linux/mman.h> 26 #include <linux/mm.h> 27 #include <linux/suspend.h> 28 #include <linux/hrtimer.h> 29 #ifdef CONFIG_PPC64 30 #include <linux/time.h> 31 #include <linux/hardirq.h> 32 #endif 33 #include <linux/kbuild.h> 34 35 #include <asm/io.h> 36 #include <asm/page.h> 37 #include <asm/pgtable.h> 38 #include <asm/processor.h> 39 #include <asm/cputable.h> 40 #include <asm/thread_info.h> 41 #include <asm/rtas.h> 42 #include <asm/vdso_datapage.h> 43 #include <asm/dbell.h> 44 #ifdef CONFIG_PPC64 45 #include <asm/paca.h> 46 #include <asm/lppaca.h> 47 #include <asm/cache.h> 48 #include <asm/mmu.h> 49 #include <asm/hvcall.h> 50 #include <asm/xics.h> 51 #endif 52 #ifdef CONFIG_PPC_POWERNV 53 #include <asm/opal.h> 54 #endif 55 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST) 56 #include <linux/kvm_host.h> 57 #endif 58 #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S) 59 #include <asm/kvm_book3s.h> 60 #include <asm/kvm_ppc.h> 61 #endif 62 63 #ifdef CONFIG_PPC32 64 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 65 #include "head_booke.h" 66 #endif 67 #endif 68 69 #if defined(CONFIG_PPC_FSL_BOOK3E) 70 #include "../mm/mmu_decl.h" 71 #endif 72 73 #ifdef CONFIG_PPC_8xx 74 #include <asm/fixmap.h> 75 #endif 76 77 #define STACK_PT_REGS_OFFSET(sym, val) \ 78 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val)) 79 80 int main(void) 81 { 82 OFFSET(THREAD, task_struct, thread); 83 OFFSET(MM, task_struct, mm); 84 #ifdef CONFIG_STACKPROTECTOR 85 OFFSET(TASK_CANARY, task_struct, stack_canary); 86 #ifdef CONFIG_PPC64 87 OFFSET(PACA_CANARY, paca_struct, canary); 88 #endif 89 #endif 90 OFFSET(MMCONTEXTID, mm_struct, context.id); 91 #ifdef CONFIG_PPC64 92 DEFINE(SIGSEGV, SIGSEGV); 93 DEFINE(NMI_MASK, NMI_MASK); 94 #else 95 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16)); 96 OFFSET(KSP_LIMIT, thread_struct, ksp_limit); 97 #ifdef CONFIG_PPC_RTAS 98 OFFSET(RTAS_SP, thread_struct, rtas_sp); 99 #endif 100 #endif /* CONFIG_PPC64 */ 101 OFFSET(TASK_STACK, task_struct, stack); 102 #ifdef CONFIG_SMP 103 OFFSET(TI_CPU, task_struct, cpu); 104 #endif 105 106 #ifdef CONFIG_LIVEPATCH 107 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp); 108 #endif 109 110 OFFSET(KSP, thread_struct, ksp); 111 OFFSET(PT_REGS, thread_struct, regs); 112 #ifdef CONFIG_BOOKE 113 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]); 114 #endif 115 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode); 116 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr); 117 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area); 118 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr); 119 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp); 120 #ifdef CONFIG_ALTIVEC 121 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr); 122 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area); 123 OFFSET(THREAD_VRSAVE, thread_struct, vrsave); 124 OFFSET(THREAD_USED_VR, thread_struct, used_vr); 125 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr); 126 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec); 127 #endif /* CONFIG_ALTIVEC */ 128 #ifdef CONFIG_VSX 129 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr); 130 #endif /* CONFIG_VSX */ 131 #ifdef CONFIG_PPC64 132 OFFSET(KSP_VSID, thread_struct, ksp_vsid); 133 #else /* CONFIG_PPC64 */ 134 OFFSET(PGDIR, thread_struct, pgdir); 135 #ifdef CONFIG_SPE 136 OFFSET(THREAD_EVR0, thread_struct, evr[0]); 137 OFFSET(THREAD_ACC, thread_struct, acc); 138 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr); 139 OFFSET(THREAD_USED_SPE, thread_struct, used_spe); 140 #endif /* CONFIG_SPE */ 141 #endif /* CONFIG_PPC64 */ 142 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 143 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0); 144 #endif 145 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 146 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu); 147 #endif 148 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 149 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu); 150 #endif 151 152 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 153 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch); 154 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar); 155 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr); 156 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar); 157 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar); 158 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr); 159 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr); 160 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs); 161 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr); 162 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave); 163 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr); 164 /* Local pt_regs on stack for Transactional Memory funcs. */ 165 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD + 166 sizeof(struct pt_regs) + 16); 167 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 168 169 OFFSET(TI_FLAGS, thread_info, flags); 170 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags); 171 OFFSET(TI_PREEMPT, thread_info, preempt_count); 172 173 #ifdef CONFIG_PPC64 174 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size); 175 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size); 176 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page); 177 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size); 178 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size); 179 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page); 180 /* paca */ 181 DEFINE(PACA_SIZE, sizeof(struct paca_struct)); 182 OFFSET(PACAPACAINDEX, paca_struct, paca_index); 183 OFFSET(PACAPROCSTART, paca_struct, cpu_start); 184 OFFSET(PACAKSAVE, paca_struct, kstack); 185 OFFSET(PACACURRENT, paca_struct, __current); 186 OFFSET(PACASAVEDMSR, paca_struct, saved_msr); 187 OFFSET(PACAR1, paca_struct, saved_r1); 188 OFFSET(PACATOC, paca_struct, kernel_toc); 189 OFFSET(PACAKBASE, paca_struct, kernelbase); 190 OFFSET(PACAKMSR, paca_struct, kernel_msr); 191 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask); 192 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened); 193 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled); 194 #ifdef CONFIG_PPC_BOOK3S 195 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id); 196 #ifdef CONFIG_PPC_MM_SLICES 197 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize); 198 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize); 199 OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit); 200 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); 201 #endif /* CONFIG_PPC_MM_SLICES */ 202 #endif 203 204 #ifdef CONFIG_PPC_BOOK3E 205 OFFSET(PACAPGD, paca_struct, pgd); 206 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd); 207 OFFSET(PACA_EXGEN, paca_struct, exgen); 208 OFFSET(PACA_EXTLB, paca_struct, extlb); 209 OFFSET(PACA_EXMC, paca_struct, exmc); 210 OFFSET(PACA_EXCRIT, paca_struct, excrit); 211 OFFSET(PACA_EXDBG, paca_struct, exdbg); 212 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack); 213 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack); 214 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack); 215 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr); 216 217 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next); 218 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max); 219 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first); 220 #endif /* CONFIG_PPC_BOOK3E */ 221 222 #ifdef CONFIG_PPC_BOOK3S_64 223 OFFSET(PACASLBCACHE, paca_struct, slb_cache); 224 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr); 225 OFFSET(PACASTABRR, paca_struct, stab_rr); 226 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp); 227 #ifdef CONFIG_PPC_MM_SLICES 228 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp); 229 #else 230 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp); 231 #endif /* CONFIG_PPC_MM_SLICES */ 232 OFFSET(PACA_EXGEN, paca_struct, exgen); 233 OFFSET(PACA_EXMC, paca_struct, exmc); 234 OFFSET(PACA_EXSLB, paca_struct, exslb); 235 OFFSET(PACA_EXNMI, paca_struct, exnmi); 236 #ifdef CONFIG_PPC_PSERIES 237 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr); 238 #endif 239 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr); 240 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid); 241 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid); 242 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area); 243 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use); 244 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 245 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use); 246 #endif 247 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx); 248 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count); 249 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx); 250 #endif /* CONFIG_PPC_BOOK3S_64 */ 251 OFFSET(PACAEMERGSP, paca_struct, emergency_sp); 252 #ifdef CONFIG_PPC_BOOK3S_64 253 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp); 254 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp); 255 OFFSET(PACA_IN_MCE, paca_struct, in_mce); 256 OFFSET(PACA_IN_NMI, paca_struct, in_nmi); 257 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area); 258 OFFSET(PACA_EXRFI, paca_struct, exrfi); 259 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size); 260 261 #endif 262 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id); 263 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state); 264 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default); 265 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime); 266 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user); 267 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime); 268 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime); 269 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save); 270 OFFSET(PACA_NAPSTATELOST, paca_struct, nap_state_lost); 271 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso); 272 #else /* CONFIG_PPC64 */ 273 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 274 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime); 275 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user); 276 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime); 277 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime); 278 #endif 279 #endif /* CONFIG_PPC64 */ 280 281 /* RTAS */ 282 OFFSET(RTASBASE, rtas_t, base); 283 OFFSET(RTASENTRY, rtas_t, entry); 284 285 /* Interrupt register frame */ 286 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); 287 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); 288 STACK_PT_REGS_OFFSET(GPR0, gpr[0]); 289 STACK_PT_REGS_OFFSET(GPR1, gpr[1]); 290 STACK_PT_REGS_OFFSET(GPR2, gpr[2]); 291 STACK_PT_REGS_OFFSET(GPR3, gpr[3]); 292 STACK_PT_REGS_OFFSET(GPR4, gpr[4]); 293 STACK_PT_REGS_OFFSET(GPR5, gpr[5]); 294 STACK_PT_REGS_OFFSET(GPR6, gpr[6]); 295 STACK_PT_REGS_OFFSET(GPR7, gpr[7]); 296 STACK_PT_REGS_OFFSET(GPR8, gpr[8]); 297 STACK_PT_REGS_OFFSET(GPR9, gpr[9]); 298 STACK_PT_REGS_OFFSET(GPR10, gpr[10]); 299 STACK_PT_REGS_OFFSET(GPR11, gpr[11]); 300 STACK_PT_REGS_OFFSET(GPR12, gpr[12]); 301 STACK_PT_REGS_OFFSET(GPR13, gpr[13]); 302 #ifndef CONFIG_PPC64 303 STACK_PT_REGS_OFFSET(GPR14, gpr[14]); 304 #endif /* CONFIG_PPC64 */ 305 /* 306 * Note: these symbols include _ because they overlap with special 307 * register names 308 */ 309 STACK_PT_REGS_OFFSET(_NIP, nip); 310 STACK_PT_REGS_OFFSET(_MSR, msr); 311 STACK_PT_REGS_OFFSET(_CTR, ctr); 312 STACK_PT_REGS_OFFSET(_LINK, link); 313 STACK_PT_REGS_OFFSET(_CCR, ccr); 314 STACK_PT_REGS_OFFSET(_XER, xer); 315 STACK_PT_REGS_OFFSET(_DAR, dar); 316 STACK_PT_REGS_OFFSET(_DSISR, dsisr); 317 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3); 318 STACK_PT_REGS_OFFSET(RESULT, result); 319 STACK_PT_REGS_OFFSET(_TRAP, trap); 320 #ifndef CONFIG_PPC64 321 /* 322 * The PowerPC 400-class & Book-E processors have neither the DAR 323 * nor the DSISR SPRs. Hence, we overload them to hold the similar 324 * DEAR and ESR SPRs for such processors. For critical interrupts 325 * we use them to hold SRR0 and SRR1. 326 */ 327 STACK_PT_REGS_OFFSET(_DEAR, dar); 328 STACK_PT_REGS_OFFSET(_ESR, dsisr); 329 #else /* CONFIG_PPC64 */ 330 STACK_PT_REGS_OFFSET(SOFTE, softe); 331 STACK_PT_REGS_OFFSET(_PPR, ppr); 332 #endif /* CONFIG_PPC64 */ 333 334 #if defined(CONFIG_PPC32) 335 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 336 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE); 337 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); 338 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */ 339 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); 340 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1)); 341 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2)); 342 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3)); 343 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6)); 344 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7)); 345 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0)); 346 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1)); 347 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0)); 348 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1)); 349 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0)); 350 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1)); 351 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit)); 352 #endif 353 #endif 354 355 #ifndef CONFIG_PPC64 356 OFFSET(MM_PGD, mm_struct, pgd); 357 #endif /* ! CONFIG_PPC64 */ 358 359 /* About the CPU features table */ 360 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); 361 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); 362 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore); 363 364 OFFSET(pbe_address, pbe, address); 365 OFFSET(pbe_orig_address, pbe, orig_address); 366 OFFSET(pbe_next, pbe, next); 367 368 #ifndef CONFIG_PPC64 369 DEFINE(TASK_SIZE, TASK_SIZE); 370 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); 371 #endif /* ! CONFIG_PPC64 */ 372 373 /* datapage offsets for use by vdso */ 374 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp); 375 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec); 376 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs); 377 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count); 378 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest); 379 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime); 380 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32); 381 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec); 382 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec); 383 OFFSET(STAMP_XTIME, vdso_data, stamp_xtime); 384 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction); 385 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size); 386 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size); 387 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size); 388 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size); 389 #ifdef CONFIG_PPC64 390 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64); 391 OFFSET(TVAL64_TV_SEC, timeval, tv_sec); 392 OFFSET(TVAL64_TV_USEC, timeval, tv_usec); 393 OFFSET(TVAL32_TV_SEC, old_timeval32, tv_sec); 394 OFFSET(TVAL32_TV_USEC, old_timeval32, tv_usec); 395 OFFSET(TSPC64_TV_SEC, timespec, tv_sec); 396 OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec); 397 OFFSET(TSPC32_TV_SEC, old_timespec32, tv_sec); 398 OFFSET(TSPC32_TV_NSEC, old_timespec32, tv_nsec); 399 #else 400 OFFSET(TVAL32_TV_SEC, timeval, tv_sec); 401 OFFSET(TVAL32_TV_USEC, timeval, tv_usec); 402 OFFSET(TSPC32_TV_SEC, timespec, tv_sec); 403 OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec); 404 #endif 405 /* timeval/timezone offsets for use by vdso */ 406 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest); 407 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime); 408 409 /* Other bits used by the vdso */ 410 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); 411 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); 412 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE); 413 DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE); 414 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); 415 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); 416 417 #ifdef CONFIG_BUG 418 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry)); 419 #endif 420 421 #ifdef CONFIG_PPC_BOOK3S_64 422 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE))); 423 #else 424 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE); 425 #endif 426 DEFINE(PTE_SIZE, sizeof(pte_t)); 427 428 #ifdef CONFIG_KVM 429 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack); 430 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid); 431 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid); 432 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr); 433 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave); 434 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr); 435 #ifdef CONFIG_ALTIVEC 436 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr); 437 #endif 438 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); 439 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); 440 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); 441 #ifdef CONFIG_PPC_BOOK3S 442 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar); 443 #endif 444 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); 445 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); 446 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 447 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr); 448 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0); 449 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1); 450 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0); 451 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1); 452 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2); 453 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3); 454 #endif 455 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING 456 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry); 457 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr); 458 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit); 459 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time); 460 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time); 461 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity); 462 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start); 463 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount); 464 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total); 465 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min); 466 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max); 467 #endif 468 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3); 469 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4); 470 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5); 471 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6); 472 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7); 473 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid); 474 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1); 475 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared); 476 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr); 477 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr); 478 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) 479 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian); 480 #endif 481 482 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0); 483 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1); 484 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2); 485 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3); 486 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4); 487 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6); 488 489 OFFSET(VCPU_KVM, kvm_vcpu, kvm); 490 OFFSET(KVM_LPID, kvm, arch.lpid); 491 492 /* book3s */ 493 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 494 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets); 495 OFFSET(KVM_SDR1, kvm, arch.sdr1); 496 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid); 497 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr); 498 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1); 499 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits); 500 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls); 501 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v); 502 OFFSET(KVM_RADIX, kvm, arch.radix); 503 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled); 504 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); 505 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar); 506 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr); 507 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty); 508 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst); 509 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested); 510 OFFSET(VCPU_CPU, kvm_vcpu, cpu); 511 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu); 512 #endif 513 #ifdef CONFIG_PPC_BOOK3S 514 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr); 515 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr); 516 OFFSET(VCPU_IC, kvm_vcpu, arch.ic); 517 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr); 518 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr); 519 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor); 520 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr); 521 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl); 522 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr); 523 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx); 524 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr); 525 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx); 526 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr); 527 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags); 528 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec); 529 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires); 530 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions); 531 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded); 532 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded); 533 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending); 534 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request); 535 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr); 536 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc); 537 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc); 538 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar); 539 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar); 540 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier); 541 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb); 542 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max); 543 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr); 544 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr); 545 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar); 546 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa); 547 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr); 548 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); 549 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap); 550 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar); 551 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr); 552 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr); 553 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb); 554 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr); 555 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr); 556 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr); 557 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr); 558 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr); 559 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr); 560 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop); 561 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort); 562 OFFSET(VCPU_TID, kvm_vcpu, arch.tid); 563 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr); 564 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr); 565 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map); 566 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest); 567 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads); 568 OFFSET(VCORE_KVM, kvmppc_vcore, kvm); 569 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset); 570 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied); 571 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr); 572 OFFSET(VCORE_PCR, kvmppc_vcore, pcr); 573 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes); 574 OFFSET(VCORE_VTB, kvmppc_vcore, vtb); 575 OFFSET(VCPU_SLB_E, kvmppc_slb, orige); 576 OFFSET(VCPU_SLB_V, kvmppc_slb, origv); 577 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb)); 578 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 579 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar); 580 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar); 581 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr); 582 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr); 583 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm); 584 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr); 585 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr); 586 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm); 587 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm); 588 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm); 589 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm); 590 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm); 591 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm); 592 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm); 593 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm); 594 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm); 595 #endif 596 597 #ifdef CONFIG_PPC_BOOK3S_64 598 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 599 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu); 600 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f)) 601 #else 602 # define SVCPU_FIELD(x, f) 603 #endif 604 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f)) 605 #else /* 32-bit */ 606 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f)) 607 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f)) 608 #endif 609 610 SVCPU_FIELD(SVCPU_CR, cr); 611 SVCPU_FIELD(SVCPU_XER, xer); 612 SVCPU_FIELD(SVCPU_CTR, ctr); 613 SVCPU_FIELD(SVCPU_LR, lr); 614 SVCPU_FIELD(SVCPU_PC, pc); 615 SVCPU_FIELD(SVCPU_R0, gpr[0]); 616 SVCPU_FIELD(SVCPU_R1, gpr[1]); 617 SVCPU_FIELD(SVCPU_R2, gpr[2]); 618 SVCPU_FIELD(SVCPU_R3, gpr[3]); 619 SVCPU_FIELD(SVCPU_R4, gpr[4]); 620 SVCPU_FIELD(SVCPU_R5, gpr[5]); 621 SVCPU_FIELD(SVCPU_R6, gpr[6]); 622 SVCPU_FIELD(SVCPU_R7, gpr[7]); 623 SVCPU_FIELD(SVCPU_R8, gpr[8]); 624 SVCPU_FIELD(SVCPU_R9, gpr[9]); 625 SVCPU_FIELD(SVCPU_R10, gpr[10]); 626 SVCPU_FIELD(SVCPU_R11, gpr[11]); 627 SVCPU_FIELD(SVCPU_R12, gpr[12]); 628 SVCPU_FIELD(SVCPU_R13, gpr[13]); 629 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr); 630 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar); 631 SVCPU_FIELD(SVCPU_LAST_INST, last_inst); 632 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1); 633 #ifdef CONFIG_PPC_BOOK3S_32 634 SVCPU_FIELD(SVCPU_SR, sr); 635 #endif 636 #ifdef CONFIG_PPC64 637 SVCPU_FIELD(SVCPU_SLB, slb); 638 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max); 639 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr); 640 #endif 641 642 HSTATE_FIELD(HSTATE_HOST_R1, host_r1); 643 HSTATE_FIELD(HSTATE_HOST_R2, host_r2); 644 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr); 645 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler); 646 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0); 647 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1); 648 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2); 649 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest); 650 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5); 651 HSTATE_FIELD(HSTATE_NAPPING, napping); 652 653 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 654 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req); 655 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state); 656 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu); 657 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore); 658 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys); 659 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys); 660 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt); 661 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr); 662 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi); 663 HSTATE_FIELD(HSTATE_PTID, ptid); 664 HSTATE_FIELD(HSTATE_TID, tid); 665 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend); 666 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]); 667 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]); 668 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]); 669 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]); 670 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]); 671 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]); 672 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]); 673 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]); 674 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]); 675 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]); 676 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]); 677 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]); 678 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]); 679 HSTATE_FIELD(HSTATE_PURR, host_purr); 680 HSTATE_FIELD(HSTATE_SPURR, host_spurr); 681 HSTATE_FIELD(HSTATE_DSCR, host_dscr); 682 HSTATE_FIELD(HSTATE_DABR, dabr); 683 HSTATE_FIELD(HSTATE_DECEXP, dec_expires); 684 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode); 685 DEFINE(IPI_PRIORITY, IPI_PRIORITY); 686 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr); 687 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar); 688 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar); 689 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap); 690 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped); 691 OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set); 692 OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore); 693 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 694 695 #ifdef CONFIG_PPC_BOOK3S_64 696 HSTATE_FIELD(HSTATE_CFAR, cfar); 697 HSTATE_FIELD(HSTATE_PPR, ppr); 698 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr); 699 #endif /* CONFIG_PPC_BOOK3S_64 */ 700 701 #else /* CONFIG_PPC_BOOK3S */ 702 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); 703 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); 704 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); 705 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); 706 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); 707 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9); 708 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); 709 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear); 710 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr); 711 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save); 712 #endif /* CONFIG_PPC_BOOK3S */ 713 #endif /* CONFIG_KVM */ 714 715 #ifdef CONFIG_KVM_GUEST 716 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1); 717 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2); 718 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3); 719 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending); 720 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr); 721 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical); 722 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr); 723 #endif 724 725 #ifdef CONFIG_44x 726 DEFINE(PGD_T_LOG2, PGD_T_LOG2); 727 DEFINE(PTE_T_LOG2, PTE_T_LOG2); 728 #endif 729 #ifdef CONFIG_PPC_FSL_BOOK3E 730 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); 731 OFFSET(TLBCAM_MAS0, tlbcam, MAS0); 732 OFFSET(TLBCAM_MAS1, tlbcam, MAS1); 733 OFFSET(TLBCAM_MAS2, tlbcam, MAS2); 734 OFFSET(TLBCAM_MAS3, tlbcam, MAS3); 735 OFFSET(TLBCAM_MAS7, tlbcam, MAS7); 736 #endif 737 738 #if defined(CONFIG_KVM) && defined(CONFIG_SPE) 739 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]); 740 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc); 741 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr); 742 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr); 743 #endif 744 745 #ifdef CONFIG_KVM_BOOKE_HV 746 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4); 747 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6); 748 #endif 749 750 #ifdef CONFIG_KVM_XICS 751 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu, 752 arch.xive_saved_state)); 753 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu, 754 arch.xive_cam_word)); 755 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed)); 756 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on)); 757 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr)); 758 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr)); 759 #endif 760 761 #ifdef CONFIG_KVM_EXIT_TIMING 762 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu); 763 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl); 764 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu); 765 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl); 766 #endif 767 768 #ifdef CONFIG_PPC_POWERNV 769 OFFSET(PACA_CORE_IDLE_STATE_PTR, paca_struct, core_idle_state_ptr); 770 OFFSET(PACA_THREAD_IDLE_STATE, paca_struct, thread_idle_state); 771 OFFSET(PACA_THREAD_MASK, paca_struct, thread_mask); 772 OFFSET(PACA_SUBCORE_SIBLING_MASK, paca_struct, subcore_sibling_mask); 773 OFFSET(PACA_REQ_PSSCR, paca_struct, requested_psscr); 774 OFFSET(PACA_DONT_STOP, paca_struct, dont_stop); 775 #define STOP_SPR(x, f) OFFSET(x, paca_struct, stop_sprs.f) 776 STOP_SPR(STOP_PID, pid); 777 STOP_SPR(STOP_LDBAR, ldbar); 778 STOP_SPR(STOP_FSCR, fscr); 779 STOP_SPR(STOP_HFSCR, hfscr); 780 STOP_SPR(STOP_MMCR1, mmcr1); 781 STOP_SPR(STOP_MMCR2, mmcr2); 782 STOP_SPR(STOP_MMCRA, mmcra); 783 #endif 784 785 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); 786 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE); 787 788 #ifdef CONFIG_PPC_8xx 789 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE)); 790 #endif 791 792 return 0; 793 } 794