1ed3e81ffSGavin Shan /* 2ed3e81ffSGavin Shan * This program is free software; you can redistribute it and/or modify 3ed3e81ffSGavin Shan * it under the terms of the GNU General Public License, version 2, as 4ed3e81ffSGavin Shan * published by the Free Software Foundation. 5ed3e81ffSGavin Shan * 6ed3e81ffSGavin Shan * This program is distributed in the hope that it will be useful, 7ed3e81ffSGavin Shan * but WITHOUT ANY WARRANTY; without even the implied warranty of 8ed3e81ffSGavin Shan * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9ed3e81ffSGavin Shan * GNU General Public License for more details. 10ed3e81ffSGavin Shan * 11ed3e81ffSGavin Shan * You should have received a copy of the GNU General Public License 12ed3e81ffSGavin Shan * along with this program; if not, write to the Free Software 13ed3e81ffSGavin Shan * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14ed3e81ffSGavin Shan * 15ed3e81ffSGavin Shan * Copyright IBM Corp. 2015 16ed3e81ffSGavin Shan * 17ed3e81ffSGavin Shan * Authors: Gavin Shan <gwshan@linux.vnet.ibm.com> 18ed3e81ffSGavin Shan */ 19ed3e81ffSGavin Shan 20ed3e81ffSGavin Shan #ifndef _ASM_POWERPC_EEH_H 21ed3e81ffSGavin Shan #define _ASM_POWERPC_EEH_H 22ed3e81ffSGavin Shan 23ed3e81ffSGavin Shan /* PE states */ 24ed3e81ffSGavin Shan #define EEH_PE_STATE_NORMAL 0 /* Normal state */ 25ed3e81ffSGavin Shan #define EEH_PE_STATE_RESET 1 /* PE reset asserted */ 26ed3e81ffSGavin Shan #define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */ 27ed3e81ffSGavin Shan #define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */ 28ed3e81ffSGavin Shan #define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */ 29ed3e81ffSGavin Shan 30*ec33d36eSGavin Shan /* EEH error types and functions */ 31*ec33d36eSGavin Shan #define EEH_ERR_TYPE_32 0 /* 32-bits error */ 32*ec33d36eSGavin Shan #define EEH_ERR_TYPE_64 1 /* 64-bits error */ 33*ec33d36eSGavin Shan #define EEH_ERR_FUNC_MIN 0 34*ec33d36eSGavin Shan #define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */ 35*ec33d36eSGavin Shan #define EEH_ERR_FUNC_LD_MEM_DATA 1 36*ec33d36eSGavin Shan #define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */ 37*ec33d36eSGavin Shan #define EEH_ERR_FUNC_LD_IO_DATA 3 38*ec33d36eSGavin Shan #define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */ 39*ec33d36eSGavin Shan #define EEH_ERR_FUNC_LD_CFG_DATA 5 40*ec33d36eSGavin Shan #define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */ 41*ec33d36eSGavin Shan #define EEH_ERR_FUNC_ST_MEM_DATA 7 42*ec33d36eSGavin Shan #define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */ 43*ec33d36eSGavin Shan #define EEH_ERR_FUNC_ST_IO_DATA 9 44*ec33d36eSGavin Shan #define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */ 45*ec33d36eSGavin Shan #define EEH_ERR_FUNC_ST_CFG_DATA 11 46*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */ 47*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_RD_DATA 13 48*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_RD_MASTER 14 49*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_RD_TARGET 15 50*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */ 51*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_WR_DATA 17 52*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_WR_MASTER 18 53*ec33d36eSGavin Shan #define EEH_ERR_FUNC_DMA_WR_TARGET 19 54*ec33d36eSGavin Shan #define EEH_ERR_FUNC_MAX 19 55*ec33d36eSGavin Shan 56ed3e81ffSGavin Shan #endif /* _ASM_POWERPC_EEH_H */ 57