xref: /openbmc/linux/arch/powerpc/include/asm/ps3gpu.h (revision d3352c9f1e8e2f2989d9686c8aa8acb4842fe75e)
1*d3352c9fSGeert Uytterhoeven /*
2*d3352c9fSGeert Uytterhoeven  *  PS3 GPU declarations.
3*d3352c9fSGeert Uytterhoeven  *
4*d3352c9fSGeert Uytterhoeven  *  Copyright 2009 Sony Corporation
5*d3352c9fSGeert Uytterhoeven  *
6*d3352c9fSGeert Uytterhoeven  *  This program is free software; you can redistribute it and/or modify
7*d3352c9fSGeert Uytterhoeven  *  it under the terms of the GNU General Public License as published by
8*d3352c9fSGeert Uytterhoeven  *  the Free Software Foundation; version 2 of the License.
9*d3352c9fSGeert Uytterhoeven  *
10*d3352c9fSGeert Uytterhoeven  *  This program is distributed in the hope that it will be useful,
11*d3352c9fSGeert Uytterhoeven  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12*d3352c9fSGeert Uytterhoeven  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13*d3352c9fSGeert Uytterhoeven  *  GNU General Public License for more details.
14*d3352c9fSGeert Uytterhoeven  *
15*d3352c9fSGeert Uytterhoeven  *  You should have received a copy of the GNU General Public License
16*d3352c9fSGeert Uytterhoeven  *  along with this program.
17*d3352c9fSGeert Uytterhoeven  *  If not, see <http://www.gnu.org/licenses/>.
18*d3352c9fSGeert Uytterhoeven  */
19*d3352c9fSGeert Uytterhoeven 
20*d3352c9fSGeert Uytterhoeven #ifndef _ASM_POWERPC_PS3GPU_H
21*d3352c9fSGeert Uytterhoeven #define _ASM_POWERPC_PS3GPU_H
22*d3352c9fSGeert Uytterhoeven 
23*d3352c9fSGeert Uytterhoeven #include <linux/mutex.h>
24*d3352c9fSGeert Uytterhoeven 
25*d3352c9fSGeert Uytterhoeven #include <asm/lv1call.h>
26*d3352c9fSGeert Uytterhoeven 
27*d3352c9fSGeert Uytterhoeven 
28*d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC	0x101
29*d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP	0x102
30*d3352c9fSGeert Uytterhoeven 
31*d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP	0x600
32*d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT		0x601
33*d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC	0x602
34*d3352c9fSGeert Uytterhoeven 
35*d3352c9fSGeert Uytterhoeven #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION	(1ULL << 32)
36*d3352c9fSGeert Uytterhoeven 
37*d3352c9fSGeert Uytterhoeven #define L1GPU_DISPLAY_SYNC_HSYNC		1
38*d3352c9fSGeert Uytterhoeven #define L1GPU_DISPLAY_SYNC_VSYNC		2
39*d3352c9fSGeert Uytterhoeven 
40*d3352c9fSGeert Uytterhoeven 
41*d3352c9fSGeert Uytterhoeven /* mutex synchronizing GPU accesses and video mode changes */
42*d3352c9fSGeert Uytterhoeven extern struct mutex ps3_gpu_mutex;
43*d3352c9fSGeert Uytterhoeven 
44*d3352c9fSGeert Uytterhoeven 
45*d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
46*d3352c9fSGeert Uytterhoeven 				       u64 ddr_offset)
47*d3352c9fSGeert Uytterhoeven {
48*d3352c9fSGeert Uytterhoeven 	return lv1_gpu_context_attribute(context_handle,
49*d3352c9fSGeert Uytterhoeven 					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
50*d3352c9fSGeert Uytterhoeven 					 head, ddr_offset, 0, 0);
51*d3352c9fSGeert Uytterhoeven }
52*d3352c9fSGeert Uytterhoeven 
53*d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
54*d3352c9fSGeert Uytterhoeven 				       u64 ddr_offset)
55*d3352c9fSGeert Uytterhoeven {
56*d3352c9fSGeert Uytterhoeven 	return lv1_gpu_context_attribute(context_handle,
57*d3352c9fSGeert Uytterhoeven 					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
58*d3352c9fSGeert Uytterhoeven 					 head, ddr_offset, 0, 0);
59*d3352c9fSGeert Uytterhoeven }
60*d3352c9fSGeert Uytterhoeven 
61*d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
62*d3352c9fSGeert Uytterhoeven 				   u64 xdr_size, u64 ioif_offset)
63*d3352c9fSGeert Uytterhoeven {
64*d3352c9fSGeert Uytterhoeven 	return lv1_gpu_context_attribute(context_handle,
65*d3352c9fSGeert Uytterhoeven 					 L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
66*d3352c9fSGeert Uytterhoeven 					 xdr_lpar, xdr_size, ioif_offset, 0);
67*d3352c9fSGeert Uytterhoeven }
68*d3352c9fSGeert Uytterhoeven 
69*d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
70*d3352c9fSGeert Uytterhoeven 				  u64 ioif_offset, u64 sync_width, u64 pitch)
71*d3352c9fSGeert Uytterhoeven {
72*d3352c9fSGeert Uytterhoeven 	return lv1_gpu_context_attribute(context_handle,
73*d3352c9fSGeert Uytterhoeven 					 L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
74*d3352c9fSGeert Uytterhoeven 					 ddr_offset, ioif_offset, sync_width,
75*d3352c9fSGeert Uytterhoeven 					 pitch);
76*d3352c9fSGeert Uytterhoeven }
77*d3352c9fSGeert Uytterhoeven 
78*d3352c9fSGeert Uytterhoeven #endif /* _ASM_POWERPC_PS3GPU_H */
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