1d3352c9fSGeert Uytterhoeven /* 2d3352c9fSGeert Uytterhoeven * PS3 GPU declarations. 3d3352c9fSGeert Uytterhoeven * 4d3352c9fSGeert Uytterhoeven * Copyright 2009 Sony Corporation 5d3352c9fSGeert Uytterhoeven * 6d3352c9fSGeert Uytterhoeven * This program is free software; you can redistribute it and/or modify 7d3352c9fSGeert Uytterhoeven * it under the terms of the GNU General Public License as published by 8d3352c9fSGeert Uytterhoeven * the Free Software Foundation; version 2 of the License. 9d3352c9fSGeert Uytterhoeven * 10d3352c9fSGeert Uytterhoeven * This program is distributed in the hope that it will be useful, 11d3352c9fSGeert Uytterhoeven * but WITHOUT ANY WARRANTY; without even the implied warranty of 12d3352c9fSGeert Uytterhoeven * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13d3352c9fSGeert Uytterhoeven * GNU General Public License for more details. 14d3352c9fSGeert Uytterhoeven * 15d3352c9fSGeert Uytterhoeven * You should have received a copy of the GNU General Public License 16d3352c9fSGeert Uytterhoeven * along with this program. 17d3352c9fSGeert Uytterhoeven * If not, see <http://www.gnu.org/licenses/>. 18d3352c9fSGeert Uytterhoeven */ 19d3352c9fSGeert Uytterhoeven 20d3352c9fSGeert Uytterhoeven #ifndef _ASM_POWERPC_PS3GPU_H 21d3352c9fSGeert Uytterhoeven #define _ASM_POWERPC_PS3GPU_H 22d3352c9fSGeert Uytterhoeven 23d3352c9fSGeert Uytterhoeven #include <linux/mutex.h> 24d3352c9fSGeert Uytterhoeven 25d3352c9fSGeert Uytterhoeven #include <asm/lv1call.h> 26d3352c9fSGeert Uytterhoeven 27d3352c9fSGeert Uytterhoeven 28d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101 29d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102 30d3352c9fSGeert Uytterhoeven 31d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600 32d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601 33d3352c9fSGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602 34*c204ff65SGeert Uytterhoeven #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603 35d3352c9fSGeert Uytterhoeven 36d3352c9fSGeert Uytterhoeven #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION (1ULL << 32) 37d3352c9fSGeert Uytterhoeven 38d3352c9fSGeert Uytterhoeven #define L1GPU_DISPLAY_SYNC_HSYNC 1 39d3352c9fSGeert Uytterhoeven #define L1GPU_DISPLAY_SYNC_VSYNC 2 40d3352c9fSGeert Uytterhoeven 41d3352c9fSGeert Uytterhoeven 42d3352c9fSGeert Uytterhoeven /* mutex synchronizing GPU accesses and video mode changes */ 43d3352c9fSGeert Uytterhoeven extern struct mutex ps3_gpu_mutex; 44d3352c9fSGeert Uytterhoeven 45d3352c9fSGeert Uytterhoeven 46d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_display_sync(u64 context_handle, u64 head, 47d3352c9fSGeert Uytterhoeven u64 ddr_offset) 48d3352c9fSGeert Uytterhoeven { 49d3352c9fSGeert Uytterhoeven return lv1_gpu_context_attribute(context_handle, 50d3352c9fSGeert Uytterhoeven L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC, 51d3352c9fSGeert Uytterhoeven head, ddr_offset, 0, 0); 52d3352c9fSGeert Uytterhoeven } 53d3352c9fSGeert Uytterhoeven 54d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_display_flip(u64 context_handle, u64 head, 55d3352c9fSGeert Uytterhoeven u64 ddr_offset) 56d3352c9fSGeert Uytterhoeven { 57d3352c9fSGeert Uytterhoeven return lv1_gpu_context_attribute(context_handle, 58d3352c9fSGeert Uytterhoeven L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP, 59d3352c9fSGeert Uytterhoeven head, ddr_offset, 0, 0); 60d3352c9fSGeert Uytterhoeven } 61d3352c9fSGeert Uytterhoeven 62d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar, 63d3352c9fSGeert Uytterhoeven u64 xdr_size, u64 ioif_offset) 64d3352c9fSGeert Uytterhoeven { 65d3352c9fSGeert Uytterhoeven return lv1_gpu_context_attribute(context_handle, 66d3352c9fSGeert Uytterhoeven L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP, 67d3352c9fSGeert Uytterhoeven xdr_lpar, xdr_size, ioif_offset, 0); 68d3352c9fSGeert Uytterhoeven } 69d3352c9fSGeert Uytterhoeven 70d3352c9fSGeert Uytterhoeven static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset, 71d3352c9fSGeert Uytterhoeven u64 ioif_offset, u64 sync_width, u64 pitch) 72d3352c9fSGeert Uytterhoeven { 73d3352c9fSGeert Uytterhoeven return lv1_gpu_context_attribute(context_handle, 74d3352c9fSGeert Uytterhoeven L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, 75d3352c9fSGeert Uytterhoeven ddr_offset, ioif_offset, sync_width, 76d3352c9fSGeert Uytterhoeven pitch); 77d3352c9fSGeert Uytterhoeven } 78d3352c9fSGeert Uytterhoeven 79*c204ff65SGeert Uytterhoeven static inline int lv1_gpu_fb_close(u64 context_handle) 80*c204ff65SGeert Uytterhoeven { 81*c204ff65SGeert Uytterhoeven return lv1_gpu_context_attribute(context_handle, 82*c204ff65SGeert Uytterhoeven L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, 83*c204ff65SGeert Uytterhoeven 0, 0, 0); 84*c204ff65SGeert Uytterhoeven } 85*c204ff65SGeert Uytterhoeven 86d3352c9fSGeert Uytterhoeven #endif /* _ASM_POWERPC_PS3GPU_H */ 87