1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2b8b572e1SStephen Rothwell /* 3b8b572e1SStephen Rothwell * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp. 4b8b572e1SStephen Rothwell * <benh@kernel.crashing.org> 5b8b572e1SStephen Rothwell */ 6b8b572e1SStephen Rothwell 7b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_DCR_H 8b8b572e1SStephen Rothwell #define _ASM_POWERPC_DCR_H 9b8b572e1SStephen Rothwell #ifdef __KERNEL__ 10b8b572e1SStephen Rothwell #ifndef __ASSEMBLY__ 11b8b572e1SStephen Rothwell #ifdef CONFIG_PPC_DCR 12b8b572e1SStephen Rothwell 13b8b572e1SStephen Rothwell #ifdef CONFIG_PPC_DCR_NATIVE 14b8b572e1SStephen Rothwell #include <asm/dcr-native.h> 15b8b572e1SStephen Rothwell #endif 16b8b572e1SStephen Rothwell 17b8b572e1SStephen Rothwell #ifdef CONFIG_PPC_DCR_MMIO 18b8b572e1SStephen Rothwell #include <asm/dcr-mmio.h> 19b8b572e1SStephen Rothwell #endif 20b8b572e1SStephen Rothwell 21b8b572e1SStephen Rothwell 22b8b572e1SStephen Rothwell /* Indirection layer for providing both NATIVE and MMIO support. */ 23b8b572e1SStephen Rothwell 24b8b572e1SStephen Rothwell #if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) 25b8b572e1SStephen Rothwell 26b8b572e1SStephen Rothwell #include <asm/dcr-generic.h> 27b8b572e1SStephen Rothwell 28b8b572e1SStephen Rothwell #define DCR_MAP_OK(host) dcr_map_ok_generic(host) 29b8b572e1SStephen Rothwell #define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c) 30b8b572e1SStephen Rothwell #define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c) 31b8b572e1SStephen Rothwell #define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n) 32b8b572e1SStephen Rothwell #define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value) 33b8b572e1SStephen Rothwell 34b8b572e1SStephen Rothwell #else 35b8b572e1SStephen Rothwell 36b8b572e1SStephen Rothwell #ifdef CONFIG_PPC_DCR_NATIVE 37b8b572e1SStephen Rothwell typedef dcr_host_native_t dcr_host_t; 38b8b572e1SStephen Rothwell #define DCR_MAP_OK(host) dcr_map_ok_native(host) 39b8b572e1SStephen Rothwell #define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c) 40b8b572e1SStephen Rothwell #define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c) 41b8b572e1SStephen Rothwell #define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n) 42b8b572e1SStephen Rothwell #define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value) 43b8b572e1SStephen Rothwell #else 44b8b572e1SStephen Rothwell typedef dcr_host_mmio_t dcr_host_t; 45b8b572e1SStephen Rothwell #define DCR_MAP_OK(host) dcr_map_ok_mmio(host) 46b8b572e1SStephen Rothwell #define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c) 47b8b572e1SStephen Rothwell #define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c) 48b8b572e1SStephen Rothwell #define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n) 49b8b572e1SStephen Rothwell #define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value) 50b8b572e1SStephen Rothwell #endif 51b8b572e1SStephen Rothwell 52b8b572e1SStephen Rothwell #endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */ 53b8b572e1SStephen Rothwell 54b8b572e1SStephen Rothwell /* 559c4cb825SKumar Gala * additional helpers to read the DCR * base from the device-tree 56b8b572e1SStephen Rothwell */ 57b8b572e1SStephen Rothwell struct device_node; 58e14d7749SGrant Erickson extern unsigned int dcr_resource_start(const struct device_node *np, 59b8b572e1SStephen Rothwell unsigned int index); 60e14d7749SGrant Erickson extern unsigned int dcr_resource_len(const struct device_node *np, 61b8b572e1SStephen Rothwell unsigned int index); 62b8b572e1SStephen Rothwell #endif /* CONFIG_PPC_DCR */ 63b8b572e1SStephen Rothwell #endif /* __ASSEMBLY__ */ 64b8b572e1SStephen Rothwell #endif /* __KERNEL__ */ 65b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_DCR_H */ 66