1*b68a24bcSAlbert Herranz/* 2*b68a24bcSAlbert Herranz * arch/powerpc/boot/gamecube-head.S 3*b68a24bcSAlbert Herranz * 4*b68a24bcSAlbert Herranz * Nintendo GameCube bootwrapper entry. 5*b68a24bcSAlbert Herranz * Copyright (C) 2004-2009 The GameCube Linux Team 6*b68a24bcSAlbert Herranz * Copyright (C) 2008,2009 Albert Herranz 7*b68a24bcSAlbert Herranz * 8*b68a24bcSAlbert Herranz * This program is free software; you can redistribute it and/or 9*b68a24bcSAlbert Herranz * modify it under the terms of the GNU General Public License 10*b68a24bcSAlbert Herranz * as published by the Free Software Foundation; either version 2 11*b68a24bcSAlbert Herranz * of the License, or (at your option) any later version. 12*b68a24bcSAlbert Herranz * 13*b68a24bcSAlbert Herranz */ 14*b68a24bcSAlbert Herranz 15*b68a24bcSAlbert Herranz#include "ppc_asm.h" 16*b68a24bcSAlbert Herranz 17*b68a24bcSAlbert Herranz/* 18*b68a24bcSAlbert Herranz * The entry code does no assumptions regarding: 19*b68a24bcSAlbert Herranz * - if the data and instruction caches are enabled or not 20*b68a24bcSAlbert Herranz * - if the MMU is enabled or not 21*b68a24bcSAlbert Herranz * 22*b68a24bcSAlbert Herranz * We enable the caches if not already enabled, enable the MMU with an 23*b68a24bcSAlbert Herranz * identity mapping scheme and jump to the start code. 24*b68a24bcSAlbert Herranz */ 25*b68a24bcSAlbert Herranz 26*b68a24bcSAlbert Herranz .text 27*b68a24bcSAlbert Herranz 28*b68a24bcSAlbert Herranz .globl _zimage_start 29*b68a24bcSAlbert Herranz_zimage_start: 30*b68a24bcSAlbert Herranz 31*b68a24bcSAlbert Herranz /* turn the MMU off */ 32*b68a24bcSAlbert Herranz mfmsr 9 33*b68a24bcSAlbert Herranz rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */ 34*b68a24bcSAlbert Herranz bcl 20, 31, 1f 35*b68a24bcSAlbert Herranz1: 36*b68a24bcSAlbert Herranz mflr 8 37*b68a24bcSAlbert Herranz clrlwi 8, 8, 3 /* convert to a real address */ 38*b68a24bcSAlbert Herranz addi 8, 8, _mmu_off - 1b 39*b68a24bcSAlbert Herranz mtsrr0 8 40*b68a24bcSAlbert Herranz mtsrr1 9 41*b68a24bcSAlbert Herranz rfi 42*b68a24bcSAlbert Herranz_mmu_off: 43*b68a24bcSAlbert Herranz /* MMU disabled */ 44*b68a24bcSAlbert Herranz 45*b68a24bcSAlbert Herranz /* setup BATs */ 46*b68a24bcSAlbert Herranz isync 47*b68a24bcSAlbert Herranz li 8, 0 48*b68a24bcSAlbert Herranz mtspr 0x210, 8 /* IBAT0U */ 49*b68a24bcSAlbert Herranz mtspr 0x212, 8 /* IBAT1U */ 50*b68a24bcSAlbert Herranz mtspr 0x214, 8 /* IBAT2U */ 51*b68a24bcSAlbert Herranz mtspr 0x216, 8 /* IBAT3U */ 52*b68a24bcSAlbert Herranz mtspr 0x218, 8 /* DBAT0U */ 53*b68a24bcSAlbert Herranz mtspr 0x21a, 8 /* DBAT1U */ 54*b68a24bcSAlbert Herranz mtspr 0x21c, 8 /* DBAT2U */ 55*b68a24bcSAlbert Herranz mtspr 0x21e, 8 /* DBAT3U */ 56*b68a24bcSAlbert Herranz 57*b68a24bcSAlbert Herranz li 8, 0x01ff /* first 16MiB */ 58*b68a24bcSAlbert Herranz li 9, 0x0002 /* rw */ 59*b68a24bcSAlbert Herranz mtspr 0x211, 9 /* IBAT0L */ 60*b68a24bcSAlbert Herranz mtspr 0x210, 8 /* IBAT0U */ 61*b68a24bcSAlbert Herranz mtspr 0x219, 9 /* DBAT0L */ 62*b68a24bcSAlbert Herranz mtspr 0x218, 8 /* DBAT0U */ 63*b68a24bcSAlbert Herranz 64*b68a24bcSAlbert Herranz lis 8, 0x0c00 /* I/O mem */ 65*b68a24bcSAlbert Herranz ori 8, 8, 0x3ff /* 32MiB */ 66*b68a24bcSAlbert Herranz lis 9, 0x0c00 67*b68a24bcSAlbert Herranz ori 9, 9, 0x002a /* uncached, guarded, rw */ 68*b68a24bcSAlbert Herranz mtspr 0x21b, 9 /* DBAT1L */ 69*b68a24bcSAlbert Herranz mtspr 0x21a, 8 /* DBAT1U */ 70*b68a24bcSAlbert Herranz 71*b68a24bcSAlbert Herranz lis 8, 0x0100 /* next 8MiB */ 72*b68a24bcSAlbert Herranz ori 8, 8, 0x00ff /* 8MiB */ 73*b68a24bcSAlbert Herranz lis 9, 0x0100 74*b68a24bcSAlbert Herranz ori 9, 9, 0x0002 /* rw */ 75*b68a24bcSAlbert Herranz mtspr 0x215, 9 /* IBAT2L */ 76*b68a24bcSAlbert Herranz mtspr 0x214, 8 /* IBAT2U */ 77*b68a24bcSAlbert Herranz mtspr 0x21d, 9 /* DBAT2L */ 78*b68a24bcSAlbert Herranz mtspr 0x21c, 8 /* DBAT2U */ 79*b68a24bcSAlbert Herranz 80*b68a24bcSAlbert Herranz /* enable and invalidate the caches if not already enabled */ 81*b68a24bcSAlbert Herranz mfspr 8, 0x3f0 /* HID0 */ 82*b68a24bcSAlbert Herranz andi. 0, 8, (1<<15) /* HID0_ICE */ 83*b68a24bcSAlbert Herranz bne 1f 84*b68a24bcSAlbert Herranz ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/ 85*b68a24bcSAlbert Herranz1: 86*b68a24bcSAlbert Herranz andi. 0, 8, (1<<14) /* HID0_DCE */ 87*b68a24bcSAlbert Herranz bne 1f 88*b68a24bcSAlbert Herranz ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/ 89*b68a24bcSAlbert Herranz1: 90*b68a24bcSAlbert Herranz mtspr 0x3f0, 8 /* HID0 */ 91*b68a24bcSAlbert Herranz isync 92*b68a24bcSAlbert Herranz 93*b68a24bcSAlbert Herranz /* initialize arguments */ 94*b68a24bcSAlbert Herranz li 3, 0 95*b68a24bcSAlbert Herranz li 4, 0 96*b68a24bcSAlbert Herranz li 5, 0 97*b68a24bcSAlbert Herranz 98*b68a24bcSAlbert Herranz /* turn the MMU on */ 99*b68a24bcSAlbert Herranz bcl 20, 31, 1f 100*b68a24bcSAlbert Herranz1: 101*b68a24bcSAlbert Herranz mflr 8 102*b68a24bcSAlbert Herranz addi 8, 8, _mmu_on - 1b 103*b68a24bcSAlbert Herranz mfmsr 9 104*b68a24bcSAlbert Herranz ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */ 105*b68a24bcSAlbert Herranz mtsrr0 8 106*b68a24bcSAlbert Herranz mtsrr1 9 107*b68a24bcSAlbert Herranz sync 108*b68a24bcSAlbert Herranz rfi 109*b68a24bcSAlbert Herranz_mmu_on: 110*b68a24bcSAlbert Herranz b _zimage_start_lib 111*b68a24bcSAlbert Herranz 112