1*bfee95bbSGrant Likely/* 2*bfee95bbSGrant Likely * Freescale Media5200 board Device Tree Source 3*bfee95bbSGrant Likely * 4*bfee95bbSGrant Likely * Copyright 2009 Secret Lab Technologies Ltd. 5*bfee95bbSGrant Likely * Grant Likely <grant.likely@secretlab.ca> 6*bfee95bbSGrant Likely * Steven Cavanagh <scavanagh@secretlab.ca> 7*bfee95bbSGrant Likely * 8*bfee95bbSGrant Likely * This program is free software; you can redistribute it and/or modify it 9*bfee95bbSGrant Likely * under the terms of the GNU General Public License as published by the 10*bfee95bbSGrant Likely * Free Software Foundation; either version 2 of the License, or (at your 11*bfee95bbSGrant Likely * option) any later version. 12*bfee95bbSGrant Likely */ 13*bfee95bbSGrant Likely 14*bfee95bbSGrant Likely/dts-v1/; 15*bfee95bbSGrant Likely 16*bfee95bbSGrant Likely/ { 17*bfee95bbSGrant Likely model = "fsl,media5200"; 18*bfee95bbSGrant Likely compatible = "fsl,media5200"; 19*bfee95bbSGrant Likely #address-cells = <1>; 20*bfee95bbSGrant Likely #size-cells = <1>; 21*bfee95bbSGrant Likely interrupt-parent = <&mpc5200_pic>; 22*bfee95bbSGrant Likely 23*bfee95bbSGrant Likely aliases { 24*bfee95bbSGrant Likely console = &console; 25*bfee95bbSGrant Likely ethernet0 = ð0; 26*bfee95bbSGrant Likely }; 27*bfee95bbSGrant Likely 28*bfee95bbSGrant Likely chosen { 29*bfee95bbSGrant Likely linux,stdout-path = &console; 30*bfee95bbSGrant Likely }; 31*bfee95bbSGrant Likely 32*bfee95bbSGrant Likely cpus { 33*bfee95bbSGrant Likely #address-cells = <1>; 34*bfee95bbSGrant Likely #size-cells = <0>; 35*bfee95bbSGrant Likely 36*bfee95bbSGrant Likely PowerPC,5200@0 { 37*bfee95bbSGrant Likely device_type = "cpu"; 38*bfee95bbSGrant Likely reg = <0>; 39*bfee95bbSGrant Likely d-cache-line-size = <32>; 40*bfee95bbSGrant Likely i-cache-line-size = <32>; 41*bfee95bbSGrant Likely d-cache-size = <0x4000>; // L1, 16K 42*bfee95bbSGrant Likely i-cache-size = <0x4000>; // L1, 16K 43*bfee95bbSGrant Likely timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot 44*bfee95bbSGrant Likely bus-frequency = <132000000>; // 132 MHz 45*bfee95bbSGrant Likely clock-frequency = <396000000>; // 396 MHz 46*bfee95bbSGrant Likely }; 47*bfee95bbSGrant Likely }; 48*bfee95bbSGrant Likely 49*bfee95bbSGrant Likely memory { 50*bfee95bbSGrant Likely device_type = "memory"; 51*bfee95bbSGrant Likely reg = <0x00000000 0x08000000>; // 128MB RAM 52*bfee95bbSGrant Likely }; 53*bfee95bbSGrant Likely 54*bfee95bbSGrant Likely soc@f0000000 { 55*bfee95bbSGrant Likely #address-cells = <1>; 56*bfee95bbSGrant Likely #size-cells = <1>; 57*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-immr"; 58*bfee95bbSGrant Likely ranges = <0 0xf0000000 0x0000c000>; 59*bfee95bbSGrant Likely reg = <0xf0000000 0x00000100>; 60*bfee95bbSGrant Likely bus-frequency = <132000000>;// 132 MHz 61*bfee95bbSGrant Likely system-frequency = <0>; // from bootloader 62*bfee95bbSGrant Likely 63*bfee95bbSGrant Likely cdm@200 { 64*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 65*bfee95bbSGrant Likely reg = <0x200 0x38>; 66*bfee95bbSGrant Likely }; 67*bfee95bbSGrant Likely 68*bfee95bbSGrant Likely mpc5200_pic: interrupt-controller@500 { 69*bfee95bbSGrant Likely // 5200 interrupts are encoded into two levels; 70*bfee95bbSGrant Likely interrupt-controller; 71*bfee95bbSGrant Likely #interrupt-cells = <3>; 72*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 73*bfee95bbSGrant Likely reg = <0x500 0x80>; 74*bfee95bbSGrant Likely }; 75*bfee95bbSGrant Likely 76*bfee95bbSGrant Likely timer@600 { // General Purpose Timer 77*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 78*bfee95bbSGrant Likely reg = <0x600 0x10>; 79*bfee95bbSGrant Likely interrupts = <1 9 0>; 80*bfee95bbSGrant Likely fsl,has-wdt; 81*bfee95bbSGrant Likely }; 82*bfee95bbSGrant Likely 83*bfee95bbSGrant Likely timer@610 { // General Purpose Timer 84*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 85*bfee95bbSGrant Likely reg = <0x610 0x10>; 86*bfee95bbSGrant Likely interrupts = <1 10 0>; 87*bfee95bbSGrant Likely }; 88*bfee95bbSGrant Likely 89*bfee95bbSGrant Likely timer@620 { // General Purpose Timer 90*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 91*bfee95bbSGrant Likely reg = <0x620 0x10>; 92*bfee95bbSGrant Likely interrupts = <1 11 0>; 93*bfee95bbSGrant Likely }; 94*bfee95bbSGrant Likely 95*bfee95bbSGrant Likely timer@630 { // General Purpose Timer 96*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 97*bfee95bbSGrant Likely reg = <0x630 0x10>; 98*bfee95bbSGrant Likely interrupts = <1 12 0>; 99*bfee95bbSGrant Likely }; 100*bfee95bbSGrant Likely 101*bfee95bbSGrant Likely timer@640 { // General Purpose Timer 102*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 103*bfee95bbSGrant Likely reg = <0x640 0x10>; 104*bfee95bbSGrant Likely interrupts = <1 13 0>; 105*bfee95bbSGrant Likely }; 106*bfee95bbSGrant Likely 107*bfee95bbSGrant Likely timer@650 { // General Purpose Timer 108*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 109*bfee95bbSGrant Likely reg = <0x650 0x10>; 110*bfee95bbSGrant Likely interrupts = <1 14 0>; 111*bfee95bbSGrant Likely }; 112*bfee95bbSGrant Likely 113*bfee95bbSGrant Likely timer@660 { // General Purpose Timer 114*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 115*bfee95bbSGrant Likely reg = <0x660 0x10>; 116*bfee95bbSGrant Likely interrupts = <1 15 0>; 117*bfee95bbSGrant Likely }; 118*bfee95bbSGrant Likely 119*bfee95bbSGrant Likely timer@670 { // General Purpose Timer 120*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 121*bfee95bbSGrant Likely reg = <0x670 0x10>; 122*bfee95bbSGrant Likely interrupts = <1 16 0>; 123*bfee95bbSGrant Likely }; 124*bfee95bbSGrant Likely 125*bfee95bbSGrant Likely rtc@800 { // Real time clock 126*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 127*bfee95bbSGrant Likely reg = <0x800 0x100>; 128*bfee95bbSGrant Likely interrupts = <1 5 0 1 6 0>; 129*bfee95bbSGrant Likely }; 130*bfee95bbSGrant Likely 131*bfee95bbSGrant Likely can@900 { 132*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 133*bfee95bbSGrant Likely interrupts = <2 17 0>; 134*bfee95bbSGrant Likely reg = <0x900 0x80>; 135*bfee95bbSGrant Likely }; 136*bfee95bbSGrant Likely 137*bfee95bbSGrant Likely can@980 { 138*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 139*bfee95bbSGrant Likely interrupts = <2 18 0>; 140*bfee95bbSGrant Likely reg = <0x980 0x80>; 141*bfee95bbSGrant Likely }; 142*bfee95bbSGrant Likely 143*bfee95bbSGrant Likely gpio_simple: gpio@b00 { 144*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 145*bfee95bbSGrant Likely reg = <0xb00 0x40>; 146*bfee95bbSGrant Likely interrupts = <1 7 0>; 147*bfee95bbSGrant Likely gpio-controller; 148*bfee95bbSGrant Likely #gpio-cells = <2>; 149*bfee95bbSGrant Likely }; 150*bfee95bbSGrant Likely 151*bfee95bbSGrant Likely gpio_wkup: gpio@c00 { 152*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 153*bfee95bbSGrant Likely reg = <0xc00 0x40>; 154*bfee95bbSGrant Likely interrupts = <1 8 0 0 3 0>; 155*bfee95bbSGrant Likely gpio-controller; 156*bfee95bbSGrant Likely #gpio-cells = <2>; 157*bfee95bbSGrant Likely }; 158*bfee95bbSGrant Likely 159*bfee95bbSGrant Likely spi@f00 { 160*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 161*bfee95bbSGrant Likely reg = <0xf00 0x20>; 162*bfee95bbSGrant Likely interrupts = <2 13 0 2 14 0>; 163*bfee95bbSGrant Likely }; 164*bfee95bbSGrant Likely 165*bfee95bbSGrant Likely usb@1000 { 166*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 167*bfee95bbSGrant Likely reg = <0x1000 0x100>; 168*bfee95bbSGrant Likely interrupts = <2 6 0>; 169*bfee95bbSGrant Likely }; 170*bfee95bbSGrant Likely 171*bfee95bbSGrant Likely dma-controller@1200 { 172*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 173*bfee95bbSGrant Likely reg = <0x1200 0x80>; 174*bfee95bbSGrant Likely interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 175*bfee95bbSGrant Likely 3 4 0 3 5 0 3 6 0 3 7 0 176*bfee95bbSGrant Likely 3 8 0 3 9 0 3 10 0 3 11 0 177*bfee95bbSGrant Likely 3 12 0 3 13 0 3 14 0 3 15 0>; 178*bfee95bbSGrant Likely }; 179*bfee95bbSGrant Likely 180*bfee95bbSGrant Likely xlb@1f00 { 181*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 182*bfee95bbSGrant Likely reg = <0x1f00 0x100>; 183*bfee95bbSGrant Likely }; 184*bfee95bbSGrant Likely 185*bfee95bbSGrant Likely // PSC6 in uart mode 186*bfee95bbSGrant Likely console: serial@2c00 { // PSC6 187*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 188*bfee95bbSGrant Likely cell-index = <5>; 189*bfee95bbSGrant Likely port-number = <0>; // Logical port assignment 190*bfee95bbSGrant Likely reg = <0x2c00 0x100>; 191*bfee95bbSGrant Likely interrupts = <2 4 0>; 192*bfee95bbSGrant Likely }; 193*bfee95bbSGrant Likely 194*bfee95bbSGrant Likely eth0: ethernet@3000 { 195*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 196*bfee95bbSGrant Likely reg = <0x3000 0x400>; 197*bfee95bbSGrant Likely local-mac-address = [ 00 00 00 00 00 00 ]; 198*bfee95bbSGrant Likely interrupts = <2 5 0>; 199*bfee95bbSGrant Likely phy-handle = <&phy0>; 200*bfee95bbSGrant Likely }; 201*bfee95bbSGrant Likely 202*bfee95bbSGrant Likely mdio@3000 { 203*bfee95bbSGrant Likely #address-cells = <1>; 204*bfee95bbSGrant Likely #size-cells = <0>; 205*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 206*bfee95bbSGrant Likely reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 207*bfee95bbSGrant Likely interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 208*bfee95bbSGrant Likely 209*bfee95bbSGrant Likely phy0: ethernet-phy@0 { 210*bfee95bbSGrant Likely reg = <0>; 211*bfee95bbSGrant Likely }; 212*bfee95bbSGrant Likely }; 213*bfee95bbSGrant Likely 214*bfee95bbSGrant Likely ata@3a00 { 215*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 216*bfee95bbSGrant Likely reg = <0x3a00 0x100>; 217*bfee95bbSGrant Likely interrupts = <2 7 0>; 218*bfee95bbSGrant Likely }; 219*bfee95bbSGrant Likely 220*bfee95bbSGrant Likely i2c@3d00 { 221*bfee95bbSGrant Likely #address-cells = <1>; 222*bfee95bbSGrant Likely #size-cells = <0>; 223*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 224*bfee95bbSGrant Likely reg = <0x3d00 0x40>; 225*bfee95bbSGrant Likely interrupts = <2 15 0>; 226*bfee95bbSGrant Likely fsl5200-clocking; 227*bfee95bbSGrant Likely }; 228*bfee95bbSGrant Likely 229*bfee95bbSGrant Likely i2c@3d40 { 230*bfee95bbSGrant Likely #address-cells = <1>; 231*bfee95bbSGrant Likely #size-cells = <0>; 232*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 233*bfee95bbSGrant Likely reg = <0x3d40 0x40>; 234*bfee95bbSGrant Likely interrupts = <2 16 0>; 235*bfee95bbSGrant Likely fsl5200-clocking; 236*bfee95bbSGrant Likely }; 237*bfee95bbSGrant Likely 238*bfee95bbSGrant Likely sram@8000 { 239*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 240*bfee95bbSGrant Likely reg = <0x8000 0x4000>; 241*bfee95bbSGrant Likely }; 242*bfee95bbSGrant Likely }; 243*bfee95bbSGrant Likely 244*bfee95bbSGrant Likely pci@f0000d00 { 245*bfee95bbSGrant Likely #interrupt-cells = <1>; 246*bfee95bbSGrant Likely #size-cells = <2>; 247*bfee95bbSGrant Likely #address-cells = <3>; 248*bfee95bbSGrant Likely device_type = "pci"; 249*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 250*bfee95bbSGrant Likely reg = <0xf0000d00 0x100>; 251*bfee95bbSGrant Likely interrupt-map-mask = <0xf800 0 0 7>; 252*bfee95bbSGrant Likely interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 253*bfee95bbSGrant Likely 0xc000 0 0 2 &media5200_fpga 0 3 254*bfee95bbSGrant Likely 0xc000 0 0 3 &media5200_fpga 0 4 255*bfee95bbSGrant Likely 0xc000 0 0 4 &media5200_fpga 0 5 256*bfee95bbSGrant Likely 257*bfee95bbSGrant Likely 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot 258*bfee95bbSGrant Likely 0xc800 0 0 2 &media5200_fpga 0 4 259*bfee95bbSGrant Likely 0xc800 0 0 3 &media5200_fpga 0 5 260*bfee95bbSGrant Likely 0xc800 0 0 4 &media5200_fpga 0 2 261*bfee95bbSGrant Likely 262*bfee95bbSGrant Likely 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI 263*bfee95bbSGrant Likely 0xd000 0 0 2 &media5200_fpga 0 5 264*bfee95bbSGrant Likely 265*bfee95bbSGrant Likely 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP 266*bfee95bbSGrant Likely >; 267*bfee95bbSGrant Likely clock-frequency = <0>; // From boot loader 268*bfee95bbSGrant Likely interrupts = <2 8 0 2 9 0 2 10 0>; 269*bfee95bbSGrant Likely interrupt-parent = <&mpc5200_pic>; 270*bfee95bbSGrant Likely bus-range = <0 0>; 271*bfee95bbSGrant Likely ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 272*bfee95bbSGrant Likely 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 273*bfee95bbSGrant Likely 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 274*bfee95bbSGrant Likely }; 275*bfee95bbSGrant Likely 276*bfee95bbSGrant Likely localbus { 277*bfee95bbSGrant Likely compatible = "fsl,mpc5200b-lpb","simple-bus"; 278*bfee95bbSGrant Likely #address-cells = <2>; 279*bfee95bbSGrant Likely #size-cells = <1>; 280*bfee95bbSGrant Likely 281*bfee95bbSGrant Likely ranges = < 0 0 0xfc000000 0x02000000 282*bfee95bbSGrant Likely 1 0 0xfe000000 0x02000000 283*bfee95bbSGrant Likely 2 0 0xf0010000 0x00010000 284*bfee95bbSGrant Likely 3 0 0xf0020000 0x00010000 >; 285*bfee95bbSGrant Likely 286*bfee95bbSGrant Likely flash@0,0 { 287*bfee95bbSGrant Likely compatible = "amd,am29lv28ml", "cfi-flash"; 288*bfee95bbSGrant Likely reg = <0 0x0 0x2000000>; // 32 MB 289*bfee95bbSGrant Likely bank-width = <4>; // Width in bytes of the flash bank 290*bfee95bbSGrant Likely device-width = <2>; // Two devices on each bank 291*bfee95bbSGrant Likely }; 292*bfee95bbSGrant Likely 293*bfee95bbSGrant Likely flash@1,0 { 294*bfee95bbSGrant Likely compatible = "amd,am29lv28ml", "cfi-flash"; 295*bfee95bbSGrant Likely reg = <1 0 0x2000000>; // 32 MB 296*bfee95bbSGrant Likely bank-width = <4>; // Width in bytes of the flash bank 297*bfee95bbSGrant Likely device-width = <2>; // Two devices on each bank 298*bfee95bbSGrant Likely }; 299*bfee95bbSGrant Likely 300*bfee95bbSGrant Likely media5200_fpga: fpga@2,0 { 301*bfee95bbSGrant Likely compatible = "fsl,media5200-fpga"; 302*bfee95bbSGrant Likely interrupt-controller; 303*bfee95bbSGrant Likely #interrupt-cells = <2>; // 0:bank 1:id; no type field 304*bfee95bbSGrant Likely reg = <2 0 0x10000>; 305*bfee95bbSGrant Likely 306*bfee95bbSGrant Likely interrupt-parent = <&mpc5200_pic>; 307*bfee95bbSGrant Likely interrupts = <0 0 3 // IRQ bank 0 308*bfee95bbSGrant Likely 1 1 3>; // IRQ bank 1 309*bfee95bbSGrant Likely }; 310*bfee95bbSGrant Likely 311*bfee95bbSGrant Likely uart@3,0 { 312*bfee95bbSGrant Likely compatible = "ti,tl16c752bpt"; 313*bfee95bbSGrant Likely reg = <3 0 0x10000>; 314*bfee95bbSGrant Likely interrupt-parent = <&media5200_fpga>; 315*bfee95bbSGrant Likely interrupts = <0 0 0 1>; // 2 irqs 316*bfee95bbSGrant Likely }; 317*bfee95bbSGrant Likely }; 318*bfee95bbSGrant Likely}; 319