1bfee95bbSGrant Likely/* 2bfee95bbSGrant Likely * Freescale Media5200 board Device Tree Source 3bfee95bbSGrant Likely * 4bfee95bbSGrant Likely * Copyright 2009 Secret Lab Technologies Ltd. 5bfee95bbSGrant Likely * Grant Likely <grant.likely@secretlab.ca> 6bfee95bbSGrant Likely * Steven Cavanagh <scavanagh@secretlab.ca> 7bfee95bbSGrant Likely * 8bfee95bbSGrant Likely * This program is free software; you can redistribute it and/or modify it 9bfee95bbSGrant Likely * under the terms of the GNU General Public License as published by the 10bfee95bbSGrant Likely * Free Software Foundation; either version 2 of the License, or (at your 11bfee95bbSGrant Likely * option) any later version. 12bfee95bbSGrant Likely */ 13bfee95bbSGrant Likely 14bfee95bbSGrant Likely/dts-v1/; 15bfee95bbSGrant Likely 16bfee95bbSGrant Likely/ { 17bfee95bbSGrant Likely model = "fsl,media5200"; 18bfee95bbSGrant Likely compatible = "fsl,media5200"; 19bfee95bbSGrant Likely #address-cells = <1>; 20bfee95bbSGrant Likely #size-cells = <1>; 21bfee95bbSGrant Likely interrupt-parent = <&mpc5200_pic>; 22bfee95bbSGrant Likely 23bfee95bbSGrant Likely aliases { 24bfee95bbSGrant Likely console = &console; 25bfee95bbSGrant Likely ethernet0 = ð0; 26bfee95bbSGrant Likely }; 27bfee95bbSGrant Likely 28bfee95bbSGrant Likely chosen { 29bfee95bbSGrant Likely linux,stdout-path = &console; 30bfee95bbSGrant Likely }; 31bfee95bbSGrant Likely 32bfee95bbSGrant Likely cpus { 33bfee95bbSGrant Likely #address-cells = <1>; 34bfee95bbSGrant Likely #size-cells = <0>; 35bfee95bbSGrant Likely 36bfee95bbSGrant Likely PowerPC,5200@0 { 37bfee95bbSGrant Likely device_type = "cpu"; 38bfee95bbSGrant Likely reg = <0>; 39bfee95bbSGrant Likely d-cache-line-size = <32>; 40bfee95bbSGrant Likely i-cache-line-size = <32>; 41bfee95bbSGrant Likely d-cache-size = <0x4000>; // L1, 16K 42bfee95bbSGrant Likely i-cache-size = <0x4000>; // L1, 16K 43bfee95bbSGrant Likely timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot 44bfee95bbSGrant Likely bus-frequency = <132000000>; // 132 MHz 45bfee95bbSGrant Likely clock-frequency = <396000000>; // 396 MHz 46bfee95bbSGrant Likely }; 47bfee95bbSGrant Likely }; 48bfee95bbSGrant Likely 49bfee95bbSGrant Likely memory { 50bfee95bbSGrant Likely device_type = "memory"; 51bfee95bbSGrant Likely reg = <0x00000000 0x08000000>; // 128MB RAM 52bfee95bbSGrant Likely }; 53bfee95bbSGrant Likely 54bfee95bbSGrant Likely soc@f0000000 { 55bfee95bbSGrant Likely #address-cells = <1>; 56bfee95bbSGrant Likely #size-cells = <1>; 57bfee95bbSGrant Likely compatible = "fsl,mpc5200b-immr"; 58bfee95bbSGrant Likely ranges = <0 0xf0000000 0x0000c000>; 59bfee95bbSGrant Likely reg = <0xf0000000 0x00000100>; 60bfee95bbSGrant Likely bus-frequency = <132000000>;// 132 MHz 61bfee95bbSGrant Likely system-frequency = <0>; // from bootloader 62bfee95bbSGrant Likely 63bfee95bbSGrant Likely cdm@200 { 64bfee95bbSGrant Likely compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 65bfee95bbSGrant Likely reg = <0x200 0x38>; 66bfee95bbSGrant Likely }; 67bfee95bbSGrant Likely 68bfee95bbSGrant Likely mpc5200_pic: interrupt-controller@500 { 69bfee95bbSGrant Likely // 5200 interrupts are encoded into two levels; 70bfee95bbSGrant Likely interrupt-controller; 71bfee95bbSGrant Likely #interrupt-cells = <3>; 72bfee95bbSGrant Likely compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 73bfee95bbSGrant Likely reg = <0x500 0x80>; 74bfee95bbSGrant Likely }; 75bfee95bbSGrant Likely 76bfee95bbSGrant Likely timer@600 { // General Purpose Timer 77bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 78bfee95bbSGrant Likely reg = <0x600 0x10>; 79bfee95bbSGrant Likely interrupts = <1 9 0>; 80bfee95bbSGrant Likely fsl,has-wdt; 81bfee95bbSGrant Likely }; 82bfee95bbSGrant Likely 83bfee95bbSGrant Likely timer@610 { // General Purpose Timer 84bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 85bfee95bbSGrant Likely reg = <0x610 0x10>; 86bfee95bbSGrant Likely interrupts = <1 10 0>; 87bfee95bbSGrant Likely }; 88bfee95bbSGrant Likely 89bfee95bbSGrant Likely timer@620 { // General Purpose Timer 90bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 91bfee95bbSGrant Likely reg = <0x620 0x10>; 92bfee95bbSGrant Likely interrupts = <1 11 0>; 93bfee95bbSGrant Likely }; 94bfee95bbSGrant Likely 95bfee95bbSGrant Likely timer@630 { // General Purpose Timer 96bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 97bfee95bbSGrant Likely reg = <0x630 0x10>; 98bfee95bbSGrant Likely interrupts = <1 12 0>; 99bfee95bbSGrant Likely }; 100bfee95bbSGrant Likely 101bfee95bbSGrant Likely timer@640 { // General Purpose Timer 102bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 103bfee95bbSGrant Likely reg = <0x640 0x10>; 104bfee95bbSGrant Likely interrupts = <1 13 0>; 105bfee95bbSGrant Likely }; 106bfee95bbSGrant Likely 107bfee95bbSGrant Likely timer@650 { // General Purpose Timer 108bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 109bfee95bbSGrant Likely reg = <0x650 0x10>; 110bfee95bbSGrant Likely interrupts = <1 14 0>; 111bfee95bbSGrant Likely }; 112bfee95bbSGrant Likely 113bfee95bbSGrant Likely timer@660 { // General Purpose Timer 114bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 115bfee95bbSGrant Likely reg = <0x660 0x10>; 116bfee95bbSGrant Likely interrupts = <1 15 0>; 117bfee95bbSGrant Likely }; 118bfee95bbSGrant Likely 119bfee95bbSGrant Likely timer@670 { // General Purpose Timer 120bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 121bfee95bbSGrant Likely reg = <0x670 0x10>; 122bfee95bbSGrant Likely interrupts = <1 16 0>; 123bfee95bbSGrant Likely }; 124bfee95bbSGrant Likely 125bfee95bbSGrant Likely rtc@800 { // Real time clock 126bfee95bbSGrant Likely compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 127bfee95bbSGrant Likely reg = <0x800 0x100>; 128bfee95bbSGrant Likely interrupts = <1 5 0 1 6 0>; 129bfee95bbSGrant Likely }; 130bfee95bbSGrant Likely 131bfee95bbSGrant Likely can@900 { 132bfee95bbSGrant Likely compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 133bfee95bbSGrant Likely interrupts = <2 17 0>; 134bfee95bbSGrant Likely reg = <0x900 0x80>; 135bfee95bbSGrant Likely }; 136bfee95bbSGrant Likely 137bfee95bbSGrant Likely can@980 { 138bfee95bbSGrant Likely compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 139bfee95bbSGrant Likely interrupts = <2 18 0>; 140bfee95bbSGrant Likely reg = <0x980 0x80>; 141bfee95bbSGrant Likely }; 142bfee95bbSGrant Likely 143bfee95bbSGrant Likely gpio_simple: gpio@b00 { 144bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 145bfee95bbSGrant Likely reg = <0xb00 0x40>; 146bfee95bbSGrant Likely interrupts = <1 7 0>; 147bfee95bbSGrant Likely gpio-controller; 148bfee95bbSGrant Likely #gpio-cells = <2>; 149bfee95bbSGrant Likely }; 150bfee95bbSGrant Likely 151bfee95bbSGrant Likely gpio_wkup: gpio@c00 { 152bfee95bbSGrant Likely compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 153bfee95bbSGrant Likely reg = <0xc00 0x40>; 154bfee95bbSGrant Likely interrupts = <1 8 0 0 3 0>; 155bfee95bbSGrant Likely gpio-controller; 156bfee95bbSGrant Likely #gpio-cells = <2>; 157bfee95bbSGrant Likely }; 158bfee95bbSGrant Likely 159bfee95bbSGrant Likely spi@f00 { 160bfee95bbSGrant Likely compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 161bfee95bbSGrant Likely reg = <0xf00 0x20>; 162bfee95bbSGrant Likely interrupts = <2 13 0 2 14 0>; 163bfee95bbSGrant Likely }; 164bfee95bbSGrant Likely 165bfee95bbSGrant Likely usb@1000 { 166bfee95bbSGrant Likely compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 167bfee95bbSGrant Likely reg = <0x1000 0x100>; 168bfee95bbSGrant Likely interrupts = <2 6 0>; 169bfee95bbSGrant Likely }; 170bfee95bbSGrant Likely 171bfee95bbSGrant Likely dma-controller@1200 { 172bfee95bbSGrant Likely compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 173bfee95bbSGrant Likely reg = <0x1200 0x80>; 174bfee95bbSGrant Likely interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 175bfee95bbSGrant Likely 3 4 0 3 5 0 3 6 0 3 7 0 176bfee95bbSGrant Likely 3 8 0 3 9 0 3 10 0 3 11 0 177bfee95bbSGrant Likely 3 12 0 3 13 0 3 14 0 3 15 0>; 178bfee95bbSGrant Likely }; 179bfee95bbSGrant Likely 180bfee95bbSGrant Likely xlb@1f00 { 181bfee95bbSGrant Likely compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 182bfee95bbSGrant Likely reg = <0x1f00 0x100>; 183bfee95bbSGrant Likely }; 184bfee95bbSGrant Likely 185bfee95bbSGrant Likely // PSC6 in uart mode 186*abf1e27fSJohn Bonesio console: psc@2c00 { // PSC6 187bfee95bbSGrant Likely compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 188bfee95bbSGrant Likely cell-index = <5>; 189bfee95bbSGrant Likely port-number = <0>; // Logical port assignment 190bfee95bbSGrant Likely reg = <0x2c00 0x100>; 191bfee95bbSGrant Likely interrupts = <2 4 0>; 192bfee95bbSGrant Likely }; 193bfee95bbSGrant Likely 194bfee95bbSGrant Likely eth0: ethernet@3000 { 195bfee95bbSGrant Likely compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 196bfee95bbSGrant Likely reg = <0x3000 0x400>; 197bfee95bbSGrant Likely local-mac-address = [ 00 00 00 00 00 00 ]; 198bfee95bbSGrant Likely interrupts = <2 5 0>; 199bfee95bbSGrant Likely phy-handle = <&phy0>; 200bfee95bbSGrant Likely }; 201bfee95bbSGrant Likely 202bfee95bbSGrant Likely mdio@3000 { 203bfee95bbSGrant Likely #address-cells = <1>; 204bfee95bbSGrant Likely #size-cells = <0>; 205bfee95bbSGrant Likely compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 206bfee95bbSGrant Likely reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 207bfee95bbSGrant Likely interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 208bfee95bbSGrant Likely 209bfee95bbSGrant Likely phy0: ethernet-phy@0 { 210bfee95bbSGrant Likely reg = <0>; 211bfee95bbSGrant Likely }; 212bfee95bbSGrant Likely }; 213bfee95bbSGrant Likely 214bfee95bbSGrant Likely ata@3a00 { 215bfee95bbSGrant Likely compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 216bfee95bbSGrant Likely reg = <0x3a00 0x100>; 217bfee95bbSGrant Likely interrupts = <2 7 0>; 218bfee95bbSGrant Likely }; 219bfee95bbSGrant Likely 220bfee95bbSGrant Likely i2c@3d00 { 221bfee95bbSGrant Likely #address-cells = <1>; 222bfee95bbSGrant Likely #size-cells = <0>; 223bfee95bbSGrant Likely compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 224bfee95bbSGrant Likely reg = <0x3d00 0x40>; 225bfee95bbSGrant Likely interrupts = <2 15 0>; 226bfee95bbSGrant Likely }; 227bfee95bbSGrant Likely 228bfee95bbSGrant Likely i2c@3d40 { 229bfee95bbSGrant Likely #address-cells = <1>; 230bfee95bbSGrant Likely #size-cells = <0>; 231bfee95bbSGrant Likely compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 232bfee95bbSGrant Likely reg = <0x3d40 0x40>; 233bfee95bbSGrant Likely interrupts = <2 16 0>; 234bfee95bbSGrant Likely }; 235bfee95bbSGrant Likely 236bfee95bbSGrant Likely sram@8000 { 237bfee95bbSGrant Likely compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 238bfee95bbSGrant Likely reg = <0x8000 0x4000>; 239bfee95bbSGrant Likely }; 240bfee95bbSGrant Likely }; 241bfee95bbSGrant Likely 242bfee95bbSGrant Likely pci@f0000d00 { 243bfee95bbSGrant Likely #interrupt-cells = <1>; 244bfee95bbSGrant Likely #size-cells = <2>; 245bfee95bbSGrant Likely #address-cells = <3>; 246bfee95bbSGrant Likely device_type = "pci"; 247bfee95bbSGrant Likely compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 248bfee95bbSGrant Likely reg = <0xf0000d00 0x100>; 249bfee95bbSGrant Likely interrupt-map-mask = <0xf800 0 0 7>; 250bfee95bbSGrant Likely interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 251bfee95bbSGrant Likely 0xc000 0 0 2 &media5200_fpga 0 3 252bfee95bbSGrant Likely 0xc000 0 0 3 &media5200_fpga 0 4 253bfee95bbSGrant Likely 0xc000 0 0 4 &media5200_fpga 0 5 254bfee95bbSGrant Likely 255bfee95bbSGrant Likely 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot 256bfee95bbSGrant Likely 0xc800 0 0 2 &media5200_fpga 0 4 257bfee95bbSGrant Likely 0xc800 0 0 3 &media5200_fpga 0 5 258bfee95bbSGrant Likely 0xc800 0 0 4 &media5200_fpga 0 2 259bfee95bbSGrant Likely 260bfee95bbSGrant Likely 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI 261bfee95bbSGrant Likely 0xd000 0 0 2 &media5200_fpga 0 5 262bfee95bbSGrant Likely 263bfee95bbSGrant Likely 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP 264bfee95bbSGrant Likely >; 265bfee95bbSGrant Likely clock-frequency = <0>; // From boot loader 266bfee95bbSGrant Likely interrupts = <2 8 0 2 9 0 2 10 0>; 267bfee95bbSGrant Likely interrupt-parent = <&mpc5200_pic>; 268bfee95bbSGrant Likely bus-range = <0 0>; 269bfee95bbSGrant Likely ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 270bfee95bbSGrant Likely 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 271bfee95bbSGrant Likely 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 272bfee95bbSGrant Likely }; 273bfee95bbSGrant Likely 274bfee95bbSGrant Likely localbus { 275bfee95bbSGrant Likely compatible = "fsl,mpc5200b-lpb","simple-bus"; 276bfee95bbSGrant Likely #address-cells = <2>; 277bfee95bbSGrant Likely #size-cells = <1>; 278bfee95bbSGrant Likely 279bfee95bbSGrant Likely ranges = < 0 0 0xfc000000 0x02000000 280bfee95bbSGrant Likely 1 0 0xfe000000 0x02000000 281bfee95bbSGrant Likely 2 0 0xf0010000 0x00010000 282bfee95bbSGrant Likely 3 0 0xf0020000 0x00010000 >; 283bfee95bbSGrant Likely 284bfee95bbSGrant Likely flash@0,0 { 285bfee95bbSGrant Likely compatible = "amd,am29lv28ml", "cfi-flash"; 286bfee95bbSGrant Likely reg = <0 0x0 0x2000000>; // 32 MB 287bfee95bbSGrant Likely bank-width = <4>; // Width in bytes of the flash bank 288bfee95bbSGrant Likely device-width = <2>; // Two devices on each bank 289bfee95bbSGrant Likely }; 290bfee95bbSGrant Likely 291bfee95bbSGrant Likely flash@1,0 { 292bfee95bbSGrant Likely compatible = "amd,am29lv28ml", "cfi-flash"; 293bfee95bbSGrant Likely reg = <1 0 0x2000000>; // 32 MB 294bfee95bbSGrant Likely bank-width = <4>; // Width in bytes of the flash bank 295bfee95bbSGrant Likely device-width = <2>; // Two devices on each bank 296bfee95bbSGrant Likely }; 297bfee95bbSGrant Likely 298bfee95bbSGrant Likely media5200_fpga: fpga@2,0 { 299bfee95bbSGrant Likely compatible = "fsl,media5200-fpga"; 300bfee95bbSGrant Likely interrupt-controller; 301bfee95bbSGrant Likely #interrupt-cells = <2>; // 0:bank 1:id; no type field 302bfee95bbSGrant Likely reg = <2 0 0x10000>; 303bfee95bbSGrant Likely 304bfee95bbSGrant Likely interrupt-parent = <&mpc5200_pic>; 305bfee95bbSGrant Likely interrupts = <0 0 3 // IRQ bank 0 306bfee95bbSGrant Likely 1 1 3>; // IRQ bank 1 307bfee95bbSGrant Likely }; 308bfee95bbSGrant Likely 309bfee95bbSGrant Likely uart@3,0 { 310bfee95bbSGrant Likely compatible = "ti,tl16c752bpt"; 311bfee95bbSGrant Likely reg = <3 0 0x10000>; 312bfee95bbSGrant Likely interrupt-parent = <&media5200_fpga>; 313bfee95bbSGrant Likely interrupts = <0 0 0 1>; // 2 irqs 314bfee95bbSGrant Likely }; 315bfee95bbSGrant Likely }; 316bfee95bbSGrant Likely}; 317