1/* 2 * Lite5200 board Device Tree Source 3 * 4 * Copyright 2006-2007 Secret Lab Technologies Ltd. 5 * Grant Likely <grant.likely@secretlab.ca> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/* 14 * WARNING: Do not depend on this tree layout remaining static just yet. 15 * The MPC5200 device tree conventions are still in flux 16 * Keep an eye on the linuxppc-dev mailing list for more details 17 */ 18 19/ { 20 model = "fsl,lite5200"; 21 // revision = "1.0"; 22 compatible = "fsl,lite5200\0generic-mpc5200"; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 cpus { 27 #cpus = <1>; 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,5200@0 { 32 device_type = "cpu"; 33 reg = <0>; 34 d-cache-line-size = <20>; 35 i-cache-line-size = <20>; 36 d-cache-size = <4000>; // L1, 16K 37 i-cache-size = <4000>; // L1, 16K 38 timebase-frequency = <0>; // from bootloader 39 bus-frequency = <0>; // from bootloader 40 clock-frequency = <0>; // from bootloader 41 32-bit; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <00000000 04000000>; // 64MB 48 }; 49 50 soc5200@f0000000 { 51 model = "fsl,mpc5200"; 52 revision = "" // from bootloader 53 #interrupt-cells = <3>; 54 device_type = "soc"; 55 ranges = <0 f0000000 f0010000>; 56 reg = <f0000000 00010000>; 57 bus-frequency = <0>; // from bootloader 58 system-frequency = <0>; // from bootloader 59 60 cdm@200 { 61 compatible = "mpc5200-cdm"; 62 reg = <200 38>; 63 }; 64 65 pic@500 { 66 // 5200 interrupts are encoded into two levels; 67 linux,phandle = <500>; 68 interrupt-controller; 69 #interrupt-cells = <3>; 70 device_type = "interrupt-controller"; 71 compatible = "mpc5200-pic"; 72 reg = <500 80>; 73 built-in; 74 }; 75 76 gpt@600 { // General Purpose Timer 77 compatible = "mpc5200-gpt"; 78 device_type = "gpt"; 79 cell-index = <0>; 80 reg = <600 10>; 81 interrupts = <1 9 0>; 82 interrupt-parent = <500>; 83 has-wdt; 84 }; 85 86 gpt@610 { // General Purpose Timer 87 compatible = "mpc5200-gpt"; 88 device_type = "gpt"; 89 cell-index = <1>; 90 reg = <610 10>; 91 interrupts = <1 a 0>; 92 interrupt-parent = <500>; 93 }; 94 95 gpt@620 { // General Purpose Timer 96 compatible = "mpc5200-gpt"; 97 device_type = "gpt"; 98 cell-index = <2>; 99 reg = <620 10>; 100 interrupts = <1 b 0>; 101 interrupt-parent = <500>; 102 }; 103 104 gpt@630 { // General Purpose Timer 105 compatible = "mpc5200-gpt"; 106 device_type = "gpt"; 107 cell-index = <3>; 108 reg = <630 10>; 109 interrupts = <1 c 0>; 110 interrupt-parent = <500>; 111 }; 112 113 gpt@640 { // General Purpose Timer 114 compatible = "mpc5200-gpt"; 115 device_type = "gpt"; 116 cell-index = <4>; 117 reg = <640 10>; 118 interrupts = <1 d 0>; 119 interrupt-parent = <500>; 120 }; 121 122 gpt@650 { // General Purpose Timer 123 compatible = "mpc5200-gpt"; 124 device_type = "gpt"; 125 cell-index = <5>; 126 reg = <650 10>; 127 interrupts = <1 e 0>; 128 interrupt-parent = <500>; 129 }; 130 131 gpt@660 { // General Purpose Timer 132 compatible = "mpc5200-gpt"; 133 device_type = "gpt"; 134 cell-index = <6>; 135 reg = <660 10>; 136 interrupts = <1 f 0>; 137 interrupt-parent = <500>; 138 }; 139 140 gpt@670 { // General Purpose Timer 141 compatible = "mpc5200-gpt"; 142 device_type = "gpt"; 143 cell-index = <7>; 144 reg = <670 10>; 145 interrupts = <1 10 0>; 146 interrupt-parent = <500>; 147 }; 148 149 rtc@800 { // Real time clock 150 compatible = "mpc5200-rtc"; 151 device_type = "rtc"; 152 reg = <800 100>; 153 interrupts = <1 5 0 1 6 0>; 154 interrupt-parent = <500>; 155 }; 156 157 mscan@900 { 158 device_type = "mscan"; 159 compatible = "mpc5200-mscan"; 160 cell-index = <0>; 161 interrupts = <2 11 0>; 162 interrupt-parent = <500>; 163 reg = <900 80>; 164 }; 165 166 mscan@980 { 167 device_type = "mscan"; 168 compatible = "mpc5200-mscan"; 169 cell-index = <1>; 170 interrupts = <1 12 0>; 171 interrupt-parent = <500>; 172 reg = <980 80>; 173 }; 174 175 gpio@b00 { 176 compatible = "mpc5200-gpio"; 177 reg = <b00 40>; 178 interrupts = <1 7 0>; 179 interrupt-parent = <500>; 180 }; 181 182 gpio-wkup@b00 { 183 compatible = "mpc5200-gpio-wkup"; 184 reg = <c00 40>; 185 interrupts = <1 8 0 0 3 0>; 186 interrupt-parent = <500>; 187 }; 188 189 pci@0d00 { 190 #interrupt-cells = <1>; 191 #size-cells = <2>; 192 #address-cells = <3>; 193 device_type = "pci"; 194 compatible = "mpc5200-pci"; 195 reg = <d00 100>; 196 interrupt-map-mask = <f800 0 0 7>; 197 interrupt-map = <c000 0 0 1 500 0 0 3 198 c000 0 0 2 500 0 0 3 199 c000 0 0 3 500 0 0 3 200 c000 0 0 4 500 0 0 3>; 201 clock-frequency = <0>; // From boot loader 202 interrupts = <2 8 0 2 9 0 2 a 0>; 203 interrupt-parent = <500>; 204 bus-range = <0 0>; 205 ranges = <42000000 0 80000000 80000000 0 20000000 206 02000000 0 a0000000 a0000000 0 10000000 207 01000000 0 00000000 b0000000 0 01000000>; 208 }; 209 210 spi@f00 { 211 device_type = "spi"; 212 compatible = "mpc5200-spi"; 213 reg = <f00 20>; 214 interrupts = <2 d 0 2 e 0>; 215 interrupt-parent = <500>; 216 }; 217 218 usb@1000 { 219 device_type = "usb-ohci-be"; 220 compatible = "mpc5200-ohci\0ohci-be"; 221 reg = <1000 ff>; 222 interrupts = <2 6 0>; 223 interrupt-parent = <500>; 224 }; 225 226 bestcomm@1200 { 227 device_type = "dma-controller"; 228 compatible = "mpc5200-bestcomm"; 229 reg = <1200 80>; 230 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 231 3 4 0 3 5 0 3 6 0 3 7 0 232 3 8 0 3 9 0 3 a 0 3 b 0 233 3 c 0 3 d 0 3 e 0 3 f 0>; 234 interrupt-parent = <500>; 235 }; 236 237 xlb@1f00 { 238 compatible = "mpc5200-xlb"; 239 reg = <1f00 100>; 240 }; 241 242 serial@2000 { // PSC1 243 device_type = "serial"; 244 compatible = "mpc5200-psc-uart"; 245 port-number = <0>; // Logical port assignment 246 cell-index = <0>; 247 reg = <2000 100>; 248 interrupts = <2 1 0>; 249 interrupt-parent = <500>; 250 }; 251 252 // PSC2 in ac97 mode example 253 //ac97@2200 { // PSC2 254 // device_type = "sound"; 255 // compatible = "mpc5200-psc-ac97"; 256 // cell-index = <1>; 257 // reg = <2200 100>; 258 // interrupts = <2 2 0>; 259 // interrupt-parent = <500>; 260 //}; 261 262 // PSC3 in CODEC mode example 263 //i2s@2400 { // PSC3 264 // device_type = "sound"; 265 // compatible = "mpc5200-psc-i2s"; 266 // cell-index = <2>; 267 // reg = <2400 100>; 268 // interrupts = <2 3 0>; 269 // interrupt-parent = <500>; 270 //}; 271 272 // PSC4 in uart mode example 273 //serial@2600 { // PSC4 274 // device_type = "serial"; 275 // compatible = "mpc5200-psc-uart"; 276 // cell-index = <3>; 277 // reg = <2600 100>; 278 // interrupts = <2 b 0>; 279 // interrupt-parent = <500>; 280 //}; 281 282 // PSC5 in uart mode example 283 //serial@2800 { // PSC5 284 // device_type = "serial"; 285 // compatible = "mpc5200-psc-uart"; 286 // cell-index = <4>; 287 // reg = <2800 100>; 288 // interrupts = <2 c 0>; 289 // interrupt-parent = <500>; 290 //}; 291 292 // PSC6 in spi mode example 293 //spi@2c00 { // PSC6 294 // device_type = "spi"; 295 // compatible = "mpc5200-psc-spi"; 296 // cell-index = <5>; 297 // reg = <2c00 100>; 298 // interrupts = <2 4 0>; 299 // interrupt-parent = <500>; 300 //}; 301 302 ethernet@3000 { 303 device_type = "network"; 304 compatible = "mpc5200-fec"; 305 reg = <3000 800>; 306 mac-address = [ 02 03 04 05 06 07 ]; // Bad! 307 interrupts = <2 5 0>; 308 interrupt-parent = <500>; 309 }; 310 311 ata@3a00 { 312 device_type = "ata"; 313 compatible = "mpc5200-ata"; 314 reg = <3a00 100>; 315 interrupts = <2 7 0>; 316 interrupt-parent = <500>; 317 }; 318 319 i2c@3d00 { 320 device_type = "i2c"; 321 compatible = "mpc5200-i2c"; 322 cell-index = <0>; 323 reg = <3d00 40>; 324 interrupts = <2 f 0>; 325 interrupt-parent = <500>; 326 }; 327 328 i2c@3d40 { 329 device_type = "i2c"; 330 compatible = "mpc5200-i2c"; 331 cell-index = <1>; 332 reg = <3d40 40>; 333 interrupts = <2 10 0>; 334 interrupt-parent = <500>; 335 }; 336 sram@8000 { 337 device_type = "sram"; 338 compatible = "mpc5200-sram\0sram"; 339 reg = <8000 4000>; 340 }; 341 }; 342}; 343