1b4e8c8ddSTorez Smith/* 2b4e8c8ddSTorez Smith * Device Tree Source for IBM Embedded PPC 476 Platform 3b4e8c8ddSTorez Smith * 4b4e8c8ddSTorez Smith * Copyright 2010 Torez Smith, IBM Corporation. 5b4e8c8ddSTorez Smith * 6b4e8c8ddSTorez Smith * Based on earlier code: 7b4e8c8ddSTorez Smith * Copyright (c) 2006, 2007 IBM Corp. 8b4e8c8ddSTorez Smith * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> 9b4e8c8ddSTorez Smith * 10b4e8c8ddSTorez Smith * This file is licensed under the terms of the GNU General Public 11b4e8c8ddSTorez Smith * License version 2. This program is licensed "as is" without 12b4e8c8ddSTorez Smith * any warranty of any kind, whether express or implied. 13b4e8c8ddSTorez Smith */ 14b4e8c8ddSTorez Smith 15b4e8c8ddSTorez Smith/dts-v1/; 16b4e8c8ddSTorez Smith 17b4e8c8ddSTorez Smith/memreserve/ 0x01f00000 0x00100000; 18b4e8c8ddSTorez Smith 19b4e8c8ddSTorez Smith/ { 20b4e8c8ddSTorez Smith #address-cells = <2>; 21b4e8c8ddSTorez Smith #size-cells = <1>; 22b4e8c8ddSTorez Smith model = "ibm,iss-4xx"; 23b4e8c8ddSTorez Smith compatible = "ibm,iss-4xx"; 24b4e8c8ddSTorez Smith dcr-parent = <&{/cpus/cpu@0}>; 25b4e8c8ddSTorez Smith 26b4e8c8ddSTorez Smith aliases { 27b4e8c8ddSTorez Smith serial0 = &UART0; 28b4e8c8ddSTorez Smith }; 29b4e8c8ddSTorez Smith 30b4e8c8ddSTorez Smith cpus { 31b4e8c8ddSTorez Smith #address-cells = <1>; 32b4e8c8ddSTorez Smith #size-cells = <0>; 33b4e8c8ddSTorez Smith 34b4e8c8ddSTorez Smith cpu@0 { 35b4e8c8ddSTorez Smith device_type = "cpu"; 36b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 37b4e8c8ddSTorez Smith reg = <0>; 38b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 39b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 40b4e8c8ddSTorez Smith i-cache-line-size = <32>; 41b4e8c8ddSTorez Smith d-cache-line-size = <32>; 42b4e8c8ddSTorez Smith i-cache-size = <32768>; 43b4e8c8ddSTorez Smith d-cache-size = <32768>; 44b4e8c8ddSTorez Smith dcr-controller; 45b4e8c8ddSTorez Smith dcr-access-method = "native"; 46*5c285dd7SRobert P. J. Day status = "okay"; 47b4e8c8ddSTorez Smith }; 48b4e8c8ddSTorez Smith cpu@1 { 49b4e8c8ddSTorez Smith device_type = "cpu"; 50b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 51b4e8c8ddSTorez Smith reg = <1>; 52b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 53b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 54b4e8c8ddSTorez Smith i-cache-line-size = <32>; 55b4e8c8ddSTorez Smith d-cache-line-size = <32>; 56b4e8c8ddSTorez Smith i-cache-size = <32768>; 57b4e8c8ddSTorez Smith d-cache-size = <32768>; 58b4e8c8ddSTorez Smith dcr-controller; 59b4e8c8ddSTorez Smith dcr-access-method = "native"; 60b4e8c8ddSTorez Smith status = "disabled"; 61b4e8c8ddSTorez Smith enable-method = "spin-table"; 62b4e8c8ddSTorez Smith cpu-release-addr = <0 0x01f00100>; 63b4e8c8ddSTorez Smith }; 64b4e8c8ddSTorez Smith cpu@2 { 65b4e8c8ddSTorez Smith device_type = "cpu"; 66b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 67b4e8c8ddSTorez Smith reg = <2>; 68b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 69b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 70b4e8c8ddSTorez Smith i-cache-line-size = <32>; 71b4e8c8ddSTorez Smith d-cache-line-size = <32>; 72b4e8c8ddSTorez Smith i-cache-size = <32768>; 73b4e8c8ddSTorez Smith d-cache-size = <32768>; 74b4e8c8ddSTorez Smith dcr-controller; 75b4e8c8ddSTorez Smith dcr-access-method = "native"; 76b4e8c8ddSTorez Smith status = "disabled"; 77b4e8c8ddSTorez Smith enable-method = "spin-table"; 78b4e8c8ddSTorez Smith cpu-release-addr = <0 0x01f00200>; 79b4e8c8ddSTorez Smith }; 80b4e8c8ddSTorez Smith cpu@3 { 81b4e8c8ddSTorez Smith device_type = "cpu"; 82b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 83b4e8c8ddSTorez Smith reg = <3>; 84b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 85b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 86b4e8c8ddSTorez Smith i-cache-line-size = <32>; 87b4e8c8ddSTorez Smith d-cache-line-size = <32>; 88b4e8c8ddSTorez Smith i-cache-size = <32768>; 89b4e8c8ddSTorez Smith d-cache-size = <32768>; 90b4e8c8ddSTorez Smith dcr-controller; 91b4e8c8ddSTorez Smith dcr-access-method = "native"; 92b4e8c8ddSTorez Smith status = "disabled"; 93b4e8c8ddSTorez Smith enable-method = "spin-table"; 94b4e8c8ddSTorez Smith cpu-release-addr = <0 0x01f00300>; 95b4e8c8ddSTorez Smith }; 96b4e8c8ddSTorez Smith }; 97b4e8c8ddSTorez Smith 98b4e8c8ddSTorez Smith memory { 99b4e8c8ddSTorez Smith device_type = "memory"; 100b4e8c8ddSTorez Smith reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage 101b4e8c8ddSTorez Smith 102b4e8c8ddSTorez Smith }; 103b4e8c8ddSTorez Smith 104b4e8c8ddSTorez Smith MPIC: interrupt-controller { 105b4e8c8ddSTorez Smith compatible = "chrp,open-pic"; 106b4e8c8ddSTorez Smith interrupt-controller; 107b4e8c8ddSTorez Smith dcr-reg = <0xffc00000 0x00030000>; 108b4e8c8ddSTorez Smith #address-cells = <0>; 109b4e8c8ddSTorez Smith #size-cells = <0>; 110b4e8c8ddSTorez Smith #interrupt-cells = <2>; 111b4e8c8ddSTorez Smith 112b4e8c8ddSTorez Smith }; 113b4e8c8ddSTorez Smith 114b4e8c8ddSTorez Smith plb { 115b4e8c8ddSTorez Smith compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ 116b4e8c8ddSTorez Smith #address-cells = <2>; 117b4e8c8ddSTorez Smith #size-cells = <1>; 118b4e8c8ddSTorez Smith ranges; 119b4e8c8ddSTorez Smith clock-frequency = <0>; // Filled in by zImage 120b4e8c8ddSTorez Smith 121b4e8c8ddSTorez Smith POB0: opb { 122b4e8c8ddSTorez Smith compatible = "ibm,opb-4xx", "ibm,opb"; 123b4e8c8ddSTorez Smith #address-cells = <1>; 124b4e8c8ddSTorez Smith #size-cells = <1>; 125b4e8c8ddSTorez Smith /* Wish there was a nicer way of specifying a full 32-bit 126b4e8c8ddSTorez Smith range */ 127b4e8c8ddSTorez Smith ranges = <0x00000000 0x00000001 0x00000000 0x80000000 128b4e8c8ddSTorez Smith 0x80000000 0x00000001 0x80000000 0x80000000>; 129b4e8c8ddSTorez Smith clock-frequency = <0>; // Filled in by zImage 130b4e8c8ddSTorez Smith UART0: serial@40000200 { 131b4e8c8ddSTorez Smith device_type = "serial"; 132b4e8c8ddSTorez Smith compatible = "ns16550a"; 133b4e8c8ddSTorez Smith reg = <0x40000200 0x00000008>; 134b4e8c8ddSTorez Smith virtual-reg = <0xe0000200>; 135b4e8c8ddSTorez Smith clock-frequency = <11059200>; 136b4e8c8ddSTorez Smith current-speed = <115200>; 137b4e8c8ddSTorez Smith interrupt-parent = <&MPIC>; 138b4e8c8ddSTorez Smith interrupts = <0x0 0x2>; 139b4e8c8ddSTorez Smith }; 140b4e8c8ddSTorez Smith }; 141b4e8c8ddSTorez Smith }; 142b4e8c8ddSTorez Smith 143b4e8c8ddSTorez Smith nvrtc { 144b4e8c8ddSTorez Smith compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; 145b4e8c8ddSTorez Smith reg = <0 0xEF703000 0x2000>; 146b4e8c8ddSTorez Smith }; 147b4e8c8ddSTorez Smith iss-block { 148b4e8c8ddSTorez Smith compatible = "ibm,iss-sim-block-device"; 149b4e8c8ddSTorez Smith reg = <0 0xEF701000 0x1000>; 150b4e8c8ddSTorez Smith }; 151b4e8c8ddSTorez Smith 152b4e8c8ddSTorez Smith chosen { 15378e5dfeaSRob Herring stdout-path = "/plb/opb/serial@40000200"; 154b4e8c8ddSTorez Smith }; 155b4e8c8ddSTorez Smith}; 156