12fc8483fSLey Foon Tanmenu "Platform options" 22fc8483fSLey Foon Tan 32fc8483fSLey Foon Tancomment "Memory settings" 42fc8483fSLey Foon Tan 52fc8483fSLey Foon Tanconfig NIOS2_MEM_BASE 62fc8483fSLey Foon Tan hex "Memory base address" 72fc8483fSLey Foon Tan default "0x00000000" 82fc8483fSLey Foon Tan help 92fc8483fSLey Foon Tan This is the physical address of the memory that the kernel will run 102fc8483fSLey Foon Tan from. This address is used to link the kernel and setup initial memory 112fc8483fSLey Foon Tan management. You should take the raw memory address without any MMU 122fc8483fSLey Foon Tan or cache bits set. 132fc8483fSLey Foon Tan Please not that this address is used directly so you have to manually 142fc8483fSLey Foon Tan do address translation if it's connected to a bridge. 152fc8483fSLey Foon Tan 162fc8483fSLey Foon Tancomment "Device tree" 172fc8483fSLey Foon Tan 182fc8483fSLey Foon Tanconfig NIOS2_DTB_AT_PHYS_ADDR 192fc8483fSLey Foon Tan bool "DTB at physical address" 202fc8483fSLey Foon Tan default n 212fc8483fSLey Foon Tan help 222fc8483fSLey Foon Tan When enabled you can select a physical address to load the dtb from. 232fc8483fSLey Foon Tan Normally this address is passed by a bootloader such as u-boot but 242fc8483fSLey Foon Tan using this you can use a devicetree without a bootloader. 252fc8483fSLey Foon Tan This way you can store a devicetree in NOR flash or an onchip rom. 262fc8483fSLey Foon Tan Please note that this address is used directly so you have to manually 272fc8483fSLey Foon Tan do address translation if it's connected to a bridge. Also take into 282fc8483fSLey Foon Tan account that when using an MMU you'd have to ad 0xC0000000 to your 292fc8483fSLey Foon Tan address 302fc8483fSLey Foon Tan 312fc8483fSLey Foon Tanconfig NIOS2_DTB_PHYS_ADDR 322fc8483fSLey Foon Tan hex "DTB Address" 332fc8483fSLey Foon Tan depends on NIOS2_DTB_AT_PHYS_ADDR 342fc8483fSLey Foon Tan default "0xC0000000" 352fc8483fSLey Foon Tan help 362fc8483fSLey Foon Tan Physical address of a dtb blob. 372fc8483fSLey Foon Tan 382fc8483fSLey Foon Tanconfig NIOS2_DTB_SOURCE_BOOL 392fc8483fSLey Foon Tan bool "Compile and link device tree into kernel image" 402fc8483fSLey Foon Tan default n 412fc8483fSLey Foon Tan help 422fc8483fSLey Foon Tan This allows you to specify a dts (device tree source) file 432fc8483fSLey Foon Tan which will be compiled and linked into the kernel image. 442fc8483fSLey Foon Tan 452fc8483fSLey Foon Tanconfig NIOS2_DTB_SOURCE 462fc8483fSLey Foon Tan string "Device tree source file" 472fc8483fSLey Foon Tan depends on NIOS2_DTB_SOURCE_BOOL 482fc8483fSLey Foon Tan default "" 492fc8483fSLey Foon Tan help 502fc8483fSLey Foon Tan Absolute path to the device tree source (dts) file describing your 512fc8483fSLey Foon Tan system. 522fc8483fSLey Foon Tan 532fc8483fSLey Foon Tancomment "Nios II instructions" 542fc8483fSLey Foon Tan 55*a89988a6SMarek Vasutconfig NIOS2_ARCH_REVISION 56*a89988a6SMarek Vasut int "Select Nios II architecture revision" 57*a89988a6SMarek Vasut range 1 2 58*a89988a6SMarek Vasut default 1 59*a89988a6SMarek Vasut help 60*a89988a6SMarek Vasut Select between Nios II R1 and Nios II R2 . The architectures 61*a89988a6SMarek Vasut are binary incompatible. Default is R1 . 62*a89988a6SMarek Vasut 632fc8483fSLey Foon Tanconfig NIOS2_HW_MUL_SUPPORT 642fc8483fSLey Foon Tan bool "Enable MUL instruction" 652fc8483fSLey Foon Tan default n 662fc8483fSLey Foon Tan help 672fc8483fSLey Foon Tan Set to true if you configured the Nios II to include the MUL 682fc8483fSLey Foon Tan instruction. This will enable the -mhw-mul compiler flag. 692fc8483fSLey Foon Tan 702fc8483fSLey Foon Tanconfig NIOS2_HW_MULX_SUPPORT 712fc8483fSLey Foon Tan bool "Enable MULX instruction" 722fc8483fSLey Foon Tan default n 732fc8483fSLey Foon Tan help 742fc8483fSLey Foon Tan Set to true if you configured the Nios II to include the MULX 752fc8483fSLey Foon Tan instruction. Enables the -mhw-mulx compiler flag. 762fc8483fSLey Foon Tan 772fc8483fSLey Foon Tanconfig NIOS2_HW_DIV_SUPPORT 782fc8483fSLey Foon Tan bool "Enable DIV instruction" 792fc8483fSLey Foon Tan default n 802fc8483fSLey Foon Tan help 812fc8483fSLey Foon Tan Set to true if you configured the Nios II to include the DIV 822fc8483fSLey Foon Tan instruction. Enables the -mhw-div compiler flag. 832fc8483fSLey Foon Tan 842fc8483fSLey Foon Tanconfig NIOS2_FPU_SUPPORT 852fc8483fSLey Foon Tan bool "Custom floating point instr support" 862fc8483fSLey Foon Tan default n 872fc8483fSLey Foon Tan help 882fc8483fSLey Foon Tan Enables the -mcustom-fpu-cfg=60-1 compiler flag. 892fc8483fSLey Foon Tan 902fc8483fSLey Foon Tanconfig NIOS2_CI_SWAB_SUPPORT 912fc8483fSLey Foon Tan bool "Byteswap custom instruction" 922fc8483fSLey Foon Tan default n 932fc8483fSLey Foon Tan help 942fc8483fSLey Foon Tan Use the byteswap (endian converter) Nios II custom instruction provided 952fc8483fSLey Foon Tan by Altera and which can be enabled in QSYS builder. This accelerates 962fc8483fSLey Foon Tan endian conversions in the kernel (e.g. ntohs). 972fc8483fSLey Foon Tan 982fc8483fSLey Foon Tanconfig NIOS2_CI_SWAB_NO 992fc8483fSLey Foon Tan int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT 1002fc8483fSLey Foon Tan default 0 1012fc8483fSLey Foon Tan help 1022fc8483fSLey Foon Tan Number of the instruction as configured in QSYS Builder. 1032fc8483fSLey Foon Tan 1042fc8483fSLey Foon Tancomment "Cache settings" 1052fc8483fSLey Foon Tan 1062fc8483fSLey Foon Tanconfig CUSTOM_CACHE_SETTINGS 1072fc8483fSLey Foon Tan bool "Custom cache settings" 1082fc8483fSLey Foon Tan help 1092fc8483fSLey Foon Tan This option allows you to tweak the cache settings used during early 1102fc8483fSLey Foon Tan boot (where the information from device tree is not yet available). 1112fc8483fSLey Foon Tan There should be no reason to change these values. Linux will work 1122fc8483fSLey Foon Tan perfectly fine, even if the Nios II is configured with smaller caches. 1132fc8483fSLey Foon Tan 1142fc8483fSLey Foon Tan Say N here unless you know what you are doing. 1152fc8483fSLey Foon Tan 1162fc8483fSLey Foon Tanconfig NIOS2_DCACHE_SIZE 1172fc8483fSLey Foon Tan hex "D-Cache size" if CUSTOM_CACHE_SETTINGS 1182fc8483fSLey Foon Tan range 0x200 0x10000 1192fc8483fSLey Foon Tan default "0x800" 1202fc8483fSLey Foon Tan help 1212fc8483fSLey Foon Tan Maximum possible data cache size. 1222fc8483fSLey Foon Tan 1232fc8483fSLey Foon Tanconfig NIOS2_DCACHE_LINE_SIZE 1242fc8483fSLey Foon Tan hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS 1252fc8483fSLey Foon Tan range 0x10 0x20 1262fc8483fSLey Foon Tan default "0x20" 1272fc8483fSLey Foon Tan help 1282fc8483fSLey Foon Tan Minimum possible data cache line size. 1292fc8483fSLey Foon Tan 1302fc8483fSLey Foon Tanconfig NIOS2_ICACHE_SIZE 1312fc8483fSLey Foon Tan hex "I-Cache size" if CUSTOM_CACHE_SETTINGS 1322fc8483fSLey Foon Tan range 0x200 0x10000 1332fc8483fSLey Foon Tan default "0x1000" 1342fc8483fSLey Foon Tan help 1352fc8483fSLey Foon Tan Maximum possible instruction cache size. 1362fc8483fSLey Foon Tan 1372fc8483fSLey Foon Tanendmenu 138